Chip Synthesis Workshop 1392
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Table of Contents Day 1: Pre-Synthesis Processes Introduction & Overview Workshop Goal.................................................................................................................. i-3 Workshop Prerequisites...................................................................................................... i-4 Workshop Target Audience ................................................................................................ i-5 Workshop Agenda.............................................................................................................. i-6
Unit 1: Introduction to Synthesis Unit Objectives .................................................................................................................. 1-2 Just What Is “Synthesis”? .................................................................................................. 1-3 Synthesis is Constraint-Driven............................................................................................ 1-7 Synthesis is Path-Based...................................................................................................... 1-8 Chip Synthesis Process ..................................................................................................... 1-9 Design Compiler Interfaces............................................................................................... 1-10 Need Help? .................................................................................................................... 1-11 Search in Acrobat Reader ................................................................................................ 1-12 Module Synthesis Roadmap ............................................................................................. 1-13 Analyze, Elaborate - Read................................................................................................ 1-14
Unit 2: Setup, Libraries, and Objects Chapter O verview.............................................................................................................. 2-3 Synthesis Review ............................................................................................................... 2-4 Technology Library............................................................................................................ 2-5 Target Library.................................................................................................................... 2-6 Link Library Variable ......................................................................................................... 2-7 Use link to Resolve Design References ............................................................................... 2-9 The search_path Variable ................................................................................................. 2-10 Design Compiler Interfaces............................................................................................... 2-13 Design Compiler Three Initialization Files.......................................................................... 2-14 .synopsys_dc.setup File: Example..................................................................................... 2-15 .synopsys_dc_setup: Tcl and dcsh Mode.......................................................................... 2-16 Design Objects: VHDL Perspective.................................................................................. 2-18 Design Objects: Verilog Perspective ................................................................................. 2-19
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Table of Contents Design Objects: Schematic Perspective............................................................................. 2-20 Multiple Objects with the Same Name.............................................................................. 2-21 The get Command............................................................................................................ 2-22 What Is a List?................................................................................................................. 2-23 Other Handy List Commands........................................................................................... 2-25 Finding objects with dc_shell-t.......................................................................................... 2-26 Appendix - Synopsys DesignWare................................................................................... 2-32
Unit 3: Partitioning for Synthesis What is Partitioning?........................................................................................................... 3-3 Why Partition a Design? .................................................................................................... 3-4 Partitioning Within the HDL Descrip tion.............................................................................. 3-5 Eliminate Unnecessary Hierarchy........................................................................................ 3-6 No Hierarchy Dividing Combinational Paths........................................................................ 3-7 Partition at Register Boundaries .......................................................................................... 3-9 Avoid Glue Logic: Example .............................................................................................. 3-10 Balance Block Size With Run Times ................................................................................. 3-12 Separate Core Logic, Pads, Clocks, and JTAG ................................................................ 3-14 Partitioning Within Design Compiler.................................................................................. 3-15 The group Command ....................................................................................................... 3-16 The ungroup Command.................................................................................................... 3-17 Partitioning Strategies for Synthesis................................................................................... 3-19
Unit 4: Coding for Synthesis The Importance of Quality of Source .................................................................................. 4-3 RTL Coding Guide............................................................................................................. 4-4 The Big Picture: Think Hardware! ...................................................................................... 4-5 The Big Picture: Think Synchronous! ................................................................................. 4-6 The Big Picture: Think RTL! .............................................................................................. 4-7 RTL Synthesis Cookbook .................................................................................................. 4-8 Synthesis of if Statements............................................................................................... 4-9 if-else Statements ............................................................................................................. 4-10 if Statements and Latches ................................................................................................. 4-12 if-then-elseif Statements.................................................................................................... 4-13 Priority Interrupt Circuit - Synthesis Results ...................................................................... 4-15 31833-000-S16B
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Table of Contents When NOT to Use if-then-elseif ...................................................................................... 4-16 Synthesis of case Statements ........................................................................................... 4-17 case Statements .............................................................................................................. 4-18 Synthesis of loop Statements ............................................................................................ 4-25 Unrolling Loops ............................................................................................................... 4-26 Tradeoffs with Loops....................................................................................................... 4-27 Hardware Result .............................................................................................................. 4-28 Recoded Loop................................................................................................................. 4-29 Synthesis of Flip-Flops..................................................................................................... 4-30 Inferring Sequential Devices.............................................................................................. 4-31 Synthesis of Arithmetic Circuits......................................................................................... 4-34 Inferring Arithmetic Parts.................................................................................................. 4-35 DesignWare Arithmetic Resources.................................................................................... 4-36 DesignWare Implementation Selection.............................................................................. 4-37 Implying a Structure by Operand Placement...................................................................... 4-39 Verilog Preprocessor Directive ......................................................................................... 4-41 Appendix: Verilog Inference and Instantiation.................................................................... 4-44
Day 2: Constraining the Design Unit 5: Timing and Area RTL Block Synthesis.......................................................................................................... 5-3 Specifying an Area Goal..................................................................................................... 5-4 Timing Goals: Synchronous Designs.................................................................................... 5-5 Defining a Clock ................................................................................................................ 5-7 Defining a Clock in Design Compiler................................................................................... 5-8 Timing Goals: Synchronous Designs, I/O............................................................................. 5-9 Constraining the Input Paths ............................................................................................. 5-10 set_input_delay: Effect on Input Paths............................................................................... 5-13 Constraining Output Paths of a Design.............................................................................. 5-14 set_output_delay: Effect on Output Paths.......................................................................... 5-17 Useful Commands............................................................................................................ 5-19
Unit 6: Environmental Attributes RTL Block Synthesis.......................................................................................................... 6-3 31833-000-S16B
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Table of Contents Constraining for Timing— What’s Missing? ........................................................................ 6-4 Describing Environmental Attributes.................................................................................... 6-5 Modeling Capacitive Load ................................................................................................. 6-6 set_load examples.............................................................................................................. 6-7 Modeling Input Drive Strength............................................................................................ 6-8 set_driving_cell Examples .................................................................................................. 6-9 Variations in cell delays .................................................................................................... 6-10 Operating Conditions ....................................................................................................... 6-11 Net delays ....................................................................................................................... 6-14 What is a Wire load model? ............................................................................................ 6-15 Specifying Wire Loads in Design Compiler ....................................................................... 6-17 Wireload Model Mode .................................................................................................... 6-18 Check Your Constraints .................................................................................................. 6-19 Appendix - Create an Operating Condition....................................................................... 6-25
Unit 7: Time and Load Budgeting RTL Block Synthesis.......................................................................................................... 7-3 Time Budgeting .................................................................................................................. 7-4 Load Budgeting.................................................................................................................. 7-8 Summary of Describing Constraints.................................................................................. 7-14
Unit 8: Timing Analysis Does Your Design Meet its Goals?..................................................................................... 8-3 Timing Analysis: What Tool Do I Use? .............................................................................. 8-4 Static Timing Analysis......................................................................................................... 8-5 Timing Paths in Design Compiler......................................................................................... 8-6 Organizing Timing Paths Into Groups .................................................................................. 8-7 Schematic Converted to a Timing Graph........................................................................... 8-10 Components of Static Timing Analysis .............................................................................. 8-11 How DesignTime Calculates Delays ................................................................................. 8-12 Non-Linear Delay Model................................................................................................. 8-13 Wire Delay Calculations and Topology............................................................................. 8-15 Operating Conditions ....................................................................................................... 8-16 Edge Sensitivity in Path Delays ......................................................................................... 8-17 Setup Relationship Between Flip-Flops............................................................................. 8-18 31833-000-S16B
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Table of Contents DesignTime Timing Reports.............................................................................................. 8-19 Timing Report: Path Information Section........................................................................... 8-20 Timing Report: Path Delay Section.................................................................................... 8-21 Timing Report: Path Required Section............................................................................... 8-22 Timing Report: Summary Section...................................................................................... 8-23 Timing Report: Options .................................................................................................... 8-24 Timing Analysis: Diagnose Synthesis Results...................................................................... 8-25
Unit 9: DC Shell – Tcl Interface What is Tcl?....................................................................................................................... 9-4 Why Tcl? .......................................................................................................................... 9-5 Converting from dc_shell to dc_shell –t............................................................................... 9-6 Executing DC-Tcl Script.................................................................................................... 9-7 Getting Help....................................................................................................................... 9-8 Comments in DC-Tcl....................................................................................................... 9-11 Nesting Commands and Quoting ...................................................................................... 9-12 Using Wildcards............................................................................................................... 9-13 Tcl Data Types ................................................................................................................ 9-14 Using Variables................................................................................................................ 9-15 Arithmetic Expressions ..................................................................................................... 9-17 Using Lists in dc_shell-t.................................................................................................... 9-18 Definitions: Objects and Attributes.................................................................................... 9-19 Definitions: Collections & Collection Handle ..................................................................... 9-20 Creating Collections ......................................................................................................... 9-21 Manipulating Collections................................................................................................... 9-23 Filtering Collections.......................................................................................................... 9-26 Running dc_shell –t Interactively ....................................................................................... 9-27
Day 3: Synthesizing the Design Unit 10: Timing Revisited Timing Goals: Part Two.................................................................................................... 10-5 Modeling Clock Trees...................................................................................................... 10-6 Modeling Uncertainty on Clock Edges.............................................................................. 10-7 set_clock_uncertainty and Setup Timing............................................................................ 10-8 31833-000-S16B
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Table of Contents Modeling Source Latency................................................................................................. 10-9 Pre/Post Layout Clock................................................................................................... 10-10 Multiple Clocks - Synchronous....................................................................................... 10-11 Synchronous Multiple Clock Designs.............................................................................. 10-12 Creating a Virtual Clock................................................................................................. 10-14 Timing Goals for Multiple Clock Designs ........................................................................ 10-15 Hints for Multiple Clock Designs ................................................................................... 10-20 Multiple Clocks - Asynchronous..................................................................................... 10-21 Asynchronous Multiple Clock Designs............................................................................ 10-22 Synthesizing with Asynchronous Clocks.......................................................................... 10-23 The set_false_path command.......................................................................................... 10-24 Timing Goals Summary................................................................................................... 10-26 check_timing.................................................................................................................. 10-27 Appendix: Multi-Cycle Behavior..................................................................................... 10-29
Unit 11: Optimization Three Phases of Optimization........................................................................................... 11-3 Architectural Optimization ................................................................................................ 11-4 Arithmetic Operators........................................................................................................ 11-5 DesignWare Implementation Selection.............................................................................. 11-6 Other High-Level Optimizations........................................................................................ 11-8 Sharing Common Sub Expressions ................................................................................... 11-9 Coding To Force Sharing ............................................................................................... 11-10 Resource Sharing: Example ............................................................................................ 11-11 Operator Reordering ...................................................................................................... 11-13 Reordering Operators for Fast Design ............................................................................ 11-14 High-Level Synthesis is Constraint-Driven ...................................................................... 11-15 Logic-Level Optimization ............................................................................................... 11-16 What is Structuring? ...................................................................................................... 11-18 What is Flattening? ........................................................................................................ 11-19 Structuring vs. Flattening................................................................................................. 11-20 Three Phases of Optimization......................................................................................... 11-21 Combinational Mapping................................................................................................. 11-22 Sequential Mapping ....................................................................................................... 11-23 Fixing Design Rule Violations.......................................................................................... 11-24
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Table of Contents Unit 12: Compile Strategies Compile Completion ........................................................................................................ 12-3 User Interrupt.................................................................................................................. 12-5 Compile Report ............................................................................................................... 12-6 Compile Strategies........................................................................................................... 12-7 Constraint and Timing Analysis ......................................................................................... 12-8 Things to Look for........................................................................................................... 12-9 Use Re-Compile ............................................................................................................ 12-12 Change the Effort Level.................................................................................................. 12-13 Use Incremental Mapping............................................................................................... 12-16 When You Have Design Rule Violations ........................................................................ 12-19 What if You Have Hold Time Violations? ...................................................................... 12-20 Checking For Hold Time Violations ............................................................................... 12-23 Use Simultaneous Min-Max .......................................................................................... 12-24 Apply set_input_delay For Hold Time ........................................................................... 12-25 Apply set_output_delay For Hold Time .......................................................................... 12-26 Calculation of set_output_delay...................................................................................... 12-27 Fixing Hold Violations .................................................................................................... 12-28
Unit 13: Compiling a Hierarchical Design Compiling a Hierarchical Design— Under the Hood........................................................... 13-3 Compiling a Hierarchy ..................................................................................................... 13-4 First Phase of Compile ..................................................................................................... 13-5 Second Phase of Compile ................................................................................................ 13-6 Resolving Multiple Instances............................................................................................. 13-7 Designs Instantiated More Than Once .............................................................................. 13-8 check_design................................................................................................................... 13-9 Methods to Resolve Multiple Instances........................................................................... 13-10 Method #1: uniquify ....................................................................................................... 13-11 Method 2: compile + dont_touch.................................................................................... 13-13 Using set_dont_touch..................................................................................................... 13-15 uniquify vs. compile + dont_touch.................................................................................. 13-16
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Table of Contents Unit 14: DC-Tcl Procedures Control Flow: Examples................................................................................................... 14-3 Looping Structures........................................................................................................... 14-4 Tcl Procedures................................................................................................................. 14-6 Scope of Variables........................................................................................................... 14-8 Procedure Information...................................................................................................... 14-9 Tcl Procedure Example .................................................................................................. 14-10
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Table of Contents Day 4: Post-Synthesis Processes Unit 15: Compiling a Large Design Techniques for Compiling a Hierarchical Design ................................................................ 15-3 Hierarchical Compile Techniques: Types........................................................................... 15-4 Top-Down Compile Methodology.................................................................................... 15-5 Advantages of Top-Down................................................................................................ 15-6 Simple Compile Mode ..................................................................................................... 15-7 Hierarchical Compile Techniques...................................................................................... 15-8 Bottom-Up Compile Methodology................................................................................... 15-9 Pros & Cons of Bottom-Up Compile ............................................................................. 15-12 Techniques for the Second-Pass Compile ....................................................................... 15-14 Problems After the First-Pass Compile ........................................................................... 15-15 Use report_constraint -all............................................................................................... 15-16 Use report_timing........................................................................................................... 15-17 Build a New Design Budget............................................................................................ 15-22 characterize.................................................................................................................... 15-23 Appendix - Design Budgeter .......................................................................................... 15-30
Unit 16: Design Exploration Traditional Reactive Flow................................................................................................. 16-4 Proactive Design Methodology......................................................................................... 16-6 Design Exploration........................................................................................................... 16-7 Typical Compile Script (Basic) ....................................................................................... 16-11 Special WLM for Ports.................................................................................................. 16-13 set_max_capacitance ..................................................................................................... 16-15 set_max_transition.......................................................................................................... 16-16 set_max_fanout.............................................................................................................. 16-17 Fanout Loads................................................................................................................. 16-18 Fastest Runtimes for Design Exploration......................................................................... 16-21 Scenarios: Exploring Subdesigns..................................................................................... 16-23 I/O Timing Constraint Options........................................................................................ 16-28 Exploring Combinational Paths ....................................................................................... 16-30 User-Defined Path Groups ............................................................................................. 16-31
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Table of Contents Path Groups vs Critical Range........................................................................................ 16-34
Unit 17: Synthesizing for Test Chip Defects: They’re Not My Fault! ............................................................................... 17-3 Manufacturing Defects...................................................................................................... 17-4 Why Test for Manufacturing Defects? .............................................................................. 17-5 How Is Manufacturing Test Performed? ........................................................................... 17-6 The Stuck-At Fault Model ............................................................................................... 17-7 Controllability................................................................................................................... 17-9 Observability.................................................................................................................. 17-10 Fault Coverage .............................................................................................................. 17-11 Testing a Multistage, Pipelined Design............................................................................. 17-12 Scan Chains Help .......................................................................................................... 17-13 Use One-Pass Scan Synthesis ........................................................................................ 17-15 DFT Checking: Example ................................................................................................ 17-17 Testability Violation: Example......................................................................................... 17-18 Running ATPG............................................................................................................... 17-19 What Is DFTC?............................................................................................................. 17-20 Test Tools Summary ...................................................................................................... 17-22 Synthesizing for Test Summary ......................................................................................... 17-2
Unit 18: Conclusion Some Thoughts on Coding ............................................................................................... 18-3 Synthesis Quality Depends on Algorithms!........................................................................ 18-4 Classic Algorithms, Architectures, & Tradeoffs ................................................................. 18-5 Reflections on Synthesis: .................................................................................................. 18-6 Pre-Compile Checklist..................................................................................................... 18-7 What Do You Do First? .................................................................................................. 18-8 Compile Strategy ............................................................................................................. 18-9 Timing Analysis to Diagnose the Problem........................................................................ 18-10 Need More Training? .................................................................................................... 18-12 Advanced Chip Synthesis............................................................................................... 18-13 Coding Styles for Synthesis ............................................................................................ 18-14 Need More Information or Help? .................................................................................. 18-15 Synopsys on the World Wide Web ................................................................................ 18-16 31833-000-S16B
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Table of Contents How to Use solv-NET! ................................................................................................. 18-17 Human Sources for Information and Help ....................................................................... 18-18 Other Sources for Information and Help ......................................................................... 18-19
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i-1 For BHNEC internal use only.
Chip Synthesis Workshop
Synopsys Customer Education Services © 2000 Synopsys, Inc. All Rights Reserved Introduction Synopsys 31833-000-S16
For BHNEC internal use only.
Chip 31833-000-S16 Synthesis Workshop
First Things First ?
Instructor Introduction
?
Student Guide
?
Lab Guide
?
Measurement of Learning Objectives
i-2
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Workshop Goal
i-3
Acquire the basic skills to synthesize a design using Synopsys Design Compiler
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Workshop Prerequisites ?
Understanding of digital IC design
?
Some knowledge of Verilog or VHDL
?
Familiarity with UNIX and X-Windows
?
Familiarity with a Unix-based text editor
i-4
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Workshop Target Audience
i-5
?
Board, FPGA, or ASIC-level Digital Designers
?
Some Verilog or VHDL knowledge
?
Little or no formal experience with Design Compiler
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
4 Day Workshop Agenda
i-6
Day
1
Pre-synthesis Processes
Day
2
Constraining the Design
Day
3
Synthesizing the Design
Day
4
Post-synthesis Processes
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Icons Used in this Workshop
i-7
Lab Exercise
Caution
Question
Note
Hint, Tip, or Suggestion
Remember
Checklist
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Abbreviations and Acronyms: Exercise
Acronym
Meaning
Acronym
DC DC
HDL HDL
RTL RTL
GTECH GTECH
SOLD SOLD
SDF SDF
PDEF PDEF
DFT DFT
ATPG ATPG
Tcl Tcl
i-8
Meaning
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 1 DAY 1
Unit
1-1
Topic
1
Introduction to Synthesis
2
Setup, Libraries, and Objects
3
Partitioning for Synthesis
4
Coding for Synthesis
Lab
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
1-2
After completing this unit you should be able to: ?
List the basic steps of synthesis
?
Describe advantages of synthesis
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Just What Is Synthesis?
1-3
Synthesis is the transformation of an idea into a manufacturable device to carry out an intended function
Introduction to Synthesis Synopsys 31833-000-S16
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Levels of Abstraction Idea Idea captured on back of envelope
Functional Graphical or textual description
1-4 Register Transfer Architectural HDL
Gate-Level Netlist
Our focus will be here Behavioral HDL and simulation language
Physical Device Silicon Introduction to Synthesis
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For Our Purposes, Synthesis is
1-5
Synthesis = Translation + Optimization + Mapping residue = 16’h0000; if (high_bits == 2’b10) residue = state_table[index]; else state_table[index] = 16’h0000;
Translate
HDL Source Optimize + Map
Generic Boolean (GTECH)
Target Technology Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Why Synthesis?
1-6 Reusability
Design Tricks DC knows plenty, tries them in context of loads, fanouts, library limitations
Parameterized code; Building-block approach; Retarget new libraries;
Why Me?
Abstraction Focus on high-level issues; tool & computer do dirty work to meet constraints
Verifiable Validate, implement, & verify in same language, Less error-prone entry
Portability IEEE standards; HDL portable across tools; technology-independent designs
Prestige
Productivity 6
How else to do 10 gates in 6 months?
Impress friends; hot skill on resume; job security; wealth and fame
Introduction to Synthesis Synopsys 31833-000-S16
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Synthesis is Constraint-Driven
1-7
Large
• Area
• • Small Short
• Delay
•
• High
You set the goals (through constraints) Design Compiler optimizes the design to meet your goals Introduction to Synthesis Synopsys 31833-000-S16
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Synthesis is Path-Based
1-8
Design Compiler uses Static Timing Analysis (STA) to calculate the timing of the paths in the design.
MY_DESIGN A
CLK
D Q FF2 QB
D Q FF3 QB
Z
How many timing paths do you see in MY_DESIGN?
Introduction to Synthesis Synopsys 31833-000-S16
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Chip Synthesis Process
1-9
Chip Specification
Integrate Blocks
Partition Chip
Insert Test
Floorplan
Floorplan
RTL Block Synthesis
Place & Route
Final Verification Introduction to Synthesis Synopsys 31833-000-S16
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Design Compiler Interfaces
1-10
Three ways to interface to Design Compiler (DC): 1
dc_shell-t (DC-Tcl)
2
dc_shell (DCSH)
3
Design Analyzer
4
Design Vision in 2000.11 release Introduction to Synthesis Synopsys 31833-000-S16
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Need Help?
1-11
%SOLD acroread \ $SYNOPSYS/doc/online/top.pdf %alias sman ‘man -M \ $SYNOPSYS/doc/syn/man’ or %setenv MANPATH “${MANPATH}: $SYNOPSYS/doc/syn/man” Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Search in Acrobat Reader
1-12
Search allows you to scan all documents in SOLD
Download Acrobat Reader with Search www.acrobat.com
There are More than 4000 SOLV-IT! articles
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Module Synthesis Roadmap GTECH
target_library
gtech.db
core_slow.db
my_chip.v(hd)
Y=A+B MY_CHIP
MY_CHIP
scripts
mapped
constraints.scr
my_chip.db my_chip.edif
my_chip.db
TRANSLATION
e writ
include
unmapped
DC_MEMORY compile
rea d
read analyze/ elaborate wr it e
HDL source
DC_MEMORY
1-13
OPTIMIZATION + MAPPING Introduction to Synthesis
Synopsys 31833-000-S16
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Analyze, Elaborate - Read mychip.vhd
1-14
analyze -f vhdl mychip.vhd
mychip.v analyzed read -f verilog mychip.v
DC MEMORY
mychip.syn mychip.sim(VHDL) mychip.mra elaborate MYCHIP
Y=A+B MYCHIP write -ouput ./unmapped/mychip.db -hier unmapped mychip.db
Introduction to Synthesis Synopsys 31833-000-S16
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Summary: Exercise
1-15
Synthesis = __________ + __________ + __________
Advantages of Synthesis: ____________________ ____________________ ____________________
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 1: Introduction
1-16 Bring in the design
LAB
25 min
Run through the basic Synthesis Flow using scripts
Constrain the design
Synthesise the design
Inspect the design
Save the design
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Appendix
1-17
Synopsys Physical Synthesis
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Physical Challenge
Wire
Gate
Percentage of Delay
1-18
1.0 ?
0.5 ?
0.25 ?
0.18 ?
Silicon Technology
Introduction to Synthesis Synopsys 31833-000-S16
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Physical Synthesis 0.8?
1-19 0.5? to 0.35?
Logic
Logic
Synthesis
Synthesis
Place & Route
Place & Route
? 0.25?
Physical Synthesis Flow Place & Route
Introduction to Synthesis Synopsys 31833-000-S16
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Synopsys Physical Synthesis
Chip Architect: •Budgeting •Estimation •Floor Planning •IO Placement FlexRoute: •Detailed Top Level Routing •Pin assignment
Micro Controller
M e m o r y
Datapath
Memory Placed Gates Gates
1-20
Module Compiler : •Specialized Datapath Synthesis
Design Compiler : •Logic Synthesis Chip Architect: •Detailed Placement •Coarse Routing
Physical Compiler: •RTL Synthesis & Placement Together
Introduction to Synthesis Synopsys 31833-000-S16
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Agenda: Day 1 DAY 1
Unit
2-1
Topic
1
Introduction to Synthesis
2
Setup, Libraries and Objects
3
Partitioning for Synthesis
4
Coding for Synthesis
Lab
Setup, Libraries, and Objects Synopsys 31833-000-S16
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Unit Measurable Objectives
2-2
After completing this unit, you should be able to:
Specify the target library
Create the setup file for DC
Differentiate between the design objects
Find objects in DCSH mode and Tcl mode
Setup, Libraries, and Objects Synopsys 31833-000-S16
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Chapter Overview
2-3
Technology Libraries
DC Setup File
Design Objects
Setup, Libraries, and Objects Synopsys 31833-000-S16
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Synthesis Review
2-4
Recall the 3 steps involved in synthesis:
Translation
Optimization
Mapping
When DC maps a circuit, how will it know which cell library you are using? How will it know the timing of your cells?
Your ASIC vendor must provide a DC-compatible technology library for synthesis!
Setup, Libraries, and Objects Synopsys 31833-000-S16
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Technology Library
2-5
Example of a cell description in .lib Format Cell name cell ( OR2_3 ) { area : 8.000 ; Cell Area pin ( Y ) { direction : output; timing ( ) { related_pin : "A" ; timing_sense : positive_unate ; rise_propagation (drive_3_table_1) { values ("0.2616, 0.2608, 0.2831,..) } rise_transition (drive_3_table_2) { values ("0.0223, 0.0254, ...) . . . . function : "(A | B)"; max_capacitance : 1.14810 ; min_capacitance : 0.00220 ; } pin ( A ) { direction : input; capacitance : 0.012000; . . . .
t
A Y
Y=A|B B
Pin A -> Pin Y nominal delays (look-up table)
Pin Y functionality Design Rules for Output Pin Electrical Characteristics of Input Pins Setup, Libraries, and Objects
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Target Library Variable
2-6
The Target Library is the library used by Design Compiler for building a circuit
During mapping, DC will
choose functionally-correct gates from this library
calculate the timing of the circuit using vendor-supplied timing data for these gates
target_library is a reserved variable in DC
Set it to point to the library file(s) provided by your silicon vendor
set target_library my_tech.db
Setup, Libraries, and Objects Synopsys 31833-000-S16
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Link Library Variable
2-7
Used to resolve design references
set link_library {* my_tech.db} DC Memory “*”
Target Library
First DC searches the memory and then the library files specified in the link_library variable
Second DC searches the all paths defined in the search_path variable
Setup, Libraries, and Objects Synopsys 31833-000-S16
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Example
2-8
set target_library my_tech.db set link_library {* my_tech.db} ALU.v
bob/
my_tech.db source/
DECODE.db
TOP.v ALU.v
module ALU (A,B,OUT1); input A, B; output [1:0] OUT1; always @(A or B) begin . . .
UNIX% dc_shell-t dc_shell-t> read_verilog source/ALU.v Loading Loading Loading Loading Current
db file standard.sldb db file gtech.db db file my_tech.db verilog file source/ALU.v design is now ALU Setup, Libraries, and Objects
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Use link to Resolve Design References
2-9
set target_library my_tech.db set link_library {* my_tech.db} TOP.v
bob/
my_tech.db source/
DECODE.db
TOP.v ALU.v
module TOP (A,B,OUT1); input A, B; output [1:0] OUT1; ALU U1 (.AIN (A), . . DECODE U2 (.A (BUS0), . .
dc_shell-t> read_verilog source/ALU.v dc_shell-t> read_verilog source/TOP.v dc_shell-t> link Unable to resolve reference ‘DECODE’ in ‘TOP’
How do we tell DC to find DECODE.db in bob? Setup, Libraries, and Objects Synopsys 31833-000-S16
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Set the search_path Variable
2-10
set target_library my_tech.db set link_library {* my_tech.db} lappend search_path {bob} TOP.v
bob/
my_tech.db source/
DECODE.db
TOP.v ALU.v
module TOP (A,B,OUT1); input A, B; output [1:0] OUT1; ALU U1 (.AIN (A), . . DECODE U2 (.A (BUS0), . .
dc_shell-t> read_verilog source/ALU.v dc_shell-t> read_verilog source/TOP.v dc_shell-t> link Loading db file bob/DECODE.db
dc_shell-t> which DECODE.db /server/my_project/bob/DECODE.db Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Use of analyze / elaborate
2-11
set target_library my_tech.db set link_library {* my_tech.db} lappend search_path {bob} TOP.v
bob/
my_tech.db source/
DECODE.db
TOP.v ALU.v
module TOP (A,B,OUT1); input A, B; output [1:0] OUT1; ALU U1 (.AIN (A), . . DECODE U2 (.A (BUS0), . .
dc_shell-t> analyze -f vhdl source/ALU.vhd dc_shell-t> analyze -f vhdl source/TOP.vhd dc_shell-t> elaborate TOP Loading db file bob/DECODE.db Current design is now ‘TOP’
Where do we specify the directory for the analyzed files? Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Chapter Overview
2-12
Technology Libraries
DC Setup File
Design Objects
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Design Compiler Interfaces
2-13
Four ways to interface to Design Compiler (DC), the Synopsys synthesis engine: design_vision (-tcl)
design_analyzer
Design Vision
Design Analyzer
Tcl mode
dcsh dcsh mode mode Design Compiler (DC)
dc_shell-t
In release 2000.11
dc_shell Setup, Libraries, and Objects
Synopsys 31833-000-S16
Synopsys Workshop
Design Compiler Three Initialization Files 2-14 User’s General Setup
1
~user
2
.synopsys_dc.setup
$SYNOPSYS/admin/setup .synopsys_dc.setup
User’s Specific Project Setup risc_design
Standard Setup
command log
3
.synopsys_dc.setup
./command.log ./view_command.log complete log of DA session Setup, Libraries, and Objects
Synopsys 31833-000-S16
Synopsys Workshop
.synopsys_dc.setup File: Example
2-15
target_library = "tc6a.db" link_library = {"*" tc6a.db opcon.db} symbol_library = "tc6a.sdb" search_path = search_path + "./unmapped” alias h history alias rc report_constraint -all_violators
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
.synopsys_dc.setup: Tcl and dcsh Mode
2-16
# set target_library {tc6a.db} set link_library {* tc6a.db opcon.db} set symbol_library {tc6a.sdb} set search_path “$search_path ./unmapped” alias h history alias rc "report_constraint -all_violators"
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Chapter Overview
2-17
Technology Libraries
DC Setup File
Design Objects
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Design Objects: VHDL Perspective
2-18
Design Clock
entity TOP is
port (A, B, C, D, CLK: in STD_LOGIC; Port OUTI: out STD_LOGIC_VECTOR (1 downto 0)); end TOP; architecture STRUCTURAL of TOP is
... signal INV1, INV0, BUS1, BUS0: STD_LOGIC;
Pin Net
begin U1: ENCODER port map (AIN=>A, . . .
Q1=>BUS1);
Cell U2: INV port map (A => BUS0, Z => INV0); U3: INV port map (A => BUS1, Z=> INV1); U4: REGFILE port map (D0=>INV0, D1=>INV1, . . CLK=>CLK); end STRUCTURAL;
Reference Setup, Libraries, and Objects
Synopsys 31833-000-S16
Synopsys Workshop
Design Objects: Verilog Perspective
2-19
Design module TOP (A,B,C,D,CLK,OUT1); input A, B, C, D, CLK; output [1:0] OUT1; Port
wire INV1,INV0,bus1,bus0;
Clock
Net
ENCODER U1 (.AIN (A), . . . .Q1 (bus1)); Reference INV Cell
U2 (.A (BUS0), .Z( INV0)), U3 (.A( BUS1), .Z( INV1));
Pin
REGFILE U4 (.D0 (INV0), .D1 (INV1), .CLK (CLK) ); endmodule Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Design Objects: Schematic Perspective 2-20 Design
Cell
Net
TOP Port
U4
U1 A B C D
A B C D
AIN
U2 INV
INV0
BUS1
U3 INV
INV1 D1
BIN CIN DIN
Clock
Q0
BUS0
Q1
D0
ENCODER CLK
OUT[1:0]
Q[1:0]
Pin
CLK REGFILE
CLK
Reference and Design
Designs: {TOP, ENCODER, REGFILE} References: {ENCODER, REGFILE , INV} Cells: {U1, U2, U3, U4} Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Multiple Objects with the Same Name
TOP A A B
CLK
U1 AIN ADD S BIN
B
2-21
CLK
U2 SIN D
Q
SUM
DFF
CLK
set_load 5 CLK Does “CLK” refer to a clock, port, net, or pin object? Does it matter onto which object DC places the load?
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
The get Command
2-22
dc_shell-t> set_load 5 [get_nets CLK]
Searches the current_design
Can be used stand-alone or composed with other functions
get commands return a list of object names, if any are found, or an empty list Setup, Libraries, and Objects
Synopsys 31833-000-S16
Synopsys Workshop
What Is a List?
2-23
Lists are a key component of Design Compiler
A list is a special type of character string
A list begins and ends with a “curly brace” {}
Each item is separated by white space
dc_shell-t> set mylist {el1 el2 el3} Information: Defining new variable ‘mylist’ el1 el2 el3
More to lists and objects in Chapter 9 Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
get Command Exercise TOP A
A
B B
2-24
U1 AI ADDS BI
U2 SIN
SOUT D
Q
SUM
DFF
CLK CLK
CLK
Write find commands to do the following: 1. List all of the ports in the design 2. List all of the cells with the letter “U” in their name 3. List all of the nets ending with “CLK” 4. List all of the “Q” pins in the design Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Other Handy List Commands
2-25
List all the input ports of the current design: dc_shell-t> all_inputs
List all the output ports of the current design: dc_shell-t> all_outputs
List all designs in the current design: dc_shell-t> get_designs
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Finding objects with dc_shell-t
2-26
Many of the get commands shown previously have an individual DC-Shell equivalent: Tcl mode
dcsh mode
get_cells *U*
find(cell, *U*)
get_nets *
find(net, “*”)
get_ports CLK
find(port, CLK)
get_clocks CLK
find(clock, CLK)
all_inputs
all_inputs()
all_outputs
all_outputs()
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Lab Details: Directory Structure
2-27
Source code for the CPU has been analyzed, elaborated, and saved (in .db format ) in the unmapped subdirectory
NOTE: Always invoke Design Compiler from the risc_design directory!
risc_design/ source/ vhdl/
unmapped/
scripts/
mapped/ reports/
verilog/
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Lab Details: Hierarchy of RISC_CORE CLK Instrn[31:0]
RISC_CORE
Reset
2-28
EndOfInstrn OUT_VALID PSW[10:0] RESULT_DATA[15:0] Rd_Instr STACK_FULL Xecutng_Instrn[31:0]
RISC_CORE
ALU
PRGRM_CNT_TOP CONTROL
INSTRN_LAT
REG_FILE
DATA_PATH STACK_TOP
PRGRM_CNT
PRGRM_FSM
PRGRM_DECODE Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Lab Details: Design Specifications
Clock Speed
200MHz (5ns)
Clock Skew
300 psec max
Voltage
1.8V ± 0.18V
Operating Temperature
0° ° C to 125° °C
Technology Library
core_slow.db
Symbol Library
core.sdb
2-29
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Lab Details: Exercise
2-30
From the specifications on the previous page, define the library setup variables: set target_library set link_library set symbol_library
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Lab 2: Introduction
2-31 Bring in the design
LAB
60 min
Introduction to Design Analyzer and the Synthesis Flow
Constrain the design
Synthesize the design PRGRM_CNT_TOP PRGRM_CNT
PRGRM_FSM
Inspect the design
PRGRM_DECODE Save the design
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Appendix: Synopsys DesignWare DesignWare®
Star IPs
Complete Source for Commodity IP
2-32
e.g., ARM MIPS IP
Re
ve el i dD s an ool T ing ag DRC ck Pa HDL
Building Blocks Silicon Libraries
MPEG2 USB2.0 PCI-X 8051 PCI 16550...
ls oo ry eT us
Complex IP Cores
>100 Components: memBIST, LFSR, FIFO CTL, etc… + - << >> * Pipeline Mult, Floating Point
Standard Cells
Memories + ProMA™
I/Os
µ 8 µ 1 0. .15 µ 0 .13 0
Memory Generator
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
DesignWare Standard Cells
2-33
0.18µm and 0.15µm Optimized for Design Compiler Optimized for Module Compiler Optimized for Power Compiler Over 600 cells simple and complex gates, buffers, flip flops, latches, complex cells, gated-clock cells
Actual silicon based on DesignWare standard cells
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
DesignWare ProMA Memory Generators
2-34
Single-port synchronous SRAM Dual-port synchronous SRAM Two-port register file ROM
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Synopsys Silicon Libraries Design Creation
High Level
Physical
2-35
Verification & Analysis
Design Compiler Module Compiler Power Compiler Behavioral Compiler
COSSAP VCS, Scirocco Verilog-XL ModelSim VERA, Formality PrimeTime DFT Compiler TetraMAX Synopsys Silicon RailMill Libraries PathMill FlexRoute TimeMill Chip Architect PowerMill Physical Compiler
Apollo Silicon Ensemble
Arcadia Dracula Calibre, Hercules Setup, Libraries, and Objects
Synopsys 31833-000-S16
Synopsys Workshop
Agenda: Day 1 DAY 1
Unit
3-1 Topic
1
Introduction to Synthesis
2
Setup, Libraries, and Objects
3
Partitioning for Synthesis
4
Coding for Synthesis
Lab
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
3-2
After completing this unit you should be able to:
List two effects of partitioning a circuit through combinational logic
State the main guideline for partitioning for synthesis
State how partitions are created in HDL code
List two DC commands for modifying partitions
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
What is Partitioning?
3-3
Partitioning is the process of dividing complex designs into smaller parts
“Divide and conquer!”
Ideally, all partitions would be planned prior to writing any HDL
Initial partitions are defined by the HDL
Initial partitions can be modified using Design Compiler Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Why Partition a Design?
3-4
Partitioning is driven by many (often competing) needs:
Separate distinct functions
Achieve workable size and complexity
Manage project in team environment
Design Reuse
Meet physical constraints
And many, many others ...
Focus will be on partitioning for synthesis Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Partitioning Within the HDL Description entity ADR_BLK is... end; architecture STR of ADR_BLK is U1:DEC port map(ADR, CLK, INST); U2:OK port map(ADR,CLK,AS,OK); end STR; module ADR_BLK (... DEC U1(ADR,CLK,INST); OK U2(ADR,CLK,AS,OK); endmodule
ADR CLK
3-5
ADR_BLK U1 DEC INST U2 OK OK
AS
entity and module statements define hierarchical blocks Instantiation of an entity or module also creates a new level of hierarchy
Inference of Arithmetic Circuits (+, -, *, ..) can create a new level of hierarchy
process and always statements do not create hierarchy Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Eliminate Unnecessary Hierarchy A
C
B REG A
CLK
COMBO LOGIC A
?
3-6
COMBO LOGIC B
?
COMBO REG LOGIC C C CLK
Are these partitions truly needed?
Design Compiler must preserve port definitions
Logic optimization does not cross block boundaries Adjacent blocks of combinational logic cannot be merged
Path from REG A to REG C may be larger and slower than necessary! Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
No Hierarchy in Combinational Paths A
CLK
3-7
C REG A
COMBO LOGIC A & B & C
REG C CLK
Better Partitioning
Related combinational logic is grouped into one block No hierarchy separates combinational functions A, B, and C
Combinational optimization techniques can now be fully exploited Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
No Hierarchy in Combinational Paths (cont) A
3-8
C REG A
COMBO LOGIC A & B & C
CLK
CLK
REG C
Best Partitioning
Related combinational logic is grouped into the same block with the destination register Combinational optimization techniques can still be fully exploited
Sequential optimization may now absorb some of the combinational logic into a more complex Flip-Flop (JK, T, Muxed, Clock-enabled…) Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Partition at Register Boundaries C
B
A
CLK
REG A
3-9
CLK
REG B
CLK
REG C
Good Partitioning Try to design so hierarchy boundaries follow register outputs. Simplifies timing constraints: All inputs to each block arrive with the same relative delay
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Avoid Glue Logic: Example
3-10
TOP C
A COMBO LOGIC A
CLK
REG A
COMBO LOGIC C
REG C CLK
B COMBO LOGIC B
CLK
REG B
Poor Partitioning The NAND gate at the top level serves only to “glue” the instantiated cells: Optimization is limited because the glue logic cannot be “absorbed” Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Remove Glue Logic Between Blocks
3-11
TOP A COMBO LOGIC A
C
CLK
REG A
COMBO REG LOGIC C C CLK + GLUE
B COMBO LOGIC B
CLK
REG B
Nothing but nets at top level
Good Partitioning
The glue logic can now be optimized with other logic
Top-level design is only a structural netlist, doesn’t need to be compiled Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Balance Block Size With Run Times TEENY
3-12
BIG
500 Gates
370,000 Gates
Too Small
100,000 Gates
8,000 Gates
Poor Partitioning
Too Big
If blocks are too small, the designer may be restricting optimization with artificial boundaries
If blocks are too big, compile run times can be very long Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Balance Block Size With Run Times
3-13
BIGGER SMALL 5,000 Gates
BIG 50,000 Gates
150,000 Gates
Good Partitioning
For quick turnaround, partition so that each block has 5,000 - 150,000 gates
Design Compiler has no inherent limit
Match module size to CPU and memory:
Larger modules are fine if sufficient resources are available
Choose smaller sizes when workstation power is limited Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Separate Core Logic, Pads, Clocks, and JTAG 3-14 Partition the Top-Level design into at least three levels of hierarchy: 1. Top-level 2. Mid-level 3. Core
TOP MID
CLOCK GEN JTAG
CORE ASYNCH
This partitioning is recommended due to: • Possible technology-dependent ( “black box”) I/O pad cells • Possible untestable “Divide By” clock generation • Possible technology-dependent JTAG circuitry Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Partitioning within Design Compiler
3-15
The group and ungroup commands modify the partitions in a design
group
ungroup
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
The group Command
3-16
group creates a new hierarchical block U1
U2
U3
group
DES_A
DES_B
DES_C
-design_name NEW_DES -cell_name U23 {U2 U3}
TOP_DESIGN U23 U2
U1
DES_B DES_A
U3
DES_C
NEW_DES
TOP_DESIGN Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
The ungroup Command
3-17
ungroup removes either one or all levels of hierarchy U1
U23 U2
U3
DES_B DES_A
current_design NEW_DES ungroup {U2 U3}
DES_C
NEW_DES TOP_DESIGN U1
DES_A
U23
NEW_DES TOP_DESIGN Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
The ungroup Command: Exercise
U1
U23 U2
U3
DES_Y DES_A
DES_Z
3-18
What happens if you ungroup U23? ungroup {U23}
DES_B TOP_DESIGN
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Partitioning Strategies for Synthesis
Do not separate combinational logic across hierarchical boundaries
Place hierarchy boundaries at register outputs
Size blocks for reasonable runtimes
Separate core logic, pads, clocks, and JTAG
3-19
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Partitioning for Synthesis: Summary
3-20
What do we gain by “partitioning for synthesis”?
Better results -- smaller and faster designs
Easier synthesis process -- simplified constraints and scripts
Faster compiles -- quicker turnaround
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 3: Introduction
LAB
3-21
30 min
group / ungroup
Design Problem: Timing Violation
PRGRM_FSM
PRGRM_ DECODE
PRGRM_CNT
Change Partition for Better Synthesis Results Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 1 DAY 1
Unit
4-1
Topic
1
Introduction to Synthesis
2
Setup, Libraries, and Objects
3
Partitioning for Synthesis
4
Coding for Synthesis
Lab
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Measurable Objectives
4-2
After completing this unit you should be able to:
Describe hardware implications for the following coding constructs:
if-else case loops
Compile HDL code and observe the effects in synthesis
Use DesignWare elements in your RTL source code
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
The Importance of Quality of Source Poor Start Point
4-3
Better Start Point Best Start Point
Goal
Code that is functionally equivalent, but coded differently, will give different synthesis results
You cannot rely solely on Design Compiler to “fix” a poorly coded design!
Try to understand the “hardware” you are describing, to give DC the best possible starting point Coding for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
RTL Coding Guide
4-4 The three big picture guidelines
Coding cookbook
L D H
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
The Big Picture, Think Hardware!
Write HDL hardware descriptions
4-5
Think of the topology implied by the code
Do not write HDL simulation models
Yes!
No explicit delays No file I/O
No!
after 20 ns and 2 clock cycles OUTPUT <= IN1 + RAM1; wait 20 ns; ...
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
The Big Picture, Think Synchronous!
4-6
Synchronous designs run smoothly through synthesis, test, simulation, and layout
Asynchronous designs may require hand instantiation and extensive simulation to verify
Isolate asynchronous logic into separately compiled blocks ACK_SET ADDR_IN
ADDR DECODE +5
ACK
AS ACK_CLR
How am I going to synthesize this? Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
The Big Picture, Think RTL!
4-7
RTL = Register Transfer Level
Writing in an RTL coding style means describing
the register architecture, the circuit topology, and the functionality between registers
Design Compiler optimizes logic between registers
It does not optimize the register placement
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
RTL Synthesis Cookbook
4-8
The three big picture guidelines
Coding cookbook
L D H
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis of if Statements
4-9
Synthesis of if statements
Synthesis of case statements
Synthesis of loop statements
Synthesis of Flip-Flops
Synthesis of arithmetic circuits
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
if-else Statements
4-10
The if-else construct implies multiplexing hardware
One output value is selected based on a certain condition
Actual circuit implementation depends on target library and constraints
if (Aflag = '1') then OutData <= A + B; else OutData <= C + D; end if;
A B C D
+
D1 OutData
+
D0 S
Aflag
How could we recode this example so that the multiplexing hardware was before the adder? Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
if-else Statements (cont)
4-11
Location of multiplexing hardware depends on location of if-else construct if (Aflag == 1’b1) begin Op1 <= A; Op2 <= B; end else begin Op1 <= C; Op2 <= D; end
A
D1 Op1
C
D0
S
Aflag B
+
OutData
D1 Op2
D
D0
S
OutData <= Op1 + Op2;
Aflag
What if Aflag was late-arriving? Which circuit is better? What if the else was missing? Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
if Statements and Latches
4-12
To infer latches, use an if statement without an else clause
VHDL/Verilog language definitions require signals to maintain their old value unless a new value is assigned Latches implement this requirement in hardware
LS373: process (ALE, ADBUS)
always @ (ALE or ADBUS)
begin
begin
if (ALE = ‘1’) then
if (ALE)
ABUS <= ADBUS;
ABUS <= ADBUS; end
end if; end process LS373; 8
ADBUS ALE
/
8
D
Q
/
ABUS
G Coding for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
if-then-elseif Statements
4-13
Since VHDL and Verilog if-elseif statements imply priority, they should only be used if priority checking is a circuit requirement
Otherwise, priority control logic will be synthesized Result will be more, and possibly slower logic
Example: Priority Interrupt Controller
One or more of four (input) interrupt lines (int0..int3) may be asserted Only one output should be asserted int0 has the highest priority int0 int1 int2 int3
active[0] active[1] active[2] active[3] Coding for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
if-then-elseif Statements (cont)
4-14
module test(active,int0,int1,int2,int3); input int0,int1,int2,int3; output [3:0] active; Why are the reg int0,int1,int2,int3; outputs active[3:0] reg [3:0] active; initialized to 0? always@(int0 or int1 or int2 or int3) begin active[3:0] <= 4’b0; if (int0) active[0] <= 1’b1; Which flag has the else if (int1) active[1] <= 1’b1; highest priority? else if (int2) active[2] <= 1’b1; else if (int3) active[3] <= 1’b1; end; endmodule
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Priority Interrupt Circuit: Synthesis Results
int0
active[0]
int1
active[1]
4-15
active[2] int2 active[3] int3
Priority Logic
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
When NOT to Use if-then-elseif
When signals have equal priority
When signals are mutually exclusive
4-16
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis of case Statements
4-17
Synthesis of if Statements
Synthesis of case Statements
Synthesis of loop Statements
Synthesis of Flip-Flops
Synthesis of Arithmetic Circuits Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
case Statements
case statements in Verilog
case statements in VHDL
4-18
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
case Statements
4-19
Case statements imply parallel mux function. process (SEL,A,B,C,D) begin case SEL is when “00” => OUTC <= A; when “01” => OUTC <= B; when “10” => OUTC <= C; when others => OUTC <= D; end case; end process;
VHDL Code always@(SEL or A or begin case (SEL) 2’b00 : OUTC = 2’b01 : OUTC = 2’b10 : OUTC = default : OUTC endcase end
00 01 10 11
A B C D
OUTC
B or C or D)
SEL
2
A; B; C; = D;
Note: Actual gates synthesized might not be a 4:1 MUX.
Verilog Code Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Interrupt Vector Address Generator
4-20
Build a logic that takes the signals of the priority interrupt circuit and generates a 16-bit memory address that is unique for each interrupt. interrupt
address to be generated
active[0] active[1] active[2] active[3]
0000000000 00000100b 0000000000 00000110b 0000000000 00001000b 0000000000 00001010b
(0004h) (0006h) (0008h) (000Ah)
Each of the above memory locations contain the starting address of an interrupt handling routine, which is read by the processor at an appropriate time after a valid interrupt is recognized. active[0] active[1] active[2] active[3]
vec[15:0]
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Address Generator: Verilog
4-21
always @(active[3] or active[2] or active[1] or active[0]) begin case ({active[3], active[2], active[1], active[0]}) 4’b1000 : temp = 3’b010; 4’b0100 : temp = 3’b011; 4’b0010 : temp = 3’b100; 4’b0001 : temp = 3’b101; 4’b0000 : temp = 3’b000; default : temp = 3’bxxx; endcase end always vec[15:4] = 12’h000; always vec[0] = 0; always @(posedge clk) vec[3:1] = temp;
What happens if you do not include the default clause? Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Schematic of Address Generator
4-22
A schematic after compiling the source code of the Interrupt Vector Address Generator. active[2] D
Q
vec[3]
active[3] CLK
active[0] D
Q
vec[2]
active[1] CLK
D
clk
Q
vec[1]
CLK
vec[0] vec[15:4]
vec[15:0]
gnd
Without the default clause, the case statement would not be fully specified and infer latches. Can be controlled by compiler directives. Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Compiler Directive full_case
4-23
always @(active[3] or active[2] or active[1] or active[0]) begin case ({active[3], active[2], active[1], active[0]}) //synopsys full_case 4’b1000 : temp = 3’b010; 4’b0100 : temp = 3’b011; 4’b0010 : temp = 3’b100; 4’b0001 : temp = 3’b101; 4’b0000 : temp = 3’b000; endcase end always vec[15:4] = 12’h000; always vec[0] = 0; always @(posedge clk)
vec[3:1] = temp;
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Compiler Directive parallel_case
4-24
always @(active[3] or active[2] or active[1] or active[0]) begin temp = 3’b000; case (1’b1)
//synopsys parallel_case
active[3] : temp = 3’b010; active[2] : temp = 3’b011; active[1] : temp = 3’b100; active[0] : temp = 3’b101; endcase end always vec[15:4] = 12’h000; always vec[0] = 0; always @(posedge clk)
vec[3:1] = temp;
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis of loop Statements
4-25
Synthesis of if Statements
Synthesis of case Statements
Synthesis of loop Statements
Synthesis of Flip-Flops
Synthesis of Arithmetic Circuits Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Unrolling Loops
4-26
In synthesis, for loops are “unrolled” during translation, and then synthesized process process (( a, a, bb )) begin begin for for ii in in 00 to to 33 loop loop out(i) out(i) <= <= a(i) a(i) and and b(3 b(3 -- i); i); end end loop; loop; end process; end process; out(0) out(1) out(2) out(3)
<= <= <= <=
a(0) a(1) a(2) a(3)
and and and and
b(3); b(2); b(1); b(0);
integer integer i; i; always@( always@( aa or or b) b) begin begin for ( i = 0; i for ( i = 0; i <= <= 33 ;; ii == ii ++ 11 )) out[i] out[i] <= <= a[i] a[i] && b[3 b[3 -- i]; i]; end end
a(0) b(3)
out(0)
a(1) b(2)
out(1)
a(2) b(1) a(3) b(0)
out(2) out(3)
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Tradeoffs with Loops process (data) variable sum : integer; begin sum := 0; -- Count the 1’s for i in 0 to 7 loop sum := data(i) + sum; end loop; --check parity odd_parity <= sum mod 2; end process;
4-27
always@(data) begin sum = 0; /* Count the number of ‘1’s */ for (i = 0; i < 8; i = i + 1) sum = sum + data[i]; /* Check if even or odd number */ odd_parity = sum[0]; end;
What does the hardware look like for this example?
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Hardware Result
4-28
Data(2)
+
Data(0)
+ Data(1)
/ 2
...
Data(6) / 2
+
/ 3
+
Data(7)
How could this be recoded?
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Recoded Loop
4-29
VHDL
unrolled
process (data) variable odd_parity : bit; begin odd_parity <= ‘0’; for i in 0 to 7 loop odd_parity <= data(i) xor odd_parity; end loop; end process;
Verilog always@ (data) begin odd_parity = ^data; end optimized design
binary XOR Coding for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis of Flip-Flops
4-30
Synthesis of if Statements
Synthesis of case Statements
Synthesis of loop Statements
Synthesis of Flip-Flops
Synthesis of Arithmetic Circuits Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Inferring Sequential Devices
4-31
“Registering” a signal means clocking it into a Flip-Flop
For DC to infer Flip-Flops, your code must imply signal assignments that take place in response to the edge of another signal
DC requires specific coding templates to infer registers
A B CLK RSTn
How do you: +
D
Q
S1 assign A+B to S1 in response to a rising edge on CLK ? With an asynchronous reset? Coding for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Flip-Flop: Example
4-32
process (CLK, RSTn) begin if (RSTn =‘0’) then -- async reset S1 <= ‘0’; elsif (CLK’event and CLK = ‘1’) then S1 <= A + B; end if; end process;
A B CLK RSTn
+
D
Q
always@(posedge CLK or negedge RSTn) begin if (! RSTn) S1 S1 <= 1’b0; else S1 <= A + B; end
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Inferring Sequential Devices
Design Compiler can synthesize hardware using a wide variety of flip-flops and latches Latch
Latch Latch Latch w/ w/Dual w/Sync Async Async Clr
DFF
DFF DFF DFF w/ w/Dual w/Sync Muxed DFF Async Async Cntl.
MS Latch
JKFF
The registers in your final circuit depend on:
4-33
Coding style (including attributes and directives) Types of registers available in the target_library
(V)HDL Compiler generates an inference report Example: Inference Report for an AR Flip-Flop Register Name Q_reg
Type
Width
Bus
MB
Flip-Flop
1
-
-
AR
AS
SR
SS
ST
Y
N
N
N
N
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis of Arithmetic Circuits
4-34
Synthesis of if Statements
Synthesis of case Statements
Synthesis of loop Statements
Synthesis of Flip-Flops
Synthesis of Arithmetic Circuits Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Inferring Arithmetic Parts
4-35
process (A, B, C, D, addr) begin if (addr = 12) then Result <= A + B; else Result <= C + D; always@ (A or B or C or D or addr) end if; begin end process;
if (addr == 4’d12) Result <= A + B; else Result <= C + D; end
What does the hardware look like in this example? Where do the mathematical circuits come from? Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
DesignWare Arithmetic Resources AND Gates, OR Gates, Flip-Flops...
link_library, target_library
Adders, Multipliers, Comparators...
Technology Library
4-36
synthetic_library
DesignWare Library
What is DesignWare?
Technology-independent “soft macros” such as adders,comparators, etc., which are synthesized into gates from your target library Enables the user to imply large and complex arithmetic operations to be synthesized: if (A1 >= A2) Y <= M * X + B; else Y <= M * X + C; Coding for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
DesignWare Implementation Selection
4-37
Multiple architectures for each macro allow DC to evaluate speed/area tradeoffs and choose the best implementation fastest
Ripple Carry Select
Z <= A + B; Conditional Sum Synthesis
DW Foundation
Brent-Kung
+
Carry Look-Forward HDL Operator
Carry Look-Ahead smallest
Ripple Carry
DW Basics
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Enabling Faster DW Implementations
4-38
DesignWare components come from synthetic libraries
Synopsys-provided synthetic library files reside in directory $SYNOPSYS/libraries/syn
The synthetic_library variable points to a list of synthetic library database (.sldb) files:
synthetic_library = {dw_foundation.sldb} link_library = link_library + synthetic_library
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Implying a Structure by Operand Placement 4-39
As with if-else blocks, coding style implies a circuit topology
V/HDL Compiler parses expressions from left to right Parentheses will override this default order DesignWare built in this order is the starting point for DC SUM <= A*B + C*D + E + F + G
A B C D
* *
+ E
+ F
+
G
+
SUM
Total Delay = Multiplier + 4 adders
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Implying a Structure by Operand Placement (cont)
4-40
Change the order, or use parentheses to force a different topology: SUM <= E + F + G + C*D + A*B SUM <= (A*B) + E F
+ G C D
(
(C*D) + ((E+F) + G)
+ *
+ A B
+
)
SUM
*
Max Delay = Multiplier + 2 adders
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Verilog Preprocessor Directive
4-41
module IFDEF(out,a,b,clk); output out; input clk,a,b; reg out; always@(posedge clk) begin ‘ifdef SYN out=b && a; ‘else SYN $display (“The output is: “); out=b && a; ‘endif set hdlin_enable_vpp true end analyze -f verilog -d SYN IFDEF.v endmodule elaborate IFDEF -lib WORK Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Documentation
4-42
Synopsys On-Line Documentation
HDL Compiler for Verilog Reference Manual
VHDL Compiler Reference Manual
Guide to HDL Coding Styles for Synthesis
Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! www.synopsys.com -> SNUG -> SNUG Papers -> 2000 San Jose
“full_case parallel_case”, the Evil Twins of Verilog Synthesis www.synopsys.com -> SNUG -> SNUG Papers -> 1999 Boston
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 4: Introduction LAB
4-43
60 min
Examine Coding Style Issues LOOP_BAD IF_BAD
LOOP_GOOD IF_GOOD
LOOP_BEST IF_BEST
Area Path Value
compare_design IF_BAD IF_GOOD Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Appendix
4-44
Inference and Instantiation
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Verilog Inference and Instantiation Inference
4-45
identifier for the resource
always @(A or B) begin :b1 /* synopsys resource r0: map_to_module = "DW02_mult", implementation = "wall", ops = "a1"; */ PROD <= A * B; //synopsys label a1 end;
synthetic module Wallace tree synthesis model
Instantiation // synopsys dc_script_begin // set_implementation wall U1 // synopsys dc_script_end DW02_mult #(Awidth, Bwidth) U1(A, B, TC, PROD); report_resources Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
VHDL Inference and Instantiation
4-46
Inference library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; inside the architecture block: PROD <= A * B; Instantiation library IEEE, DWARE; use IEEE.std_logic_1164.all; use DWARE.DW_Foundation_comp; inside the architecture block: U1: DW01_add
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 2 DAY 2
Unit
5-1 Topic
5
Timing and Area
6
Environmental Attributes
7
Time and Load Budgeting
8
Timing Analysis
9
DC Tcl - Introduction
Lab
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
5-2
After completing this unit, you should be able to:
Constrain a design for area
Constrain a design for timing
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
RTL Block Synthesis Write RTL HDL Code
Rewrite
No
Analysis
Simulate OK? Yes
Yes Major Violations?
5-3
No
No
Synthesize HDL Code To Gates
Constraints & Attributes Area & Timing Goals
Met Constraints? Yes Timing and Area
Synopsys 31833-000-S16
Chip Synthesis Workshop
Specifying an Area Goal dc_shell-t> dc_shell-t> dc_shell-t> dc_shell-t>
5-4
current_design current_design PRGRM_CNT_TOP PRGRM_CNT_TOP set_max_area set_max_area 100 100
Units are those of target library, defined by the vendor 2-input-NAND-gate transistors square mils
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Goals: Synchronous Designs
5-5
Synchronous Designs:
Data arrives from a clocked device
Data goes to a clocked device
Objective:
Define the timing constraints for all paths within a design:
all input logic paths
the internal (register to register) paths, and
all output paths
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Goals: Synchronous Designs (cont)
5-6
TO_BE_SYNTHESIZED D Q FF1 QB
M
N
D Q FF2 QB
X
D Q FF3 QB
S
T
D Q FF4 QB
Clk
What information must you provide to constrain all the register-to-register paths in your design? Does the duty cycle of your clock matter? Example: Clock Period = 10ns
Setup = 1ns
What is the max delay requirements for the register-to-register paths in the block TO_BE_SYNTHESIZED? Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Defining a Clock
5-7
User MUST Define: Clock Source (port or pin) Clock Period
User may also define: Duty Cycle Offset/Skew Clock Name TO_BE_SYNTHESIZED
Clk N
Period
D Q FF2
X
D Q FF3
S
Clk
1 Clock Cycle Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Defining a Clock in Design Compiler
5-8
dc_shell-t> create_clock -period 10 [get_ports Clk] dc_shell-t> set_dont_touch_network
[get_clocks Clk]
TO_BE_SYNTHESIZED
Clk
Creating a clock constrains timing paths between registers
Use report_clock to see defined clocks and their attributes
set_dont_touch_network tells DC not to “buffer up” the clock net, even if there are too many flip-flops loading it
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Goals: Synchronous Designs, I/O
5-9
Path X constrained by create_clock TO_BE_SYNTHESIZED D Q FF1 QB
M
N
D Q FF2
X
D Q FF3
S
T
D Q FF4 QB
Clk
Paths N & S are still unconstrained!
Method: 1. Define the clocks 2. Define the I/O timing relative to the clocks
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Constraining the Input Paths TO_BE_SYNTHESIZED
External Logic
Launch edge triggers data
M D
5-10
N
A
Q
D
Q
Clk
Next edge captures data
Clk
TClk-q
TM
TN
TSETUP
What information must you provide to constrain the input paths?
Clk Valid new data
A (TClk-q + TM)
(TN + TSETUP)
(Input Delay) Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Constraining Input Paths in DC
5-11
dc_shell-t> set_input_delay -max 4 -clock Clk [get_ports A]
The set_input_delay command constrains input paths Launch Edge
You specify how much time is used by external logic... DC calculates how much time is left for the internal logic
Capture Edge
4
delay of time left for external internal logic logic
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
set_input_delay: Exercise EXTERNAL CIRCUIT
TO_BE_SYNTHESIZED
CLK-OUTPUT 7.4 ns (worst)
Clock (50 MHz)
5-12
A
N Clk
create_clock
U1
_______________________________________
set_dont_touch_network set_input_delay
____________________________
____________________________________ 0.0
Clk
D Q
10.0
20.0
7.4
A Constraint of YOUR input path Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
set_input_delay: Effect on Input Paths EXTERNAL CIRCUIT
Clk (50 MHz)
CLK-OUTPUT 7.4 ns (worst)
5-13
TO_BE_SYNTHESIZED
A N
Clk
D Q
U1
create_clock -period 20 [get_ports Clk] set_dont_touch_network [get_clocks Clk] set_input_delay -max 7.4 -clock Clk [get_ports A]
If U1 has a 1 ns setup requirement: What is the maximum delay for TN? Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Constraining Output Paths of a Design U3 Launches Data
External Logic
TO_BE_SYNTHESIZED U3 D
S
B
T
Q
D
Q
5-14 External Flip-Flop captures data
Clk
TClk-q
Ts
TT
TSETUP
What information must you provide to constrain the output paths? Launch Edge
Capture Edge
Clk B
Valid new data
TClk-q + TS TT + TSETUP (Output Delay) Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Constraining Output Paths in DC
5-15
dc_shell-t> set_output_delay -max 5.4 -clock Clk
[get_port B]
The set_output_delay command constrains output paths You specify how much time is needed by external logic... DC calculates how much time is left for internal logic
Capture Edge
Launch Edge
5.4 Constraint of YOUR output path
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
set_output_delay Exercise
5-16
TO_BE_SYNTHESIZED U3 D
Clk (50 MHz)
EXTERNAL CIRCUIT B
S Q
Setup Requirement: 7.0 ns
Clk
create_clock
_______________________________________
set_dont_touch_network set_output_delay 0.0
_____________________________
___________________________________ 10.0
20.0
Clk 7.0
Gets clocked here
B Data launched here
Must be valid here Timing and Area
Synopsys 31833-000-S16
Chip Synthesis Workshop
set_output_delay: Effect on Output Paths 5-17 TO_BE_SYNTHESIZED U3
D
Q
S
EXTERNAL CIRCUIT
B
Clk
Setup Requirement: 7.0 ns
Clock (50 MHz)
create_clock -period 20 [get_ports Clk] set_dont_touch_network [get_clocks Clk] set_output_delay -max 7.0 -clock Clk [get_ports B]
If U3 has TCLK-Q = 1.0ns: What is the maximum delay for TS? Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Area & Timing Goals Summary: Exercise 5-18 How do you constrain for area?
TO_BE_SYNTHESIZED
Clk
D Q FF1 QB
M
N
D Q FF2 QB
X
D Q FF3 QB
S
T
D Q FF4 QB
How do you constrain the register to register paths? How do you constrain the the I/O paths? Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Useful Commands
5-19
report_port -verbose
Returns all attributes and constraints placed on all input and output ports
report_clock
Returns the source, waveform and period of all clock objects in current_design
reset_design
Removes attributes and constraints from current_design
list_libs
Returns the available libraries in memory
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 5: Introduction
LAB
5-20
30 min unmapped PRGRM_CNT_TOP.db
Apply Timing Constraints
Bring in the design
Constrain the design
unmapped
prgrm_attr.db
Save the design
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 2 DAY 2
Unit
6-1 Topic
5
Timing and Area
6
Environmental Attributes
7
Time and Load Budgeting
8
Timing Analysis
9
DC Tcl - Introduction
Lab
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
6-2
After completing this unit, you should be able to:
Scale cell delays for Temperature and Voltage extremes
Use Wire Load Models within DC
Use constraints for DC to account for external circuitry
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
RTL Block Synthesis Write RTL HDL Code
Rewrite
No Yes Major Violations?
6-3
Simulate OK?
Yes No
Synthesize HDL Code To Gates
Constraints & Attributes Area & Timing Goals
Netlist Analysis
No
Met Constraints?
Yes Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Constraining for Timing: What’s Missing? TO_BE_SYNTHESIZED
6-4
set_output_delay
set_input_delay N
D Q FF2 QB
X
D Q FF3 QB
S
CLK
create_clock
What physical information about the chip is required in order to accurately calculate the speed of each path?
What information (besides external setup) does DC require in order to ensure logic S meets timing?
What information (besides input delay) does DC require in order to ensure logic N meets timing? Environmental Attributes
Synopsys 31833-000-S16
Chip Synthesis Workshop
Describing Environmental Attributes
6-5
set_operating_conditions set_load
set_driving_cell set_wire_load_model
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Modeling Capacitive Load
6-6
TO_BE_SYNTHESIZED
In order to accurately calculate the timing of an output circuit, DC needs to know the total capacitance driven by the output cells
set_load allows the user to specify the external capacitive load on ports
By default, DC assumes that the external load on ports is 0
You can specify some other constant value, or... The load_of command can be used to specify the external load as the pin load of a cell in your technology library
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
set_load Examples
6-7
Use set_load to specify a load value on an output port: OUT1
set_load 5 [get_ports OUT1]
5
Use set_load load_of(lib/cell/pin) to place the load of a gate from the technology library on the port: A
OUT1
OUT1
A AN2 B
A A
set_load [load_of(my_lib/and2a0/A)] [get_ports OUT1] set_load [expr [load_of(my_lib/inv1a0/A) * 3]] OUT1
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Modeling Input Drive Strength
6-8
In order to accurately calculate the timing of an input circuit, DC needs to know the transition time of the signal arriving at the input port
set_driving_cell allows the user to specify a realistic external cell driving the input ports
By default, DC assumes that the external signal has a transition time of 0
Placing a driving cell on the input ports causes DC to calculate the actual (non-zero) transition time on the input signal as though the specified library cell was driving it TO_BE_SYNTHESIZED
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
set_driving_cell Examples
6-9
TO_BE_SYNTHESIZED ND2 IN1
dc_shell-t> set_driving_cell -lib_cell and2a0 \ [get_ports IN1]
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Variations in Cell Delays
6-10
Library cells are usually characterized using “nominal” voltage and temperature: nom_process : nom_temperature : nom_voltage :
1.0; 25.0; 1.8;
What if the circuit is to operate at a voltage and/or temperature OTHER than nominal?
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Operating Conditions
6-11
Vendors allow for synthesis of circuits which will not operate under “nominal” conditions by embedding operating condition models in the technology libraries
Operating conditions can be placed on your design by using the set_operating_conditions command
During synthesis, “nominal” cell and wire delays will be scaled based on the operating conditions
worst Delay
nominal best Temperature
Delay
worst nominal best
Voltage
Delay
worst nominal best Process Environmental Attributes
Synopsys 31833-000-S16
Chip Synthesis Workshop
Default Operating Conditions
6-12
By default, NO operating conditions are specified for a design
Use report_lib libname to list the vendor-supplied operating conditions
Operating Conditions: Name Library Process Temp Volt ---------------------------------------------------typ_25_1.80 my_lib 1.00 25.00 1.80 slow_125_1.62 my_lib 1.00 125.00 1.62 fast_0_1.98 my_lib 1.00 0.00 1.98
To set operating conditions, enter
dc_shell-t> set_operating_conditions -max “slow_125_1.62” quotes are optional Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Technology Libraries
6-13
ASIC vendors might deliver multiple technology libraries, defining:
best-case and worst-case operating conditions
optimistic and pessimistic WLM
minimum and maximum timing delay
Syntax: set_min_library max_library -min_version min_library Example: dc_shell-t> set_min_library ssc_core_slow -min_version ssc_core_fast dc_shell-t> set_operating_conditions -max slow_125_1.62 \ -min fast_0_1.98 Cannot use -min without -max Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Net delays
6-14 I/O Pad Driver
RAM
Prior to layout, how can the RC delay of nets be estimated?
Receiving Gates
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
What Is a Wire Load Model?
6-15
A wire load model is an estimate of a net’s RC parasitics based on the net’s fanout:
Model is created by your vendor
Estimates are based on statistics from other designs the vendor has fabricated using this process
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Wire Load Model: Standard Format
6-16
Example: Standard Format Name : 160KGATES Location : ssc_core_slow Resistance : 0.000271 Capacitance : 0.00017 Area : 0 Slope : 50.3104 Fanout Length --------------------------------1 31.44 2 81.75 3 132.07 4 182.38 5 232.68 Time Unit
R per unit length C per unit length Extrapolation slope
: 1ns Capacitive Load Unit : 1.000000pf Pulling Resistance Unit : 1kilo-ohm Environmental Attributes
Synopsys 31833-000-S16
Chip Synthesis Workshop
Specifying Wire Loads in Design Compiler 6-17
Manual model selection dc_shell-t> set current_design addtwo dc_shell-t> set_wire_load_model -name 160KGATES
Automatic model selection dc_shell-t> set auto_wire_load_selection true Definition from report_lib: Selection Wire load name min area max area ------------------------------------------0.00 43478.00 5KGATES 43478.00 86956.00 10KGATES 86956.00 173913.00 20KGATES 173913.00 347826.00 40KGATES 347826.00 695652.00 80KGATES Environmental Attributes
Synopsys 31833-000-S16
Chip Synthesis Workshop
Wireload Model Mode
6-18
Specifies wire load model to use for nets that cross hierarchical boundaries. mode = enclosed TOP
mode = top TOP
SUB B1
SUB B2
WLM_SUB
B2
B1
WLM_TOP
less pessimistic mode Example: dc_shell-t> set_wire_load_mode enclosed
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Check Your Constraints
6-19
report_port -v a
check_design
report_design check_timing
write_script
report_clock
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Commands for Data Removal
6-20
You have several useful commands for libraries and designs: reset_design
Erases all attributes and constraints from design
remove_design -design
Removes designs from Design Compiler memory
remove_design -all
Removes designs and libraries from DC memory
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
List Commands
6-21
list_files
Lists all files in DC memory
list_designs
Lists all design names in DC memory
list_lib
Lists all libraries in DC memory
list_license
Lists all licenses uses by this shell
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Exercise: Describe the Environment
6-22
Create a “default” script file which can be applied to each subblock of a large ASIC, using the following specifications: Clock Speed
125 MHz
Input logic use 40% of clock period
3.2 ns
Output logic use 40% of clock period
3.2 ns
Operating at 85° °C and 1.6 volts
oc_85_16
Wireload Model
40KGATES
Cell driving inputs
inv1a0
Output have to drive 5 pF
5 pF Environmental Attributes
Synopsys 31833-000-S16
Chip Synthesis Workshop
Script File: Describe the Environment
6-23
reset_design # Timing
# Environment
Environmental Attributes Synopsys 31833-000-S16
.
Chip Synthesis Workshop
Lab 6: Introduction
6-24 Bring in the design
LAB
30 min unmapped
prgrm_attr.db
Apply Environmental Constraints
Constrain the design
Synthesize the design
mapped PC.db
Inspect the design
Save the design Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Appendix
6-25
Create an Operating Condition
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Create Your Own Operating Conditions
6-26
You can create your own operating conditions — without a Library Compiler license — if there are none that satisfy your design requirements extra.lib: library (“extra”) { operating_conditions("SLOW") { process : 1.75 ; temperature : 100; voltage : 1.60 ; tree_type : “worst_case_tree”;} }
After you create your own operating conditions, you must compile them to make them available for use by the Design Compiler
dc_shell-t> dc_shell-t> dc_shell-t> dc_shell-t>
read_lib extra.lib write_lib extra -output extra.db set link_library “* tech_library extra.db” set_operating_conditions SLOW -library extra Environmental Attributes
Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 2 DAY 2
Unit
7-1 Topic
5
Timing and Area
6
Environmental Attributes
7
Time and Load Budgeting
8
Timing Analysis
9
DC Tcl - Introduction
Lab
Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
7-2
After completing this unit, you should be able to:
Create a timing budget for a design block
Use the set_max_capacitance command to limit the input capacitance of a block
Budget the load on the output ports using the set_load command
Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
RTL Block Synthesis Write RTL HDL Code
Rewrite
No Yes Major Violations?
7-3
Simulate OK?
Yes No
Synthesize HDL Code To Gates
Constraints & Attributes Area & Timing Goals
Netlist Analysis
No
Met Constraints?
Yes Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Time Budgeting
7-4
What if you don’t know the delays on your inputs or the setup requirements of your outputs?
D Q FF1
CLK (100 MHz)
ckt Y
MY circuit
ckt X ?
?
N
D Q FF2
X
D Q FF3
S
?
?
D Q FF4
A: Create a Time Budget !
Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Time Budgeting (cont) circuit X D Q
?
7-5
MY circuit N
FF1
CLK (100 MHz)
D Q
X
FF2
40% of clock period
Better to budget conservatively than to compile with paths unconstrained! Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Time Budgeting Example
7-6
# A generic Time Budgeting script file # for MY_BLOCK create_clock -period 10 [get_ports CLK] set_dont_touch_network [get_clocks CLK] set_input_delay -max 6 -clock CLK [all_inputs] remove_input_delay [get_ports CLK] set_output_delay -max 6 -clock CLK [all_outputs] X_BLOCK X
10
D Q FF1
MY_BLOCK S
N
4
D Q FF2
Y_BLOCK X
10
D Q FF3
S
4
N
X
D Q FF4
10
DC still needs to consider delay of FF1 and setup of FF2 Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Time Budgeting Example (cont)
7-7
# Time Budgeting script file # for X_BLOCK and Y_BLOCK create_clock -period 10 [get_ports CLK] set_dont_touch_network [get_clocks CLK] set_input_delay -max 6 -clock CLK [all_inputs] remove_input_delay [get_ports CLK] set_output_delay -max 6 -clock CLK [all_outputs] X_BLOCK X
10
D Q FF1
MY_BLOCK S
4
N
D Q FF2
Y_BLOCK X
10
D Q FF3
S
N
4
X
D Q FF4
10
Would it be easier to specify a time budget if all outputs were registered? Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Load Budgeting
7-8
What if, prior to compiling, the cells driving your inputs, and the loads on your outputs are not known?
D Q FF1
Y_BLOCK
MY_BLOCK
X_BLOCK ?
N
D Q FF2
X
?
D Q FF3
S
?
?
D Q FF4
Z_BLOCK
A: Create a Load Budget! Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Load Budgeting (cont)
7-9
Whatif, if, prior prior to loads on on your outputs, Q: What to compiling, compiling,the the loads your outputs, andthe the cells cells driving areare notnot known? and drivingyour yourinputs inputs known?
A: Create a load budget
Assume a weak cell driving the inputs, to be conservative
Limit the input capacitance of each input port
Estimate the number of other major blocks your outputs may have to drive
How do we limit the input capacitance of an input port?
A: Place restrictive design rules on our input ports
Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Load Budget Example
7-10
Example Specification: Inputs
of any block shall present no more than the load of 10 “AND2” gates to their driving block
Outputs
of any blocks will only be allowed to connect to a maximum of 3 other blocks
Otherwise, output port will need to be replicated in code
1
10x
2 Assume a weak cell driving the inputs
Cinternal
3 10
Limit the load imposed 10x on driving block Cexternal
10x 10x
Keep track of how many other designers are using each output Timing and Load Budgeting
Synopsys 31833-000-S16
Chip Synthesis Workshop
Load Budget Example (cont)
7-11
current_design myblock link source timing_budget.tcl # Assume a weak driving buffer on the inputs set_driving_cell -lib_cell inv1a0 [all_inputs] remove_driving_cell [get_ports Clk] # Limit the input load set MAX_INPUT_LOAD [expr [load_of(tech_lib/and2a0/A) * 10]] set_max_capacitance $MAX_INPUT_LOAD [all_inputs] remove_attribute max_capacitance [get_ports Clk] # Model the max possible load on the outputs, assuming # outputs will only be tied to 3 subsequent blocks set_load [expr [$MAX_INPUT_LOAD * 3]] [all_outputs] Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Exercise: Describe the Environment
7-12
Create a “default” script file which can be applied to each subblock of a large ASIC, using the following specifications: Clock Speed
125 MHz
input / output ports use 40% of clock
3.2 ns
Operating at 85°°C and 1.6V
oc_85_45
Wireload Model
40KGATES
Cell driving inputs
inv1a0
max input capacitance at input ports
10x pin “A” of buf1a0
Output drive no more than 4 blocks
4 blocks
Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Script File: Describe the Environment
7-13
reset_design # Timing
# Environment
Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary of Describing Constraints
7-14
Timing and Area Goals: set_max_area create_clock
set_input_delay set_output_delay set_dont_touch_network
Environmental Attributes: set_driving_cell set_operating_conditions
set_load set_wire_load_model
Design Rules: set_max_capacitance
Reports: report_clock report_port -verbose report_design
write_script
Problems? reset_design
remove_design Timing and Load Budgeting
Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 7: Introduction
7-15 Bring in the design
LAB
45 min unmapped
PRGRM_CNT_TOP.db
Apply Timing and Load Budget
Constrain the design
Synthesize the design
unmapped
prgrm_attr.db
Inspect the design
Save the design Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 2 DAY 2
Unit
8-1 Topic
5
Timing and Area
6
Environmental Attributes
7
Time and Load Budgeting
8
Timing Analysis
9
DC Tcl - Introduction
Lab
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
8-2
After completing this unit, you should be able to:
Generate a worst-case (maximum) timing report
Interpret a timing report to determine if you have met timing constraints
Use a timing report to diagnose timing constraint violations
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Does Your Design Meet Its Goals? Write RTL HDL Code
Rewrite
No Yes Major Violations?
8-3
Simulate OK?
Yes No
Synthesize HDL Code To Gates
Constraints & Attributes Area & Timing Goals
Netlist Analysis
No
Met Constraints?
Yes
Use Timing Analysis! Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Analysis: What Tool Do I Use?
8-4
Design Compiler has a built-in static timing analyzer called DesignTime Verilog
VHDL
Design Analyzer HDL Compiler
VHDL Compiler
Design Compiler DesignTime
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Static Timing Analysis Path 1 A
8-5
Path 2 D
Q
Z
CLK
Path 3
Static Timing Analysis can determine if a circuit meets timing constraints without dynamic simulation
This involves three main steps:
Design is broken down into sets of timing paths
The delay of each path is calculated
All path delays are checked to see if timing constraints have been met Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Paths in Design Compiler
8-6
MY_DESIGN A
D Q FF1 QB
D Q FF2 QB
Z
CLK
DesignTime breaks designs into sets of signal paths
Each path has a startpoint and an endpoint
Startpoints: Input ports Clock pins of Flip-Flops or registers
Endpoints: Output ports Data input pins of sequential devices
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Organizing Timing Paths into Groups
8-7
MY_DESIGN
CLK1 path1
A CLK1 CLK2
D Q FF2 QB
path2
D Q path3 FF3 QB
Z
path1
CLK2 path4
Timing Paths
DEFAULT
path2
path3 path4
Path Groups
Paths are grouped by the clocks controlling their endpoints
The default path group contains all paths not captured by a clock
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Path Exercise
8-8
How many timing paths do you see? How many path groups are there?
CLK_1 CLK_2 Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Path Exercise
8-9 12 timing paths 3 path groups
CLK_1 CLK_2
Clock Group 1 Clock Group 2
Default Group Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Schematic Converted to a Timing Graph
8-10
To calculate total delay, Design Time breaks each path into timing arcs
Each timing arc contributes either a net delay or cell delay
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Components of Static Timing Analysis
Look what’s under the hood of this thing!
8-11
What components are used in STA path delay calculations?
Cell delay models Linear and Nonlinear
Wire load models Pre-layout estimates of wire parasitics: How much R? How much C?
Interconnect models (R-C “tree type”) How are R and C distributed?
Design Time
Operating conditions How are the delays affected by process, voltage, and temperature?
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
How DesignTime Calculates Cell Delays
8-12
Cell delay model used by the technology library is chosen by the Vendor Cell delays are calculated using one of several cell delay models:
Nonlinear Delay Model
Linear Delay Model
Others…
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Nonlinear Delay Model
RCell
input transition intrinsic delay
RNet
8-13
CNet
Cpin
output response zero load delay
linear delay model
DSlope + DIntrinsic + RCell (CNet , CPin)
nonlinear delay model
f(TInput , RCell , CNet , CPin) + f(RNet, CNet , CPin)
cell delay from 2D table
time-of-flight WLM Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Cell Delay: Nonlinear Delay Models
In the two-dimensional NLDM, output loading and input transition affect the cell delay and output transition
Output transition becomes the next cell’s input transition
There are typically two NLDM tables per cell Example: Output load = 2 fF Input transition = 10 units 3 ........
Output Load (fF)
0
1
2
0
2
3
4
5
10
3
4.5
6
7
20
5
8
10.7
13
Cell Delay = 6 ps
0
1
2
0
1
10
18
10
2
13
25
20
4
16
39
........
........
Cell Delay (ps)
Input Transition
Output Load (fF)
Input Transition
8-14
........
Output Transition (vendor units)
Output Transition = 25 units Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Wire Delay Calculations and Topology
8-15
WLM determines the amount of R and C for a net Tree-type determines R and C distribution for timing calculations • Interconnect delay (DC) is measured from state change at driver pin to state change at each receiving cell’s input pin (same in every branch!) best_case_tree Optimistic
balanced_tree
Load adjacent to driver (net resistance is zero) DC = 0 Each load pin shares equal portion of net’s R and C R/2 DC = ( Rnet / N ) x ( Cnet / N + Cpin ) where N= fanout
C/2
Default
R/2 C/2
worst_case_tree Pessimistic
Assume a lumped RC load DC = Rnet x ( Cnet + Cpins )
R
C Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Operating Conditions
8-16
STA scales each cell and net delay based on process, voltage, and temperature (PVT) variations
Tree type indicates which interconnect model to use
Operating Conditions: Name Library Process Temp Volt Interconnect --------------------------------------------------------------------slow_125_1.62 ssc_core_slow 1.00 125.00 1.62 balanced_tree slow_125_1.62_WCT ssc_core_slow 1.00 125.00 1.62 worst_case_tree
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Edge Sensitivity in Path Delays
8-17
What is the longest path for the circuit below? What is the shortest? Can’t we just add the longest delays and add the shortest delays? library: pin(Z) intrinsic_rise : 1.2; intrinsic_fall : 0.5;
library: pin(Z) intrinsic_rise : 1.5; intrinsic_fall : 0.3;
There is an “edge sensitivity” (called unateness) in a cell’s timing arc
DesignTime keeps track of unateness in each timing path Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Setup Relationship Between Flip-Flops
8-18
The default behavior of Design Compiler is to assume that all data must go from launch to capture edge in one clock cycle. The path between FF1 and FF2 has a max delay constraint of TCLK - FF2libSetup FF1
FF2
Launch Edge FF1
FF2 Default setup check
Capture Edge Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
DesignTime Timing Reports
8-19
Users will typically access DesignTime via the report_timing command
The report_timing command The design is broken down into individual timing paths Each timing path is timed out twice;
once for a rising edge input, and
once with a falling edge input
The critical path (worst violator) for each clock group is found A timing report for each clock group is echoed to the screen
A DesignTime timing report has four major sections Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report: Path Information Section
8-20
**************************************** Report : timing -path full -delay max -max_paths 1 Design : TT Version: 2000.05 Date : Tue Aug 29 18:22:38 2000 **************************************** Operating Conditions: slow_125_1.62 Wire Load Model Mode: enclosed
Library: ssc_core_slow
Startpoint: data1 (input port clocked by clk) Endpoint: u4 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library -----------------------------------------------TT 5KGATES ssc_core_slow Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report: Path Delay Section Individual Contribution to Path Delay
8-21
Running Total of the Path Delay
Point Incr Path --------------------------------------------clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 1.00 1.00 data1 (in) 0.00 1.00 u2/Y (inv1a1) 0.12 1.12 u12/Y (or2a1) 0.26 1.38 u23/Y (mx2d2) 0.23 1.61 u4/D (fdef1a1) 0.00 1.61 data arrival time 1.61
Signal Transition f f r r f f
Total Delay
Net & Cell Delays 0.12
data1
0.0001
Time-of-flight
D U2
Y U12
U23
U4 Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report: Path Required Section
8-22
Clock Edge Point Incr Path ----------------------------------------------clock clk (rise edge) 5.00 5.00 clock network delay (ideal) 0.00 5.00 U4/CLK (fdef1a1) 0.00 5.00 library setup time -0.19 4.81 data required time 4.81
From the Library
Data must be valid by this time
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report: Summary Section
8-23
-----------------------------------------------data required time 4.81 data arrival time -1.61 -----------------------------------------------slack (MET) 3.20
Either (MET) or (VIOLATED)
Timing margin (slack): negative indicates constraint violation
CLK Data Arrival 0
1.61
Data Required
Slack
4.81
5
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report: Options
8-24
report_timing [ [ [ [ [ [ [
-delay max/min ] -to name_list ] -from name_list ] -through name_list ] -input_pins ] -max_paths path_count ] -nets ]
...
Remember, the default behavior of report_timing is to report the path with the worst slack within each path group
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Analysis: Diagnose Synthesis Results
8-25
Spot the whales in the timing report: Where are they? What are they? And why? Point clock (input port clock) (rise edge) input external delay addr31 (in) u_proc/address31 (proc) u_proc/u_dcl/int_add[7] (dcl) u_proc/u_dcl/U159/Q (NAND3H) u_proc/u_dcl/U160/Q (NOR3F) u_proc/u_dcl/U186/Q (AND3F) u_proc/u_dcl/U86/Q (INVF) u_proc/u_dcl/U135/Q (NOR3B) u_proc/u_dcl/U136/Q (INVF) u_proc/u_dcl/U100/Q (NBF) u_proc/u_dcl/U95/Q (BF) u_proc/u_dcl/U96/Q (BF) u_proc/u_dcl/U94/Q (NBF) u_proc/u_dcl/U93/Q (NBF) u_proc/u_dcl/ctl_rs_N (dcl) u_proc/u_ctl/ctl_rs_N (ctl) u_proc/u_ctl/U126/Q (NOR3B) u_proc/u_ctl/U120/Q (NAND2B) u_proc/u_ctl/U99/Q (NBF) u_proc/u_ctl/U122/Q (OR2B) u_proc/u_ctl/read_int_N (ctl) u_proc/int_cs (proc) u_int/readN (int) u_int/U39/Q (NBF) u_int/U17/Q (INVB) u_int/U16/Q (AOI21F) u_int/U60/Q (AOI22B) u_int/U68/Q (INVB) u_int/int_flop_0/D (DFF) data arrival time
Incr 0.00 22.40 0.00 1.08 0.00 0.62 0.75 1.33 0.64 1.36 0.49 0.87 0.44 0.45 0.84 0.94 0.00 0.00 1.78 1.07 0.88 10.72 0.00 0.00 0.00 1.29 1.76 2.49 1.43 1.81 0.00
Path 0.00 22.40 22.40 23.48 23.48 24.10 24.85 26.18 26.82 28.17 28.67 29.54 29.98 30.43 31.27 32.21 32.21 32.21 33.98 35.06 35.94 46.67 46.67 46.67 46.67 47.95 49.71 52.20 53.63 55.44 55.44 55.44
f f f f r f f r f r r f r r r r r f r r r r r r r f r f r r
Rather late arrival for a 30 ns period! Six buffers back to back?!
11 ns delay for an OR gate is not good
Four hierarchical partitions
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report Exercise dc_shell> dc_shell> report_timing report_timing **************************************** **************************************** Report Report :: timing timing -path -path full full -delay -delay max max -max_paths -max_paths 11 Design Design :: AM2910 AM2910 Version: 1998.08 Version: 1998.08 Date Date :: Thu Thu Feb Feb 11 11 10:53:32 10:53:32 1999 1999 **************************************** ****************************************
8-26 What Whattype typeof ofstartpoint startpointdoes doesthis this path pathhave have(input (inputport portor orregister? register?
What Whattype typeof ofendpoint endpointdoes doesthis this path pathhave? have?
Operating Operating Conditions: Conditions: WCCOM WCCOM Library: lsi10k Library: lsi10k Wire Wire Loading Loading Model Model Mode: Mode: top top Design Wire Library Design Wire Loading Loading Model Model Library ----------------------------------------------------------------------------------------------AM2910 30x30 lsi10k AM2910 30x30 lsi10k Startpoint: Startpoint: U3/OUTPUT_reg[12] U3/OUTPUT_reg[12] (rising (rising edge-triggered edge-triggered Flip-Flop Flip-Flop clocked clocked by by CLOCK) CLOCK) Endpoint: U2/OUTPUT_reg[2] Endpoint: U2/OUTPUT_reg[2] (rising (rising edge-triggered edge-triggered Flip-Flop Flip-Flop clocked clocked by by CLOCK) CLOCK) Path Group: CLOCK Path Group: CLOCK Path Path Type: Type: max max Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report Exercise (cont) Point Incr Path Point Incr Path --------------------------------------------------------------------------------------------------clock 0.00 0.00 clock CLOCK CLOCK (rise (rise edge) edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock network delay (ideal) 0.00 0.00 U3/OUTPUT_reg[12]/CP (FD1) 0.00 0.00 U3/OUTPUT_reg[12]/CP (FD1) 0.00 0.00 rr U3/OUTPUT_reg[12]/Q 3.97 3.97 U3/OUTPUT_reg[12]/Q (FD1) (FD1) 3.97 3.97 rr .. .. .. .. .. .. .. .. .. .. U3/U148/Z 2.90 17.25 U3/U148/Z (IV) (IV) 2.90 17.25 rr U3/ZERO 0.00 17.25 U3/ZERO (REGCNT) (REGCNT) 0.00 17.25 rr U5/REGCNT_ZERO 0.00 17.25 U5/REGCNT_ZERO (CONTROL) (CONTROL) 0.00 17.25 rr U5/U230/Z 0.64 17.88 U5/U230/Z (ND2) (ND2) 0.64 17.88 ff U5/U232/Z 2.77 19.65 U5/U232/Z (XOR2) (XOR2) 2.77 19.65 ff U5/U236/Z 1.75 21.15 U5/U236/Z (IVA) (IVA) 1.75 21.15 rr U5/U193/Z 1.38 22.53 U5/U193/Z (ND4) (ND4) 1.38 22.53 ff U5/Y_CONTROL[1] 0.00 22.53 U5/Y_CONTROL[1] (CONTROL) (CONTROL) 0.00 22.53 ff U4/OPERATION[1] 0.00 22.53 U4/OPERATION[1] (Y) (Y) 0.00 22.53 ff U4/core/MUXOUT[1] 7.24 29.77 U4/core/MUXOUT[1] (Y_core) (Y_core) 7.24 29.77 rr U4/MUXOUT[1] 0.00 29.77 U4/MUXOUT[1] (Y) (Y) 0.00 29.77 rr U2/DATA[12] 0.00 29.77 U2/DATA[12] (UPC) (UPC) 0.00 29.77 rr .. .. .. .. .. .. .. .. .. .. U2/U62/Z 1.92 38.90 U2/U62/Z (AN2) (AN2) 1.92 38.90 ff U2/OUTPUT_reg[2]/D 0.01 38.91 U2/OUTPUT_reg[2]/D (FD1) (FD1) 0.01 38.91 ff data 38.91 data arrival arrival time time 38.91
8-27 How Howmany manylevels levelsof of hierarchy hierarchydoes doesthis this path pathtraverse? traverse?
Do Doany anycells cellsappear appear to tohave haveaarelatively relatively large largedelay? delay?
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report Exercise (cont)
8-28
Does Doesthe thepath pathmeet meettiming? timing? What Whatis isthe thepercentage percentageviolation? violation?
clock 30.00 30.00 clock CLOCK CLOCK (rise (rise edge) edge) 30.00 30.00 clock network delay (ideal) 0.00 30.00 clock network delay (ideal) 0.00 30.00 clock uncertainty 0.00 30.00 clock uncertainty 0.00 30.00 U2/OUTPUT_reg[2]/CP (FD1) 30.00 U2/OUTPUT_reg[2]/CP (FD1) 30.00 rr library -0.80 29.20 library setup setup time time -0.80 29.20 data required time 29.20 data required time 29.20 ----------------------------------------------------------------------------------------------------------------------------data 29.20 data required required time time 29.20 data arrival time -38.91 data arrival time -38.91 ----------------------------------------------------------------------------------------------------------------------------slack -9.71 slack (VIOLATED) (VIOLATED) -9.71
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary
8-29
Use report_timing to get detailed information about the critical path:
clock period
slack
operating condition used
wire load model used
network delay
skew
setup/hold times
partitions
net delay
net names Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 2 DAY 2
Unit
9-1 Topic
5
Timing and Area
6
Environmental Attributes
7
Time and Load Budgeting
8
Timing Analysis
9
DC Tcl - Introduction
Lab
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
9-2
After completing this unit, you should be able to:
Use online help to determine the syntax of a command
Define data types supported by DC-Tcl
Use DC-Tcl to assign a value to variables
Write a simple DC-Tcl script to automate common DC tasks, including:
Reading in Designs
Constraining a Design
Compiling a Design
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Tired of Working? Man, I'm tired of sitting at this terminal.
9-3 DC-Tcl script!!
I sure wish I could have my compile done automatically.
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
What is Tcl?
9-4
Tcl = Tool Command Language
An "open", industry-standard language
Developed at UCA Berkeley
Offers many powerful “C-shell” style features
References:
Tcl and the Tk Toolkit, John K. Ousterhout
Practical Programming in Tcl and Tk, Brent B. Welch
Visual Tcl, David Young
www.scriptics.com
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Why Tcl?
Tcl is becoming an industry standard for tools
Tcl is more powerful than dc_shell
9-5
much more extensive online help lists AND arrays are supported user-defined procedures case construct, string manipulation and comparison, file manipulation more
Synopsys tools that use Tcl for consistency:
Design Compiler
Formality
PrimeTime
Physical Compiler
Chip Architect, etc…
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Converting from dc_shell to dc_shell-t
9-6
For users who wish to migrate from "old" dc_shell to DC-Tcl, an automated program has been written UNIX% dc-transcript
my_script.scr
my_script.tcl
Will convert most commands in existing scripts to Tcl
Only goes from DCSH to DC-Tcl
Called from the UNIX prompt
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Executing DC-Tcl Script
9-7
There are two ways to execute commands in DC-Tcl:
Interactively from DC-Tcl: dc_shell-t> dc_shell-t> source source my.tcl my.tcl
Execute from UNIX: UNIX% UNIX% dc_shell-t dc_shell-t -f -f my.tcl my.tcl UNIX% UNIX% dc_shell-t dc_shell-t -f -f my.tcl my.tcl >> my.log my.log UNIX% UNIX% dc_shell-t dc_shell-t -f -f my.tcl my.tcl || tee tee my.log my.log
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Getting Help
9-8
To Get a Basic Summary of all DC-Tcl Commands dc_shell-t> dc_shell-t> help help Procedures: Procedures: Builtins: Builtins: after, after, alias, alias, append, append, apropos, apropos, array, array, break, break, catch, catch, cd, cd, clock, clock, close, close, concat, concat, continue, continue, create_command_group, create_command_group, define_proc_attributes, define_proc_attributes, echo, echo, eof, eof, error, error, error_info, error_info, eval, eval, exec, exec, exit, exit, expr, expr, fblocked, fblocked, fconfigure, fconfigure, .. .. ..
Default Default Command Command Group: Group: add_module, add_module, add_to_collection, add_to_collection, all_clocks, all_clocks, all_cluster_cells, all_cluster_cells, all_clusters, all_clusters, all_connected, all_connected, all_critical_cells, all_critical_cells, all_critical_pins, all_critical_pins, all_designs, all_designs, all_inputs, all_inputs, all_outputs, all_outputs, all_registers, all_registers, analyze, analyze, balance_buffer, balance_buffer, balance_registers, balance_registers, bc_check_design, bc_check_design, .. .. .. DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Getting Help (cont)
9-9
Use a Wildcard to Find a Command dc_shell-t> dc_shell-t> help help *clock *clock clock ## Builtin clock Builtin create_clock ## create_clock create_clock create_clock create_test_clock ## create_test_clock create_test_clock create_test_clock remove_clock ## remove_clock remove_clock remove_clock remove_propagated_clock remove_propagated_clock ## remove_propagated_clock remove_propagated_clock report_clock ## report_clock report_clock report_clock set_propagated_clock ## set_propagated_clock set_propagated_clock set_propagated_clock
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
More Help!
9-10
Use help -verbose for command syntax information: dc_shell-t> help -verbose set_input_delay set_input_delay [-clock clock_name] [-clock_fall] [-level_sensitive] [-rise] [-fall] [-max] [-min] [-add_delay] delay_value port_pin_list
# set_input_delay (relative clock) (delay is relative to falling edge of clock) (delay is from level-sensitive latch) (specifies rising delay) (specifies falling delay) (specifies maximum delay) (specifies minimum delay) (don't remove existing input delay) (path delay) (list of ports and/or pins)
Use Useman mancommand command(from (fromeither eitherthe theUNIX UNIXprompt promptor or dc_shell-t) dc_shell-t)for forthe theentire entireUNIX UNIXmanpage manpageon onaacommand command DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Comments in DC-Tcl
9-11
## Comments Comments in in Tcl Tcl are are line-oriented line-oriented ## If If you you wish wish to to comment comment on on the the same same line, line, be be sure sure to to use use ## aa semicolon semicolon before before the the comment: comment: set set header_str header_str “Output “Output Header”; Header”; ## Same Same line line comment comment
This semicolon is required!
Comment a line in a DC-Tcl script using the ‘#’ character
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Nesting Commands and Quoting
9-12
Commands are nested using square brackets: dc_shell-t> dc_shell-t> set_output_delay set_output_delay 55 -clock -clock CLK CLK [all_outputs] [all_outputs]
Two ways of quoting text:
weak quoting with “ “ dc_shell-t> dc_shell-t> set set aa 55 dc_shell-t> dc_shell-t> set set ss “temp “temp == data[$a]” data[$a]” temp temp == data[5] data[5]
rigid quoting with { } dc_shell-t> dc_shell-t> set set ss {temp {temp == data[$a]} data[$a]} temp temp == data[$a] data[$a] DC Tcl - Introduction
Synopsys 31833-000-S16
Chip Synthesis Workshop
Using Wildcards
9-13
Tcl supports two wildcard characters:
? will match exactly one character (PrimeTime only)
* will match zero to ‘n’ characters
Examples: dc_shell-t> help create* dc_shell-t> set_input_delay 5 -clock CLK [get_ports BUS*]
\
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Tcl Data Types
9-14
DC-Tcl supports the following data types:
Real
Integer
String
Lists
Collections
Tcl also supports arrays containing one or more of these data types
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Using Variables
9-15
Variables are created and assigned using the Tcl set command dc_shell-t> dc_shell-t> set set my_var my_var 10 10 To reference a variable, it must be preceded with a “$” dc_shell-t> dc_shell-t> set set my_New_Var my_New_Var $my_var $my_var To print variables dc_shell-t> dc_shell-t> echo echo $my_var $my_var To remove variables dc_shell-t> dc_shell-t> unset unset my_var my_var DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Using Variables: Exercise
9-16
What will be the result of executing the following commands? dc_shell-t> dc_shell-t> set set clock_period clock_period 10 10 10 10 dc_shell-t> dc_shell-t> echo echo clock_period clock_period ______________________ ______________________
dc_shell-t> dc_shell-t> echo echo “clock “clock period period == ““ $clock_period $clock_period ______________________ ______________________
dc_shell-t> dc_shell-t> echo echo “Frequency “Frequency == ““ 1/$clock_period 1/$clock_period ______________________ ______________________
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Arithmetic Expressions
9-17
Tcl is string-oriented
To evaluate arithmetic expressions, use the expr command
dc_shell-t> dc_shell-t> set set period period 10.0 10.0 10.0 10.0
necessary whitespace
dc_shell-t> dc_shell-t> set set freq freq [expr [expr (1 (1 // $period)] $period)] 0.1 0.1 dc_shell-t> dc_shell-t> echo echo “Freq “Freq =“ =“ [expr [expr $freq $freq ** 1000] 1000] “MHz” “MHz” Freq Freq == 100.0 100.0 MHz MHz dc_shell-t> dc_shell-t> set_load set_load [expr [expr [load_of [load_of cba_core/and2a0/A] cba_core/and2a0/A] ** 5] 5] \\ [all_outputs] [all_outputs]
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Using Lists in dc_shell-t
9-18
Lists are a component of Tcl
A list is one string, containing items separated by white space dc_shell-t> dc_shell-t> set set L1 L1 {el1 {el1 el2 el2 el3} el3} el1 el1 el2 el2 el3 el3 dc_shell-t> dc_shell-t> echo echo $L1 $L1 el1 el2 el3 el1 el2 el3 dc_shell-t> dc_shell-t> set set Num_of_List_Elements Num_of_List_Elements [llength [llength $L1] $L1] 33 dc_shell-t> dc_shell-t> set set link_library link_library {*} {*} ** dc_shell-t> dc_shell-t> lappend lappend link_library link_library tc6a.db tc6a.db opcon.db opcon.db ** tc6a.db tc6a.db opcon.db opcon.db dc_shell-t> dc_shell-t> echo echo $link_library $link_library ** tc6a.db tc6a.db opcon.db opcon.db DC Tcl - Introduction
Synopsys 31833-000-S16
Chip Synthesis Workshop
Definitions: Objects and Attributes
Recall that designs consist of objects
designs, cells, references, ports, pins, clocks, and nets
In order to keep track of circuit functionality and timing, DC attaches many attributes to each of these objects
9-19
ports can have the following attributes: direction
driving_cell
max_capacitance
others. . .
designs can have the following attributes: area
operating_conditions_max
max_area
others…
Standard Tcl data formats (lists, strings) are not adequate to keep track of circuit elements and their attributes! DC Tcl - Introduction
Synopsys 31833-000-S16
Chip Synthesis Workshop
Definitions: Collection & Collection Handle
9-20
In order to keep track of circuit objects and their attributes, DC-Tcl contains an extension to standard Tcl -- collections
Collection:
A set of design objects which DC internally stores and refers to by a name, the collection handle
Collections are created by a get_ or all_ commands
Collection handle:
A handle, or pointer, to a collection
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Creating Collections
9-21
Here is a partial list of DC-Tcl commands that create collections: get_cells get_cells get_clocks get_clocks get_designs get_designs get_libs get_libs get_nets get_nets get_pins get_pins get_ports get_ports
## Create Create aa collection collection of of cells cells ## Create Create aa collection collection of of clocks clocks ## Create Create aa collection collection of of designs designs ## Create a collection of libraries Create a collection of libraries ## Create Create aa collection collection of of nets nets ## Create Create aa collection collection of of pins pins ## Create Create aa collection collection of of ports ports
all_clocks all_clocks all_designs all_designs all_inputs all_inputs all_outputs all_outputs all_registers all_registers
## Create Create aa collection collection of of all_clocks all_clocks ## Create Create aa collection collection of of all_designs all_designs ## Create Create aa collection collection of of all_inputs all_inputs ## Create Create aa collection collection of of all_outputs all_outputs ## Create Create aa collection collection of of all_registers all_registers
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Collections Are Referenced by a Handle 9-22 dc_shell-t> dc_shell-t> set set mylist mylist {a {a bb hello hello world} world} aa bb hello hello world world dc_shell-t> dc_shell-t> llength llength $mylist $mylist 44 dc_shell-t> dc_shell-t> set set foo foo [all_inputs] [all_inputs] {"Clk", {"Clk", "Reset", "Reset", "Crnt_Instrn[31]", "Crnt_Instrn[31]", ... ... "Crnt_Instrn[0]"} "Crnt_Instrn[0]"} dc_shell-t> dc_shell-t> llength llength $foo $foo 11 dc_shell-t> dc_shell-t> echo echo $foo $foo Collection Handle _sel5 _sel5 dc_shell-t> dc_shell-t> sizeof_collection sizeof_collection $foo $foo 34 34 dc_shell-t> dc_shell-t> query_objects query_objects $foo $foo {"Clk", {"Clk", "Reset", "Reset", "Crnt_Instrn[31]", "Crnt_Instrn[31]", ... ... "Crnt_Instrn[0]"} "Crnt_Instrn[0]"}
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Manipulating Collections
9-23
dc_shell-t> dc_shell-t> help help *collection* *collection* add_to_collection add_to_collection compare_collections compare_collections copy_collection copy_collection filter_collection filter_collection
## Add Add object(s) object(s) ## compares compares two two collections collections ## Make Make aa copy copy of of aa collection collection ## Filter Filter aa collection, collection, resulting resulting in in aa new new collection collection foreach_in_collection foreach_in_collection ## Iterate Iterate over over aa collection collection index_collection ## Extract index_collection Extract object object from from collection collection remove_from_collection remove_from_collection ## Remove Remove object(s) object(s) from from aa collection collection sizeof_collection ## Number sizeof_collection Number of of objects objects in in aa collection collection sort_collection ## Create sort_collection Create aa sorted sorted copy copy of of aa collection collection
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Manipulating Collections (cont)
Add objects to a collection using add_to_collection
Remove objects from a collection using remove_from_collection
9-24
dc_shell-t> dc_shell-t> set set pci_ports pci_ports [get_ports [get_ports “DATA*”] “DATA*”] dc_shell-t> dc_shell-t> set set pci_ports pci_ports [add_to_collection [add_to_collection $pci_ports $pci_ports \\ [get_ports [get_ports “CTRL*”]] “CTRL*”]] dc_shell-t> \\ dc_shell-t> set set all_inputs_except_clk all_inputs_except_clk [remove_from_collection [remove_from_collection [all_inputs] [all_inputs] [get_ports [get_ports “CLK”]] “CLK”]] DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Collection Usage: Example
9-25
## Constrain Constrain aa design design for for timing, timing, using using aa time time budget budget set set CLK_PER CLK_PER set time_budget set time_budget
10.0; 10.0; ## clock clock period period (ns) (ns) 40.0; # percentage of 40.0; # percentage of clock clock period period ## allowed for input/output allowed for input/output logic logic
## calculate calculate intermediate intermediate variables variables set set IO_DELAY IO_DELAY [expr [expr (( (1-$time_budget/100.0) (1-$time_budget/100.0) ** $CLK_PER)] $CLK_PER)] set set all_except_clk all_except_clk [remove_from_collection [remove_from_collection \\ [all_inputs] [all_inputs] [get_ports [get_ports CLK] CLK] ]] ## constrain constrain the the design design for for timing timing create_clock -period $CLK_PER create_clock -period $CLK_PER -name -name MY_CLOCK MY_CLOCK [get_ports [get_ports Clk] Clk] set_input_delay set_input_delay $IO_DELAY $IO_DELAY -max -max -clock -clock MY_CLOCK MY_CLOCK \\ $all_except_clk $all_except_clk set_output_delay set_output_delay $IO_DELAY $IO_DELAY -max -max -clock -clock MY_CLOCK MY_CLOCK \\ [all_outputs] [all_outputs] DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Filtering Collections
9-26
Use the filter_collection command 1
filter_collection filter_collection [get_cells] [get_cells] “ref_name “ref_name == == AN2” AN2” 2
filter_collection filter_collection [get_cells] [get_cells] “is_mapped “is_mapped == == true” true”
Use -filter option 3
get_cells get_cells -filter -filter “@dont_touch “@dont_touch == == true” true” 4
set set fastclks fastclks [get_clocks [get_clocks -filter -filter “@period “@period << 10”] 10”] DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Running dc_shell-t Interactively
9-27
Name common UNIX commands can you run in dc_shell-t? dc_shell-t> dc_shell-t> ___ ___ ;; ___ ___ ;; ___ ___
What are the commands for these tasks? Show Showthe thehistory historyof ofcommands commandsentered: entered: dc_shell-t> ___ dc_shell-t> ___ Repeat Repeatlast lastcommand: command: dc_shell-t> dc_shell-t> ___ ___ Execute Executecommand commandno. no.77from fromthe thehistory historylist: list: dc_shell-t> dc_shell-t> ___ ___ Execute Executethe thelast lastreport_ report_command: command: dc_shell-t> dc_shell-t> ___ ___ DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 9: Introduction LAB
9-28
60 min
Create two generic Tcl scripts unmapped PRGRM_CNT_TOP.db
constraints.tcl create_clock set_input_delay ...
runit.tcl read_db ... source constraints.tcl compile report_constraint write . . .
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 3 DAY 3
Unit
10-1
Topic
10
Timing Revisited
11
Optimization
12
Compile Strategies
13
Compiling a Hierarchical Design
14
DC Tcl - Procedures
Lab
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
10-2
After completing this unit, you should be able to:
Model non-ideal clock effects
Create and use virtual clocks
Constrain a multiple clock design (synchronous clocks)
Constrain a multiple clock design (asynchronous clocks)
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
RTL Block Synthesis Write RTL HDL Code
Rewrite
No Yes Major Violations?
10-3
Simulate OK?
Yes No
Synthesize HDL Code To Gates
Constraints & Attributes Area & Timing Goals
Netlist Analysis
No
Met Constraints?
Yes Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Recall Timing Constraints From Unit 5
10-4
TO_BE_SYNTHESIZED D Q FF1 QB
M
N
D Q FF2 QB
X
D Q FF3 QB
T
S
D Q FF4 QB
Clk
set_output_delay
set_input_delay create_clock ( period )
create_clock ( period )
create_clock ( period )
Method: 1. Define the clock 2. Define the I/O timing relative to the clock Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Goals: Part Two
10-5
Modeling Real-Life Clocks
Multiple Clocks - Synchronous
Multiple Clocks - Asynchronous
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Modeling Clock Trees
10-6
Design Compiler is NOT used for synthesis of the clock tree. Clock tree synthesis is usually done by the vendor, based on physical placement data.
D_In D_In
D Q FF1
D Q FF2
D Q FF1 D Q FF2
CLK CLK
Logical Circuit
Post-Layout Circuit
What design considerations need to be taken into account by the synthesis tool, prior to layout? Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Modeling Uncertainty on Clock Edges D_In
10-7
D Q FF1 D Q FF2
CLK TU
Post-Layout Circuit
To account for varying delays between the clock network branches (commonly called clock skew): set_clock_uncertainty TU [get_clocks CLK] placed on clock objects
Default clock skew is zero Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
set_clock_uncertainty and Setup Timing 10-8 Example: create_clock -period 10 [get_ports CLK] set_clock_uncertainty 0.5 [get_clocks CLK] D Q FF1
X
D Q FF2
FF1 Data Launch Edge (No uncertainty!)
FF2 setup check at: 10 - 0.5 - 0.2 = 9.3
/ /
0
5 Max allowable delay for block “X”
9.3 9.5 10 Assume lib setup = 0.2ns Timing Revisited
Synopsys 31833-000-S16
Chip Synthesis Workshop
Model Source Latency
10-9
Source latency is the propagation time from the actual clock origin to the clock definition point in the design
Use for either ideal or propagated clocks
create_clock -per 10 [get_ports CLK] set_clock_latency -source 3 CLK set_propagated_clock CLK YOUR_DESIGN Network Latency CLK 3ns
1ns
D
Q
CLK
Origin of Clock Source Latency Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Pre/Post Layout Clock
10-10
ideal clock
uncertainty
transition
latency [ jitter 0.2 + skew 0.4 ] 抖动 ＋ 时滞
pre-layout create_clock -p 30 -n MCLK Clk set_clock_uncertainty 0.6 MCLK set_clock_latency -source 4 MCLK
post-layout set_propagated_clock MCLK
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Clocks: Synchronous
10-11
Modeling Real-Life Clocks
Multiple Clocks - Synchronous
Multiple Clocks - Asynchronous
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Synchronous Multiple Clock Designs
10-12
TO_BE_SYNTHESIZED CLKD
CLKA
N
D Q FF2 QB
X
D Q FF3 QB
S
CLKC
CLKB
CLKE
What is different? A: Multiple clock sources All derived from the same clock source Some clocks do not have a corresponding clock port on our design Multiple constraints on a single port What do we do now? Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Answer: Use Virtual Clocks!
10-13
What are virtual clocks? A: Clocks in the environment of the design to be synthesized that:
Are defined clock objects within Design Compiler’s memory Do not clock any sequential devices within the current_design
Serve as references for input or output delays
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Creating a Virtual Clock
10-14
How do I create a virtual clock? A: It’s the same as defining a clock, but don’t specify a clock pin or port You must name your virtual clock, since there’s no clock port for the virtual clock Example: create_clock Must be named
-name vTEMP_CLK
-period 20
No source pin or port!
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Goals for Multiple Clock Designs ÷9 ÷6 ÷4 ÷3
300 MHz
10-15
CLKA CLKC CLKD CLKE
TO_BE_SYNTHESIZED
N
CLKA (33 Mhz)
D Q FF2
CLKC (50 Mhz)
X
D
Q
S
CLKD (75 Mhz)
FF3
CLKE (100 Mhz)
Method is the same as that for single clock designs: 1. Define the clock(s), using virtual clocks if necessary 2. Specify I/O delays relative to the clock(s)
Design Compiler will determine which clock imposes the most restrictive constraint on the design Timing Revisited
Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Clock Input Delay: Example
10-16
create_clock create_clock -period -period 30 30 -name -name CLKA CLKA create_clock create_clock -period -period 20 20 [get_ports [get_ports CLKC] CLKC] set_dont_touch_network set_dont_touch_network [get_clocks [get_clocks CLKC] CLKC] set_input_delay set_input_delay 5.5 5.5 -clock -clock CLKA CLKA -max -max [get_ports [get_ports IN1] IN1]
5.5 ns TO_BE_SYNTHESIZED
IN1 300 MHz
CLKA ÷9 ÷6
0.5 ns CLK-Q
5 ns
N CLKC
tN
CLKC
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Clock Input Delay Example -Waveforms 300 MHz
10-17 ÷6
CLKC
÷9
CLKA
CLKA
CLKC 0
10
20
30
40
50
60
10 ns
For the example shown, input logic cloud of TO_BE_SYNTHESIZED must meet:
tN < 10 - 5.5 - tsetup Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Clock Output Delay: Example
10-18
create_clock -period [expr (1.0/75*1000)] -name CLKD create_clock -period 10
-name CLKE
set_dont_touch_network
÷4 ÷6 ÷3
300 MHz
create_clock -period 20 [get_ports CLKC] [get_clocks CLKC]
CLKD CLKC CLKE
set_output_delay -max 2.5 -clock CLKD [get_ports OUT1] set_output_delay -max 4.5 -clock CLKE -add_delay [get_ports OUT1] 2.5 ns TO_BE_SYNTHESIZED
2ns
0.5 ns SETUP
OUT1
S
CLKD
tS CLKC
4 ns
0.5 ns SETUP
CLKE 4.5 ns Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Clock Output Delay Example -Waveforms
300 MHz
10-19 ÷4 ÷6 ÷3
CLKD CLKC CLKE
6.7
CLKD CLKC CLKE 10
0
20
30
40
10
For the example shown, output logic cloud of TO_BE_SYNTHESIZED must meet: tS < 10 - 4.5
AND
tS < 6.7 - 2.5 Timing Revisited
Synopsys 31833-000-S16
Chip Synthesis Workshop
Hints for Multiple Clock Designs
10-20
By definition, all clocks used with Design Compiler are synchronous
You can not create asynchronous clocks with the create_clock command.
DC will determine every possible data launch/data capture time, and synthesize to the most conservative
DC builds a common base period for all clocks
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Clocks: Asynchronous
10-21
Modeling Real-Life Clocks
Multiple Clocks - Synchronous
Multiple Clocks - Asynchronous
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Asynchronous Multiple Clock Designs
10-22
TO_BE_SYNTHESIZED CLKD
CLKA
CLKB
N
D Q FF2 QB
X
D Q FF3 QB
S
CLKC CLKE
What is different? A: Multiple clock sources & sinks All Asynchronous Clocks do not have a corresponding clock port on our design What do we do now? Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesizing with Asynchronous Clocks 10-23
It is the user’s responsibility to account for the metastability Instantiate double-clocking, metastable-hard Flip-Flops dual-port FIFO etc..
The user must then disable timing-based synthesis on any path which crosses an asynchronous boundary
This will prevent DC from wasting time trying to get the asynchronous path to “meet timing”
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
The set_false_path command
10-24
How do we disable timing-based synthesis for asynchronous paths? A: Use the set_false_path command
A false path is a path for which we wish to ignore timing constraints
set_false_path can be used to disable timingbased synthesis on a path-by-path basis
Useful for:
Constraining asynchronous paths
Constraining logically false paths
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
set_false_path: Example
10-25
TOP Des_A
Des_B
CLKA (100 Mhz from OSC1)
N
D
Q
D Q
X
D Q
CLKB (100 Mhz from OSC2)
current_design TOP /* Make sure register-register paths meet timing */ create_clock -period 10 [get_ports CLKA] create_clock -period 10 [get_ports CLKB] /* Don’t optimize logic crossing clock domains */ set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB] compile Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Goals Summary
10-26 Defines output timing requirements set_output_delay
Define input arrival time relative to clock set_input_delay
Models skew on clock source set_clock_uncertainty
Define clock source create_clock set_dont_touch_network
LOGIC CLOUD
LOGIC CLOUD
Exceptions to single-cycle behavior: set_false_path
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
check_timing
10-27
Paths which are not completely or properly constrained may not appear in violation reports
Analysis should flag unconstrained paths so the problems can be corrected, e.g., by adding constraints dc_shell-t> dc_shell-t> check_timing check_timing
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 10: Introduction
10-28
45 min LAB
Add skew and run timing reports constraints.tcl
runit.tcl
mapped
compile
PRGRM_CNT_TOP.db
Run timing reports
Timing Report
Timing Report
Timing Report
Timing Report
default
min
pins
nets Timing Revisited
Synopsys 31833-000-S16
Chip Synthesis Workshop
Appendix
10-29
Multicycle Paths
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multi-Cycle Behavior
10-30
Situation: Not all paths operate at the target frequency of the design
SYSTEM_SYNCH_SET FF4
DATA
FF1
64 x 64 MULTIPLIER
FF2
CLK
Choose one of the following options: 1. Add pipeline stage(s) to divide the logic into single-cycle paths 2. Ease off the single-cycle requirement: allow more clock cycles
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Checks on Multicycle Paths
10-31
The hold check is related to the setup check
The default hold check is one edge before the setup 0
1
2
2-cycle example
setup check default hold check Tp < delay < 2Tp
dc_shell-t> set_multicycle_path 2 -from A -to B
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multicycle Path: Example
10-32
We want Design Compiler to allow two clock cycles for BIG_LOGIC: FF3
FF1
AD
BIG_LOGIC
FF4
FF2
CLK
set_multicycle_path 2 -setup -from [get_cells FF1] -to [get_cells FF2]
set_multicycle_path 1 -hold -from [get_cells FF1] -to [get_cells FF2]
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 3 DAY 3
Unit
11-1
Topic
10
Timing Revisited
11
Optimization
12
Compile Strategies
13
Compiling a Hierarchical Design
14
DC Tcl - Procedures
Lab
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
11-2
After completing this unit, you should be able to:
List the three phases of optimization
List three architecture-level optimizations
List two types of logic-level optimizations
Identify the two gate-level optimizations
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Three Phases of Optimization
11-3
Optimization can occur at each of three levels: HDL Description or unmapped db
mapped db
Architectural
Logic-Level
Gate-Level
High-Level Synthesis
Structure & Flatten
Mapping
Optimized Netlist Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Architectural Optimization
HDL Description or unmapped db
11-4
DesignWare Implementation Selection
Architectural
Sharing Common Subexpressions Resource Sharing
mapped db
Reordering Operators
Logic-Level
Gate-Level
Structure & Flatten
Mapping
Optimized Netlist Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Arithmetic Operators
11-5
For the code: if (int0) y <= busA + busB; else y <= busC + busD;
What type of circuit is implied by the “+” sign? What type of adder should be synthesized? How many adders will appear in the final circuit?
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
DesignWare Implementation Selection
11-6
Multiple architectures for each macro allow DC to evaluate speed/area tradeoffs and choose the best implementation fastest
Ripple Carry Select
Z <= A + B; Conditional Sum Synthesis
DW Foundation
Brent-Kung
+
Carry Look-Forward HDL Operator
Carry Look-Ahead smallest
Ripple Carry
DW Basics
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
DesignWare Foundation
AND Gates, OR Gates, Flip-Flops...
target_library
Technology Library
Adders, Multipliers, Comparators...
11-7
synthetic_library
DesignWare Library
Hardcoding of {standard.sldb} is implicit to always provide basic implementations of +, -, *, >=, <, <= etc…
The synthetic_library variable points to a list of synthetic library database files (.sldb):
set synthetic_library “dw_foundation.sldb” Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Other High-Level Optimizations
Sharing Common Subexpressions
Resource Sharing
Operator Reordering
11-8
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Sharing Common Sub-Expressions
11-9
DC can “share” common mathematical sub-expressions B C A
A
SUM1 <= A + B + C; SUM2 <= A + B + D; SUM3 <= A + B + E;
E A
B
C
+
+
Implies D
B D A
B E
+
+
+
+
SUM1
SUM2
SUM3
E
+ +
+
+
SUM1
SUM2
SUM3
Share
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Coding To Force Sharing
11-10
Remember HDL coding can force a specific topology to be synthesized To force a shared topology directly: temp SUM1 SUM2 SUM3
:= <= <= <=
A + B; temp + C; temp + D; temp + E;
B
A
C
D
E
+ +
+
+
SUM1
SUM2
SUM3
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Resource Sharing: Example Given the following HDL description, two different structures might be synthesized:
A
A
+
C SUM
C D
if (SEL = ‘1’) then SUM <= A + B; else SUM <= C + D; end if;
More area-efficient implementation:
Implied implementation:
B
11-11
+
SEL
+
SUM
B D
SEL Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Resource Sharing
11-12
A resource is a DesignWare Component
The following HDL operators imply resources that can be shared:
* + >
>=
<
<=
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Operator Reordering
11-13
Design Compiler can automatically reorder arithmetic operators to produce the fastest designs Example: Z
<=
A + B + C + D
(where Z is time constrained)
Initial ordering is left to right: A B C D
+ + +
Z
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Reordering Operators for Fast Design A
If inputs arrive at the same time, Design Compiler will create a balanced tree architecture
If signal A is late arriving, Design Compiler may reorder the operators
Remember:
11-14
+
B
Z
+ C
+
D
B C D Late A
+ + +
Z
Coding style can force a particular order Z = ( (B+C) + D) + Late_A; Optimization
Synopsys 31833-000-S16
Chip Synthesis Workshop
High-Level Synthesis Is Constraint-Driven 11-15 High-level synthesis is based on design constraints and coding style Very important to specify realistic constraints Design Compiler makes high-level synthesis decisions to produce area-efficient results that meet timing High-Level Synthesis takes place only when optimizing an unmapped design
It will not occur when reoptimizing a gate-level netlist EXCEPTION: DesignWare incremental implementation selection can recur after mapping to gates
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Logic-Level Optimization HDL Description or unmapped db Architectural-Level
mapped db Logic-Level
Gate-Level
11-16
High-Level Synthesis
Structure Flatten
Mapping
Optimized Netlist
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Logic-Level Optimization (cont)
After high-level optimization, circuit function is represented by GTECH parts
Two optimization processes can occur during Logic- Level optimization:
11-17
1. Structuring 2. Flattening
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
What Is Structuring?
11-18
The use of intermediate terms to create a multilevel implementation of a design that satisfies constraints Useful for speed optimization as well as area optimization This is the default logic-level optimization strategy C B A STR
D Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
What Is Flattening?
11-19
The reduction of combinational logic paths to a two-level, sum-of-products (SOP) circuit Useful for speed optimization; may be very area-intensive A B C D SOP
set_flatten true -effort low | medium | high Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Structuring vs. Flattening
11-20
A B C
C B A
vs.
D
D
Structuring
Flattening
Creates intermediate structures to implement design
Removes intermediate structures — reduces design to SOP
Is constraint-based
Is done independent of constraints
Can help both area and speed of a design
Can be very area-intensive
No guarantee that flattening will actually map to a two-level SOP (possible library limitations)
set_structure true | false
set_flatten true | false Optimization
Synopsys 31833-000-S16
Chip Synthesis Workshop
Three Phases of Optimization
11-21
Optimization can occur at each of three levels: Architectural, Logical, and Gate
HDL Description or unmapped db Architectural-Level
High-Level Synthesis
mapped db Logic-Level
Phases of Gate-Level Optimization: 1. Delay 2. DRC I 3. DRC II 4. Area
Structure & Flatten
Combinational
Gate-Level
and Sequential Mapping
Optimized Netlist Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Combinational Mapping
11-22
The process of using gates from the target library to generate a design that meets timing and area goals A B C
A B C
F
A B
gG
F
A B
Gg
A C B A SLOW B
Q
A B
A B SLOW
C
Q
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Sequential Mapping
11-23
Process by which Design Compiler maps to sequential cells from the technology library
Tries to save speed and area by using a more complex sequential cell
0
A
A SEL
D ENA
1
CLK SEL CLK
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Fixing Design Rule Violations
11-24
Technology libraries contain vendor-specific design rules for each cell, e.g. max_capacitance
During mapping, Design RuleConstraints (DRCs) are checked Phases of Gate-Level Optimization: 1. Delay 2. DRC I 3. DRC II 4. Area
Design Compiler tries to fix all design rule violations without affecting area or speed
If no other way can be found, Design Compiler fixes design rule violations at the expense of timing and area
Design Compiler inserts buffers and resizes cells to correct design rule violations Optimization
Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary
11-25
HDL Description or unmapped db
Architectural
mapped db
Logic-Level
Gate-Level
High-Level Synthesis
Structure & Flatten
Mapping
Optimized Netlist
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 3 DAY 3
Unit
12-1
Topic
10
Timing Revisited
11
Optimization
12
Compile Strategies
13
Compiling a Hierarchical Design
14
DC Tcl - Procedures
Lab
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
12-2
After completing this unit, you should be able to: Interrupt compilation List the default priority of constraints Enable DC to work harder on the critical path Explain the difference between a compile and an incremental compile Fix hold time violations
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Compile Completion
12-3
Compile Completion
Compile Strategies
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Compile Complete
12-4
Compiling stops when: All constraints are met Design Compiler reaches a point of diminishing returns User interrupt
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
User Interrupt
12-5
Typing a Ctrl-C during delay optimization will result in the following menu appearing: Please Please type type in in one one of of the the following following option: option: 11 to to Write Write out out the the current current status status of of the the design design 22 to to Abort Abort optimization optimization 33 to to Kill Kill the the process process 44 to to Continue Continue optimization optimization Please Please enter enter aa number: number:
Pressing Ctrl-C three times kills the dc_shell process
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Compile Report
12-6
Beginning Delay Optimization Phase ---------------------------------ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- ------- --------- --------- ------------------0:10:04 2761.7 1.38 3.20 18.1 Zro_Flag_reg/D 0:10:05 2761.7 1.38 3.20 18.1 Zro_Flag_reg/D 0:10:08 2761.7 1.28 3.10 18.1 Zro_Flag_reg/D 0:10:12 2761.7 1.26 3.06 18.1 Zro_Flag_reg/D
Critical Path timing violations
Sum of all timing violations
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Compile Strategies
12-7
Compile Completion
Compile Strategies
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Constraint and Timing Analysis You have performed a default compile. The reports indicate remaining violations. report_constraint -all_violators
12-8
good starting point
Reports all constraints which have been violated in the design Includes design rules, setup, hold and area
report_timing -delay max
Reports the worst timing path for each path group for setup time constraints
report_timing -delay min
Reports the worst timing path for each path group for hold time constraints
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Things to Look for
12-9
During constraint / timing analysis, what should you look for? How large is the worst negative slack (WNS)? Do you have design rule violations? Do you have hold time violations? How many paths are violating timing?
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Big Violations
12-10
dc_shell> report_constraint -all Information: Updating design information... (UID-85) **************************************** Report : constraint -all_violators Design : RISC_CORE Version: 1999.05 Date : Thu Nov 11 09:38:42 1999 **************************************** max_delay/setup ('Clk' group)
A rather big violation
Required Actual Endpoint Path Delay Path Delay Slack --------------------------------------------------------------------------RESULT_DATA[1] 1.20 2.84 r -1.64 (VIOLATED) RESULT_DATA[2] 1.20 2.84 r -1.64 (VIOLATED) RESULT_DATA[8] 1.20 2.84 r -1.64 (VIOLATED) RESULT_DATA[14] 1.20 2.84 r -1.64 (VIOLATED) RESULT_DATA[5] 1.20 2.84 r -1.64 (VIOLATED) RESULT_DATA[11] 1.20 2.84 r -1.64 (VIOLATED)
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
What Should I Do Next?
12-11
Check the constraints Check the partition
Re-compile the optimized netlist Re-compile using a higher effort Change the HDL source code Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Use Re-Compile HDL Architectural
12-12 Entire design will be returned to a GTECH representation
Logic-Level
Gate-Level
Optimized Netlist
dc_shell-t> compile
Logic-level optimization will be performed Gate-level optimization will be performed DesignWare Implementations may still be changed
A successive compile will probably not help, unless you change something!
Modify the constraints Change the set_structure or set_flatten options Change the map effort of compile Compile Strategies
Synopsys 31833-000-S16
Chip Synthesis Workshop
Change the Effort Level compile
12-13
-map_effort (low | medium | high)
Controls how “hard” DC works on the critical path during gate-level optimization low:
Do NOT use for production work or as starting point for other optimizations
medium:
Always start with medium compile effort Default Should produce good results most of the time
high:
Activates additional algorithms Very CPU intensive
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Start from a Changed HDL Source
HDL Architectural
Logic-Level
12-14
Runs through all levels of optimization Takes changes in the HDL source fully into account
Gate-Level
Optimized Netlist
Caveat: The source code might not be available or cannot be changed anymore.
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Small Violations
12-15
dc_shell> report_constraint -all Information: Updating design information... (UID-85) **************************************** Report : constraint -all_violators Design : RISC_CORE Version: 1999.05 Date : Thu Nov 11 09:38:42 1999 **************************************** max_delay/setup ('Clk' group)
Assuming your constraints and partitions are correct, what should you do?
Required Actual Endpoint Path Delay Path Delay Slack --------------------------------------------------------------------------RESULT_DATA[1] 1.20 1.30 r -0.10 (VIOLATED) RESULT_DATA[2] 1.20 1.26 r -0.06 (VIOLATED) RESULT_DATA[8] 1.20 1.26 r -0.06 (VIOLATED) RESULT_DATA[14] 1.20 1.22 r -0.02 (VIOLATED) RESULT_DATA[5] 1.20 1.22 r -0.02 (VIOLATED) RESULT_DATA[11] 1.20 1.22 r -0.02 (VIOLATED)
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Use Incremental Mapping Architectural
Logic-Level
compile
-incremental_mapping
Only gate-level optimization is done
Gate-Level
Optimized Netlist
12-16
The design is not taken back to GTECH” No logic-level optimization DesignWare Implementations may still be changed
Incremental is much faster than regular compile
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Incremental Mapping (cont) compile
Architectural
Logic-Level critical Gate-Level
path
-inc
12-17 -map high
Algorithm only accepts solutions that reduce critical path slack The design will most likely get better or stay the same
Optimized Netlist
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
The set_critical_range Command
12-18
set_critical_range 2 current_design() timing 2ns
paths
This command causes DC to optimize all violating paths within 2ns of the critical path Very CPU and memory intensive. Use with caution!
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
When You Have Design Rule Violations
12-19
Design rule violations may cause timing violations Use the following report commands
report_constraint -all_violators report_net -connections -verbose report_timing -net (for fanout) Added buffer to fix DR
set_max_capacitance 0.1 A
A CLK
N
D Q FF2 QB
A
N
D Q FF2 QB
CLK
compile -only_design_rule Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
What if You Have Hold Time Violations? 12-20 My design works fine for worst case conditions, but when I check it for best case, I have minimum delay violations!
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Hold Time Violations
12-21
What is the minimum delay requirement from FF2 to FF3?
N
(assume 0.5 ns hold requirement on FF3)
D Q FF2 QB
X
D Q FF3 QB
S
CLK
0
0.5
FF2/CLK FF3/CLK FF3/D
VALID Hold
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Let’s Complicate the Picture What is the minimum delay requirement now?
N
12-22
D Q FF2 QB
X
D Q FF3 QB
S
CLK 0.5 0
0.5
1.0
FF2/CLK FF3/CLK VALID
FF3/D
Hold
Hold time requirements are affected by Synopsys 31833-000-S16
Skew on the clock tree network Operating Conditions FF Hold Time
Compile Strategies Chip Synthesis Workshop
Checking for Hold Time Violations
12-23
Typically, you will fix hold time violations after layout
Clock tree timing is not accurate until layout
Fixing “phantom” hold time violations may cause setup violations and increase area
Often, pre-layout hold violations are “fixed” when real net delays are used for hold time analysis
Best-Case operating conditions may assume zero net delay!
Sometimes you may need to fix hold time violations before layout
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Use Simultaneous Min-Max
12-24
Simultaneous Min-Max Optimization
Environment and timing constraints supported for BOTH min and max values Fixes hold time without violating setup time constraints
What constraints should you specify before analyzing and fixing hold time violations? set_clock_uncertainty -hold set_input_delay -min set_output_delay -min set_operating_conditions -min -max
Specify min and max technology library set_min_library max_library -min_version min_library
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Apply set_input_delay for Hold Time
12-25
min 0.3ns TO_BE_SYNTHESIZED D Q FF1 QB
M
N
D Q FF2
X
D Q FF3
S
T
D Q FF4 QB
Clk
set_input_delay -min describes the fastest arrival time of the external logic on the input ports create_clock create_clock -period -period 10 10 [get_ports [get_ports Clk] Clk] set_input_delay set_input_delay -min -min 0.3 0.3 -clock -clock Clk Clk $all_in_ex_clk $all_in_ex_clk If FF2 has THOLD = 1ns: What is the min delay allowed for N? Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Apply set_output_delay for Hold Time 0.3ns
12-26 0.5ns Hold Time Requirement
TO_BE_SYNTHESIZED D Q FF1 QB
M
N
D Q FF2
X
D Q FF3
S
T
D Q FF4 QB
Clk
set_output_delay -min describes the hold time requirement of the external logic on the output ports
If FF has THOLD = 0.5ns and TT = 0.3ns: What is the min output delay?
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Calculation of set_output_delay
12-27
Tmin 0.3ns D Q FF3
S
T
setup = 0.8 hold = 0.5 D Q FF4 QB
Clk
set_output_delay -max (Tmax + FF4setup) set_output_delay -min (Tmin - FF4hold)
create_clock -period 5 [get_ports Clk] set_output_delay -min (0.3-0.5) -clock Clk [all_outputs] -0.2 Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Fixing Hold Violations
12-28
set_fix_hold [all_clocks] compile -only_design_rule By default, DC does NOT fix hold time violations
Use set_fix_hold to tell DC to fix hold time violations
Use compile -only_design_rule
DC only adds buffers or resizes cells
DC fixes only design rule and hold time violations
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary: Example Script
12-29
read_db read_db Top_meetsSetup.db Top_meetsSetup.db source source TimingConstraints_max.tcl TimingConstraints_max.tcl set_operating_conditions set_operating_conditions -max -max WORST WORST -min -min BEST BEST set set ALL_IN_EX_CLOCK ALL_IN_EX_CLOCK [remove_from_collection [remove_from_collection \\ [all_inputs] [all_inputs] [get_ports [get_ports Clk]] Clk]] set_input_delay set_input_delay -min -min 0.2 0.2 -clock -clock Clk Clk $ALL_IN_EX_CLOCK $ALL_IN_EX_CLOCK set_output_delay set_output_delay -min -min -0.1 -0.1 -clock -clock Clk Clk [all_outputs] [all_outputs] set_clock_uncertainty set_clock_uncertainty -hold -hold 0.5 0.5 [get_clocks [get_clocks Clk] Clk] report_timing report_timing -delay -delay min min ## Fix Fix min min timing timing violations violations set_fix_hold set_fix_hold [all_clocks] [all_clocks] compile compile -only_design_rule -only_design_rule redirect redirect top.rpt top.rpt {report_constraint {report_constraint -all_violators} -all_violators} Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 12: Introduction
12-30
45 min LAB
Practice Optimization Techniques source
source
calculation.v calculation.vhd
converter.v converter.vhd
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 3 DAY 3
Unit
13-1 Topic
10
Timing Revisited
11
Optimization
12
Compile Strategies
13
Compiling a Hierarchical Design
14
DC Tcl - Procedures
Lab
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
13-2
After completing this unit, you should be able to:
List two methods of resolving multiple instances
List one advantage and one disadvantage of using each method
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Compiling a Hierarchical Design
13-3
Compiling a Hierarchical DesignUnder The Hood
Resolving Multiple Instances
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Compiling a Hierarchy
13-4
D_design U1
U2 Ades
Bdes
Y= A+B
Y= A+B
U3 Cdes Y= A+B
Designs in the hierarchy are mapped to gates in two phases… Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
First Phase of Compile
13-5
The first phase of compile maps all blocks to gates without regard to constraints. D_design
D_design
U1 Ades
U2 Bdes
U1 Ades
U2 Bdes
Y=A+B U3 Cdes Y=A+B
U3 Cdes Y=A+B
D_design U1 Ades
U2 Bdes
U3 Cdes
Hierarchy is Preserved During a Compile Compiling a Hierarchical Design
Synopsys 31833-000-S16
Chip Synthesis Workshop
Second Phase of Compile
13-6
During the second phase, Design Compiler
optimizes logic to meet timing and area constraints
fixes violations caused by the surrounding blocks D_Design U1 Ades
U2 Bdes
U3 Cdes
What if a design is instantiated more than once?
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Resolving Multiple Instances
13-7
Compiling a Hierarchical DesignUnder the Hood
Resolving Multiple Instances
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Designs Instantiated More Than Once
13-8
In this example, Ades is used in two different locations Only one copy of the Ades exists in DC memory D_design U1
U2
Ades
Bdes
Y=A+B
Y=A+B
U3
Ades Y=A+B Ades
Bdes
Y=A+B
Y=A+B Design Compiler Memory
Which environmental attributes and constraints should DC use for Ades during compile? Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
check_design
13-9
dc_shell-t> dc_shell-t> check_design check_design
Returns warnings if your current design:
has multiple instantiations
has unconnected pins
compile terminates if multiple instantiations are not resolved!
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Methods to Resolve Multiple Instances
13-10
1.uniquify 2.compile + dont_touch D_design U1
U2 Ades
Bdes
Y=A+B
Y=A+B U3 Ades Y=A+B Bdes
Ades
Y=A+B
Y=A+B Design Compiler Memory
You must resolve multiple instances using one of these methods! Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Method #1: uniquify
13-11
uniquify makes a copy of each multiply-instantiated design (one copy for each instance)
Each instance gets a unique design name DC can now map each instance to its own specific environment D_Design U1 Ades_0 Y=A+B
U2 Bdes Y=A+B Bdes
Ades_0 Y=A+B
U3 Ades_1
Y=A+B
Y=A+B Ades_1 Y=A+B Design Compiler Memory Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Method #1: uniquify (cont)
13-12
D_Design U2
U1 Ades_0
Bdes
Y=A+B
Y=A+B
U3 Ades_1 Y=A+B
current_design D_design source D_constraints.tcl uniquify compile
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Method 2: compile + dont_touch
13-13
1. Constrain and compile Ades 2. Place a dont_touch attribute on the compiled Ades 3. Compile D_design D_design U1
U2
Ades
Bdes
Y=A+B
Y=A+B
U3 Ades Y=A+B Bdes
Ades
Y=A+B
Y=A+B Design Compiler Memory dont_touch
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Method 2: compile + dont_touch
13-14
read_db read_db unmapped/A_des.db unmapped/A_des.db current_design current_design Ades Ades link link source source Aconstraints.tcl Aconstraints.tcl compile compile read_db read_db unmapped/D_design.db unmapped/D_design.db current_design current_design D_design D_design set_dont_touch set_dont_touch [get_designs [get_designs Ades] Ades] source source Dconstraints.tcl Dconstraints.tcl compile U1 compile
D_design U2
Ades
Bdes Y=A+B U3
Ades
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Using set_dont_touch U1 Ades
13-15 U2 Bdes
U3 Ades
D_design
set_dont_touch can be assigned to design objects
It prevents modification of that design object Caution: If placed on an unmapped design, the design will remain unmapped
To resolve the multiple instantiation, set_dont_touch on the design Ades
Prevents any further optimization of instances U1 and U3 Compiling a Hierarchical Design
Synopsys 31833-000-S16
Chip Synthesis Workshop
uniquify vs. compile + dont_touch D_design
D_design U1
U2
Ades
13-16
Bdes
U3
U1
U2
Ades
Bdes
U3
Ades
Ades
uniquify
dont_touch
_________
__________
Which could take more time to compile? _________
__________
Which would offer you better results?
__________
Which solution would be easier to implement?
_________
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary current_design D_design source Dconstraints.tcl uniquify
13-17 Method #1
compile current_design Ades source Aconstraints.tcl compile current_design D_design set_dont_touch [get_designs Ades] source Dconstraints.tcl compile
Method #2
Use uniquify unless you are concerned about:
compile run times (large blocks or tightly constrained blocks)
memory limitations (large blocks or many instances)
laying out the block only once Compiling a Hierarchical Design
Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 13: Introduction LAB
13-18
45 min
Compiling a Hierarchical Design unmapped STACK_TOP.db
uniquify
dont_touch
mapped
mapped
STACK_TOP_ UNIQUIFY.db
STACK_TOP_ DONT_TOUCH.db
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 3 DAY 3
Unit
14-1
Topic
10
Timing Revisited
11
Optimization
12
Compile Strategies
13
Compiling a Hierarchical Design
14
DC Tcl - Procedures
Lab
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
14-2
After completing this unit, you should be able to:
Use Tcl commands to build loops and control flows
Write procedures for a DC-Tcl script for constraining a design
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Control Flow: Examples
14-3
if if [file [file exists exists My_Design.db] My_Design.db] {{ read_db read_db My_Design.db My_Design.db }} else else {{ echo echo Could Could not not read read My_Design.db My_Design.db }}
must be on same line as else!
set set FTYPE FTYPE [file [file type type My_Design.db] My_Design.db] switch switch $FTYPE $FTYPE {{ file {read_db file {read_db My_Design.db} My_Design.db} link {echo link {echo db db file file is is aa symbolic symbolic link} link} default default {echo {echo File File is is not not aa valid valid type type for for reading} reading} }}
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Looping Structures
14-4
## foreach foreach loop loop example example -- iterates iterates over over ## elements elements of of aa list: list: set set MYlist MYlist {Hello {Hello World} World} foreach foreach list_element list_element $MYlist $MYlist {{ echo echo $list_element $list_element }} ## while while loop loop example example set set idx idx 00 set set clk_per clk_per 10.0 10.0 ## Create Create divided divided clocks clocks on on ports ports CLK0 CLK0 -- CLK9 CLK9 while {$idx < 10} { while {$idx < 10} { create_clock create_clock -period -period $clk_per $clk_per [get_ports [get_ports CLK$idx] CLK$idx] incr incr idx idx set set clk_per clk_per [expr [expr (2 (2 ** $clk_per)] $clk_per)] }} Results shown in the Notes section Synopsys 31833-000-S16
DC Tcl - Procedures Chip Synthesis Workshop
Iterating over a Collection: Example
14-5
read_db read_db mapped/PRGRM_CNT_TOP.db mapped/PRGRM_CNT_TOP.db set set CellColl CellColl [get_cells [get_cells *] *] set set Count Count 11 ## Print Print aa list list of of all all cells cells in in the the Design Design foreach_in_collection foreach_in_collection SingleCell SingleCell $CellColl $CellColl {{ set set CellName CellName [get_object_name [get_object_name $SingleCell] $SingleCell] echo echo Cell Cell $Count $Count is is $CellName $CellName incr incr Count Count }} Results shown in the Notes section
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Tcl Procedures
Tcl allows the user to write their own “built-in” commands
14-6
Commands are written using a Tcl procedure
Powerful capabilities of procedures:
Allow you to define your own commands
Allow any number of arguments
user can define default values
Can have variable number of arguments
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Tcl Procedure Syntax myproc.tcl
14-7 necessary whitespace same line
proc proc CALC_PERIOD CALC_PERIOD {Clock_Freq} {Clock_Freq} {{ ## Convert Convert clock clock frequency frequency (Mhz) (Mhz) to to period period (ns) (ns) return return [expr [expr (( (1.0 (1.0 // $Clock_Freq) $Clock_Freq) ** 1000)] 1000)] }} dc_shell-t> dc_shell-t> source source myproc.tcl myproc.tcl dc_shell-t> dc_shell-t> CALC_PERIOD CALC_PERIOD 125.0 125.0 8.0 8.0 dc_shell-t> dc_shell-t> create_clock create_clock \\ -period -period [CALC_PERIOD [CALC_PERIOD 125.0] 125.0] \\ [get_ports [get_ports Clk] Clk] DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Scope of Variables
14-8
Variables created in a procedure only live for the duration of the procedure, (local scope)
Any variable defined outside any procedure is a global variable
Global variables are not visible to a procedure unless the global scope keyword is used when defining the variables in the procedure dc_shell-t> dc_shell-t> proc proc SP SP {} {} {{ global global search_path search_path set set search_path search_path “$search_path “$search_path ./scripts” ./scripts” }} dc_shell-t> dc_shell-t> SP SP dc_shell-t> dc_shell-t> echo echo $search_path $search_path {... {... slow_core.db slow_core.db ./scripts} ./scripts} DC Tcl - Procedures
Synopsys 31833-000-S16
Chip Synthesis Workshop
Procedure Information
14-9
Display the procedures in memory dc_shell-t> dc_shell-t> info info procs procs .. .. .. CALC_PERIOD CALC_PERIOD dc_shell-t> dc_shell-t>
Display the contents of a procedure dc_shell-t> dc_shell-t> info info body body CALC_PERIOD CALC_PERIOD ## Convert Convert clock clock frequency frequency (Mhz) (Mhz) to to period period (ns) (ns) return return [expr [expr (( (1.0 (1.0 // $Clock_Freq) $Clock_Freq) ** 1000)] 1000)] dc_shell-t> dc_shell-t>
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Tcl Procedure: Example
14-10 procs.tcl
proc TimeBudget
{clock_freq time_budget}
{
# Constrain a design for timing, using a time budget # clock_freq # time_budget # #
clock frequency in Mhz percentage of clock period allowed for delay of input/output logic in design being constrained
# calculate intermediate variables set CLK_PER [expr ((1/$clock_freq) * 1000)] set MY_IO_CONSTRAINT [expr ($CLK_PER*($time_budget/100.0)) ] set IO_DELAY [expr ($CLK_PER - $MY_IO_CONSTRAINT)] set all_except_clk [remove_from_collection \ [all_inputs] [get_ports Clk*] ] # constrain the design for timing DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Tcl Procedure: Example (cont)
14-11
# constrain the design for timing # create clock on clock port create_clock -period $CLK_PER -name MY_CLOCK [get_ports Clk*]
\
# constrain the inputs set_input_delay $IO_DELAY -max -clock MY_CLOCK \ $all_except_Clk # constrain the outputs set_output_delay $IO_DELAY -max -clock MY_CLOCK [all_outputs] };
\
# end of TimeBudget
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Tcl Procedure: Example (cont)
14-12
source procs.tcl read_db PRGRM_CNT_TOP.db current_design PRGRM_CNT_TOP # constrain design for Timing # using a clock period of 100 Mhz # and 40% of the clock period for IO timing TimeBudget 100.0 40.0 # constrain design for environmental attributes
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 14: Introduction LAB
14-13
30 min
Create two generic Tcl procedures unmapped PRGRM_CNT_TOP.db
myprocs.tcl proc TimeBudget proc LoadBudget
runit.tcl read_db ... TimeBudget LoadBudget compile report_constraint write...
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Check for errors
14-14
check_error -verbose dc_shell-t> dc_shell-t> check_error check_error -reset -reset dc_shell-t> dc_shell-t> source source my_script.tcl my_script.tcl dc_shell-t> dc_shell-t> check_error check_error -v -v 00 dc_shell-t> dc_shell-t>
check_error -reset dc_shell-t> dc_shell-t> check_error check_error -reset -reset dc_shell-t> dc_shell-t> source source my_script.tcl my_script.tcl dc_shell-t> dc_shell-t> check_error check_error -v -v {CMD-010} {CMD-010} dc_shell-t> dc_shell-t> error_info error_info
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 4 DAY 4
Unit
15-1 Topic
15
Compiling a Large Design
16
Design Exploration
17
Synthesizing for Test
18
Conclusion
Lab
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
15-2
After completing this unit, you should be able to:
Execute a top-down compile
Execute a bottom-up compile
Determine a second-pass compile strategy
Execute the characterize command
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Techniques for Compiling a Hierarchical Design 15-3
Techniques for Compiling a Hierarchical Design
Techniques for the Second-Pass Compile
characterize
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Hierarchical Compile Techniques: Types 15-4
There are two strategies for compiling a large hierarchical design:
Top-down
Bottom-up
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Top-Down Compile Methodology 1. 2. 3. 4. 5. 6.
Read in the entire design Resolve multiple instances Apply top-level constraints Compile Assess results Save design
15-5
DATA_PATH
INSTRN_LAT
PRGRM_CNT_TOP
STACK_TOP
ALU
REG_FILE
RISC_CORE top-down.tcl analyze -format vhdl {alu.vhd reg_file.vhd ... risc_core.vhd } elaborate RISC_CORE uniquify source scripts/top_level.tcl compile report_constraint -all write -format db -hierarchy -output mapped/RISC.db quit Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Advantages of Top-Down
15-6
"push-button" approach Intermodule dependencies are taken care of automatically Fewer man-hours spent “driving the tool”
Most productive approach when practical
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Simple Compile Mode
15-7
For designs without aggressive timing constraints • Run time can be reduced • Multiple instantiations are mapped once during compile • At the end of optimization, you get an automatically uniquified netlist analyze -format vhdl {alu.vhd... risc_core.vhd} elaborate RISC_CORE source scripts/top_level.tcl /* Do NOT execute uniquify */ set_simple_compile_mode true compile set_simple_compile_mode false
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Hierarchical Compile Techniques
15-8
There are two strategies for compiling a large hierarchical design:
Top-down
Bottom-up
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Bottom-Up Compile Methodology
15-9
1. Constrain and compile subblocks independently RISC_CORE
2. Make sure all subblocks meet their initial constraints 3. Read in the entire compiled design and apply top-level constraints
ALU
PRGRM_CNT_TOP
. . . REG_FILE
4. Check constraint report: if your design passes, you’re are done!
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Bottom-Up Compile Methodology
15-10
Compile each subblock to meet their respective budget
analyze analyze -format -format vhdl vhdl {PRGRM_CNT.vhd {PRGRM_CNT.vhd ... ... PRGRM_CNT_TOP.vhd} PRGRM_CNT_TOP.vhd} elaborate elaborate PRGRM_CNT_TOP PRGRM_CNT_TOP source source constraints.tcl constraints.tcl compile compile report_constraint report_constraint -all -all >> reports/PRGRM_CNT_TOP.rpt reports/PRGRM_CNT_TOP.rpt /* /* MAKE MAKE SURE SURE timing timing has has been been met! met! If If not, not, recode recode or or recompile recompile */ */ write write -format -format db db -hier -hier -output -output mapped/PRGRM_CNT_TOP.db mapped/PRGRM_CNT_TOP.db
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Bottom-Up Compile Methodology (cont) 15-11 Perform top-level integration and constraint analysis read_vhdl read_vhdl source/RISC_CORE.vhd source/RISC_CORE.vhd /* /* Bring Bring in in compiled compiled .db .db files files */ */ link link /* /* SYSTEM-LEVEL SYSTEM-LEVEL Constraints Constraints */ */ source source Top_level.tcl Top_level.tcl /* /* Check Check for for timing timing violations violations */ */ report_constraint report_constraint -all -all >> reports/RISC_CORE.rpt reports/RISC_CORE.rpt write write -format -format db db -hier -hier -output -output mapped/RISC_CORE.db mapped/RISC_CORE.db
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Pros & Cons of Bottom-Up Compile
15-12
Advantages:
Large designs are compiled with the “divide and conquer” approach Not limited by available memory
Disadvantages:
May require iterations until block-to-block interfaces are stable
Requires careful revision control
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary
15-13
Use top-down for “smaller” designs An overnight compile is considered a reasonable compile run time
Use bottom-up for all other designs Make time and load budgets as accurate and conservative as possible
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Techniques for the Second-Pass Compile 15-14
Techniques for Compiling a Hierarchical Design
Techniques for the Second-Pass Compile
characterize
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Problems After the First-Pass Compile
15-15
What if there were still timing violations after the first-pass top-down compile? What if there were timing violations during top-level integration after the bottom-up compile? RISC_CORE
ALU
CONTROL
DATA_PATH
PRGRM_CNT_TOP
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Use report_constraint -all dc_shell>
15-16
report_constraint -all
*************************** Report : constraint -all_violators Design : RISC_CORE Version: 1999.05 Date : Fri Nov 12 11:57:30 1999 ***************************
The violationis roughly 15% of the timing constraints.
max_delay/setup ('Clk' group) Required Actual Endpoint Path Delay Path Delay Slack ---------------------------------------------------------------------I_ALU/Zro_Flag_reg/D0 9.34 10.78 r -1.44 (VIOLATED) I_ALU/Neg_Flag_reg/D0 9.31 10.39 f -1.09 (VIOLATED) I_ALU/Lachd_Result_reg[15]/D0 9.31 10.31 f -1.00 (VIOLATED) OUT_VALID 1.20 2.16 r -0.96 (VIOLATED) I_ALU/Lachd_Result_reg[14]/D0 9.31 9.89 f -0.59 (VIOLATED)
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Use report_timing
15-17
Point Incr Path -------------------------------------------------------------------------clock Clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 I_DATA_PATH/Oprnd_B_reg[3]/CLK (fdmf1a2) 0.00 0.00 r I_DATA_PATH/Oprnd_B_reg[3]/Q (fdmf1a2) 0.85 0.85 f I_DATA_PATH/Oprnd_B[3] (DATA_PATH) 0.00 0.85 f I_ALU/Oprnd_B[3] (ALU) 0.00 0.85 f I_ALU/add_72/plus/A[3] (ALU_DW01_add_16_1) 0.00 0.85 f I_ALU/add_72/plus/U124/Y (inv1a0) 0.34 1.19 r I_ALU/add_72/plus/U79/Y (inv1a2) 0.32 1.51 f I_ALU/add_72/plus/U180/Y (nor2a2) 0.20 1.71 r
• • •
I_ALU/U564/Y (ao3e1) I_ALU/U509/Y (mx2d2) I_ALU/Lachd_Result_reg[14]/D0 (fdm1a1)
0.60 0.28 0.00
data arrival time
9.61 r 9.89 f 9.89 f 9.89
All of the combinational logic causing the violation is fully contained in ALU.
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Next Steps
15-18
A more aggressive second-pass top-down compile
compile -incremental -map_effort high
Compile only top-level violations
Check the partitions
Build a new design budget for the design ALU
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Compile only Top-Level Violations
15-19
What if after bottom-up compile we have timing violations at the top-level?
compile -top
Fixes timing violations on top-level paths only
Less memory and CPU intensive than a top-level compile -incremental
A good compile strategy to fix integration problems due to small discrepancies in design budgets Compiling a Large Design
Synopsys 31833-000-S16
Chip Synthesis Workshop
Check Your Partitions
15-20
How would you compile this design? RISC_CORE CONTROL
PRGRM_CNT ALU
40 k gates
20 k gates
DATA_PATH
Glue 5k 100 k gates
data_bus 32 30 k gates
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Top-Level Partitions
15-21
Compile top-down on as large a design as is reasonable for compile run times and floorplan issues Motivation: Often produces better results in less time than a design budgeting/bottom-up strategy
Partition at register outputs for timing-critical paths and major hierarchical blocks
Generating design budgets is greatly simplified
Design Compiler will not optimize logic across hierarchical boundaries
To repartition change your HDL source or use group/ungroup. Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Build a New Design Budget
15-22
Design Budgeting!
“Tighten” the budget for time, load, and drive budgets for each block to meet
Compile each block to meet that budget
Integration at top level should cause no problems if: All blocks compiled and met their budget Budget was accurate and sufficiently constrained the design
How can we automate the process of generating new design budgets?
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
characterize
15-23
Techniques for Compiling a Hierarchical Design
Techniques for the Second-Pass Compile
characterize
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
The characterize Command
15-24
characterize calculates the actual attributes and constraints imposed on a design by its surroundings characterize then places those constraints on the design TOP U1 A
U2
U3 C
Output Load and Delay Constraints
B
Input Delay Times and Drive on Inputs
current_design TOP characterize -constraints find(cell, U2) current_design B compile -inc -map high Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Viewing the Results of characterize
15-25
write_script outputs a script containing all of the constraints that have been set on the current_design /****************************************************** Created by write_script() on Mon Oct 12 18:44:54 1998 ******************************************************/ /* Set the current_design */ current_design ALU create_clock -name "my_clock" -period 10 -waveform {0 5} find(port,"Clk") set_dont_touch_network find(clock, "my_clock") set_input_delay 2.2439 -max -rise -clock "my_clock" find(port,"Latch_Flags") set_input_delay 2.28963 -max -fall -clock "my_clock" find(port,"Latch_Flags") set_output_delay 5.77132 -max -rise -clock "my_clock" find(port,"Carry_Flag") set_output_delay 5.80142 -max -fall -clock "my_clock" find(port,"Carry_Flag") set_load -pin_load 0.343 find(port, "Reset") set_wire_load "tc6a120m2" -library "cba_core" -port_list find(port, "Reset") set_driving_cell -lib_cell buf1a4 -pin "Y" -no_design_rule find(port,"Reset") set_max_capacitance 2.4 find(port, "Reset") Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Recompile HDL Source after characterize 15-26
Create a script to characterize and recompile design B TOP U1 A
current_design TOP characterize -cons U2 current_design B write_script > B_w.tcl remove_design -hier B
U3 U2 B
C
read -f verilog B.v current_design B source B_w.tcl compile write -hier -o B.db current_design TOP report_constraints
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
characterize Limitations
15-27
characterize can only be used when all blocks are mapped to gates
characterize can NOT be used to derive first-pass compile design budgets
characterize can only be done one block at a time Once a block has been characterized and recompiled, there are “new” cells driving/loading other subblocks
characterize “pushes away” any margin that may exist on block-block interface
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary
15-28
Use the Top-Down methodology if feasible
The second-pass compile strategy depends on the kind of violations in the design
characterize allows to generate detailed blocklevel constraints from the interblock requirement
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 15: Introduction LAB
60 min
Resolve Timing Violations
15-29
RISC_CORE
ALU
CONTROL
DATA_PATH
PRGRM_CNT_TOP
This exercise is a review of the last few labs, so spend some time thinking about the various compile steps. Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Appendix
15-30
Design Budgeter
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Budgeter
15-31 Allocate Budgets U1 U4 U5
Compile U1
Compile U4
Compile U5
Reassemble Modules Verify Timing
Designs Best Suited for Budgeting Hierarchical Designs Large Designs Designs with subblocks that are not fully registered Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Budgeter Methodology Build initial constraints
RTL
bottom-up compile
compile compile compile
constraints
15-32
GTECH database
budgeter Pass Zero
compile compile compile
refined constraints
budgeter Pass One
remove false_path
compile -inc
Pass Two
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Build the Initial Timing Constraints
65
15-33
35
virtual clock
create_clock -period n -name vclock; create_clock -period n -name reg2reg clk_ports; set_input_delay -clock vclock 0.35*n \ $all_inports_except_clockports; set_output_delay -clock vclock 0.65*n [all_outputs]; set_false_path -from reg2reg -to reg2reg; Do not use the -max or -min options ! Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Example U1
15-34 U3
U4
Timing Model
U5
U2 dont_touch
allocate_budget -write_context {U1 U4 U5} Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Command Flow
15-35
Pass Zero budget_shell> read_db mapped/TOP.db budget_shell> allocate_budgets -check_only budget_shell> allocate_budgets -write_context {U1 U4 U5} budget_shell> sh ls U1.ptsh U4.ptsh U5.ptsh
Pass One budget_shell> budget_shell> budget_shell> budget_shell> budget_shell>
critical design read_db unmapped/U1.db source U1.ptsh compile allocate_budgets -write_context U1 write -f db -hier -out mapped/U1.db
Pass Two budget_shell> budget_shell> budget_shell> budget_shell>
current_design U1 source U1.ptsh compile -inc write -f db -hier -out mapped/U1.db Compiling a Large Design
Synopsys 31833-000-S16
Chip Synthesis Workshop
How to Access Design Budgeter?
15-36
PrimeTime (Tcl) pt_shell> allocate_budgets
Design Budget Shell (Tcl) budget_shell> allocate_budgets
Note: allocate_budget is not supported in dc_shell-t; use the budget_shell instead.
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 4 DAY 4
Unit
16-1
Topic
15
Compiling a Large Design
16
Design Exploration
17
Synthesizing for Test
18
Conclusion
Lab
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
16-2
After completing this unit, you should be able to:
Perform a Design Exploration compile
Fine-tune the Design Constraints
Build user-defined Path Groups
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Classic Six-Month Design Flow
Plan: Three Months for Coding and Simulating
16-3 HDL Coding
Functional Simulation Functionally Correct?
No
Code Freeze Yes
Synthesis Plan: Three Months for Implementing the Design
Test Insertion Physical Design
How Long Has it Taken You to do it This Way?
Gate-Level Analysis & Signoff Design Exploration
Synopsys 31833-000-S16
Chip Synthesis Workshop
Traditional Reactive Flow
16-4
Traditional Flows address problems reactively, after they occur
Functional Simulation
HDL Coding Functionally Correct?
Bad budgets “painted you into a corner”
No
Yes
Synthesis
Failed
Test Insertion Failed Physical Design
Failed
Final Analysis & Signoff Failed
Couldn’t meet timing (inefficient RTL code) Fault Coverage <10% (uncontrollable reset) Unroutable (too congested) Couldn’t meet timing after place and route Design Exploration
Synopsys 31833-000-S16
Chip Synthesis Workshop
Identify and Resolve Problems Early!
16-5
Degrees of Freedom Library, Algorithm, Architecture System-Level Constraints
Cost $
Code, Partitions, BOA, HLO
$$$$
DC switches, BRT
$$$$$$
LBO/FPM
$$$$$$$$$$$$ Layout
Proactive Design Exploration • Discover and resolve performance issues early in the flow • Fix problems at the source code level whenever possible • Plan for the speed and area impact of scan insertion • Anticipate the problems of slow top-level interconnects Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
The Proactive Design Methodology Logical Design
16-6
Physical Design Check Tool Flow
Code RTL
Validate Design
Early Floorplan / P&R Functional Simulation Check WLM’s Design Exploration
Create Custom WLM
Code Freeze?
Implement Design
Compile Major Subblocks
Floorplan
Integrate Chip
Create Custom WLM
Reoptimize Design
Place & Route
Final Analysis & Signoff
ECO P&R Design Exploration
Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Exploration
16-7
A quick, exploratory synthesis run to gauge design performance against goals
When is Design Exploration performed?
In parallel with functional simulation, not at the end!!! Any time code changes enough to impact performance On small blocks of code where the problem is self-contained and easily fixable Logical Design Code RTL Functional Simulation Design Exploration
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Exploration Goals
Use the fastest, default-effort compiles possible to:
Verify that code is synthesizable
Verify that code is close to meeting constraints (10-15%)
Verify that constraints are realistic and sufficient
Identify and declare timing exceptions
Identify partitioning problems
Identify testability problems
Account for the impact of inserting scan cells
Ensure that your wire load models are “reasonable”
16-8
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Why 10% and Not 0%?
16-9
You are simply validating that you are close to meeting timing with the code you have, so you don’t have to recode later.
Design Compiler was not meant to fix bad code Garbage In ==> Garbage Out
You can reasonably expect advanced compile strategies to fix violations that are 10-15% over timing
More efficient HDL code (better algorithms and architectures) is often required to fix larger violations
You are performing exploration on code that may not be stable yet.
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
What Is the Design Exploration Flow? New
16-10
Constrain
HDL code Recode HDL
Test-ready compile
Repartition Design FIX
Analyze timing, partitioning, & test rule violations GOOD Initial Floorplan, Create custom wire load model
FIX
Design Exploration
Continue
Analyze timing violations GOOD
Simulation
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Typical Constraint Script (Basic)
16-11
my_block_constraints.tcl # Define clock create_clock -period 5 [get_ports CLK] set_dont_touch_network [all_clocks] # Delay and drive strength on input ports set all_inputs_but_clk [remove_from_collection [all_inputs] CLK] set_input_delay $clk_to_q -clock CLK $all_inputs_but_clk set_driving_cell -lib_cell $my_register $all_inputs_but_clk # Delay and load on output ports set_output_delay [expr 5 - $clk_to_q] -clock CLK [all_outputs] set_load [expr $pessimistic_load * 3] [all_outputs] A # Describe environment B set_operating_conditions WCCOM CLK set_wire_load_model -name 100k_WLM -mode top
Y
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Detailed Modeling of External Loads
16-12
set pessimistic_load [expr load_of(TECH_LIB/inv1a1/A)] # Account for Pin Load and Wire Load on Outputs set_load [expr $pessimistic_load * 3] [all_outputs]
# pins
set_port_fanout_number 3 [all_outputs]
# wires
# Account for Pin Load and Wire Load on Inputs too! set_load $pessimistic_load $all_inputs_but_clk
# pins
set_port_fanout_number 1 [all_inputs]
# wires
MY_BLOCK
A
A
inv1a1
A A
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Special WLM for Ports (Global Nets)
16-13
# Describe different WLMs for internal nets vs. global nets set_wire_load_mode top 100k_WLM set_wire_load_model -name GLOBAL_NET_WLM [get_ports *] TOP BLOCK_1
BLOCK_2
BLOCK_3
BLOCK_4
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Rule Constraints
DC respects design rules as highest priority of all
Certain design rules may exist on library cell pins
16-14
max_capacitance max_transition max_fanout
You can apply design rules to entire designs to:
Anticipate the interface environment your block will see
Prevent the design from operating cells close to their limits, where performance degrades rapidly
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
set_max_capacitance
16-15
my_dr_cons.tcl # Find the max capacitive load allowed on your expected driver set DRIVE_PIN TECH_LIB/inv1a27/Y set MAX_CAP [get_attribute
$DRIVE_PIN
max_capacitance]
3.600 # Add some margin so DC won’t fully load the driver set CONSERVATIVE_MAX_CAP [expr $MAX_CAP / 2.0] 1.800 set_load 1.2 [get_ports IN1] set_max_capacitance $CONSERVATIVE_MAX_CAP [get_ports IN1] # max internal load DC can put on IN1 is [1.8 - 1.2 = 0.6pf]
inv1a27 Y A
IN1
1.2pf Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
set_max_transition
16-16 my_dr_cons.tcl
# Find the max transition allowed on your expected driver set DRIVE_PIN TECH_LIB/inv1a27/Y set MAX_TRANS [get_attribute
$DRIVE_PIN
max_transition]
0.400 # Add some margin so DC won’t fully load the driver set CONSERVATIVE_MAX_TRANS [expr $MAX_TRANS / 2.0] 0.200 set_max_transition $CONSERVATIVE_MAX_TRANS [get_ports IN1] # DC accounts for the driving_cell type and external load on it, # limits internal loads placed on IN1 to meet your design rule
inv1a27 Y A
IN1
1.2pf Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
set_max_fanout
16-17
set_max_fanout 6 [get_ports IN1]
A IN1
Y inv1a1 inv1a1 inv1a1 inv1a27 inv1a27
Is the max_fanout design rule on port IN1 met? How many cells might port IN1 have to drive? Does it matter what the cell type is?
get_attribute TECH_LIB/inv1a1/A fanout_load 0.25 # DC might load port IN1 with 6 / 0.25 = 24 inv1a1 cells! get_attribute TECH_LIB/inv1a27/A fanout_load 3.00 # DC can only load port IN1 with 6 / 3.00 = 2 inv1a27 cells! Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Fanout Loads
16-18
•set_max_fanout uses fanout_load, NOT absolute fanout number! • Sum of fanout_load on a port must be less than max_fanout design rule constraint A = 0.25 = 0.25
IN1
= 0.25 = 3.00 = 3.00
Y inv1a1 inv1a1 inv1a1 inv1a27 inv1a27
Some cell/pins have no fanout_load attribute
DC then checks library for default_fanout_load attribute
If neither exists, DC assumes a value of zero This may allow infinite fanout on an input port! Design Exploration
Synopsys 31833-000-S16
Chip Synthesis Workshop
Controlling Port Fanout
16-19
How can I force port fanout to only one real load? # Easiest case set_max_fanout 1 [all_inputs] # Trickier case set SMALL_CELL TECH_LIB/buf1a1/A set SMALL_FOL get_attribute $SMALL_CELL 0.5000 set_max_fanout $SMALL_FOL [all_inputs]
Does my library have the necessary attribute? get_attribute 0.0000 # Uh-oh!
TECH_LIB
default_fanout_load
If not, how can I set it? set_attribute TECH_LIB -type float 1.0000
Synopsys 31833-000-S16
fanout_load
default_fanout_load
1.0 \
Design Exploration Chip Synthesis Workshop
Typical Compile Script (Basic)
16-20
compile_flow.tcl # Read in source files and build initial Gtech design if (You_are_using_VHDL) { analyze -format vhdl {file1.vhd file2.vhd file3.vhd TOP.vhd} elaborate TOP } else { read_verilog {file1.v file2.v file3.v TOP.v} } # Constrain the Gtech design source my_block_constraints.tcl source my_dr_cons.tcl # Optimize and map the design compile # Save the design and exit write -format db -hierarchy -output my_block.db quit Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Fastest Runtimes for Design Exploration
16-21
current_design MY_BLOCK reset_design source time_and_load_budget_constraints.tcl remove_attribute MY_BLOCK “max_area” if (You_Have_DesignWareFoundation_and_Plan_To_Use_It) { set synthetic_library dw_foundation.sldb append link_library “ $synthetic_library” } set_simple_compile_mode true set compile_dw_simple_mode true set_scan_configuration -style multiplexed_flip_flop
compile
-area_effort none
-scan
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Additional Runtime Speed-ups
16-22
New in v2000.05: “Presto” RTL code reader
Average 6x faster Verilog elaboration than in v1999.10 Presto’s VHDL support due in v2000.10 release Average 35% less memory usage Supports additional Verilog language constructs
dc_shell-t> set hdlin_enable_presto true
New in v2000.05: New Verilog netlist reader
Average 3x faster than v1999.10 Average 3x memory reduction compared to v1999.10
dc_shell-t> set enable_verilog_netlist_reader dc_shell-t> read_verilog -netlist mapped.v
true
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Scenarios: Exploring Subdesigns
16-23
What Compile Technique Should I Use During Design Exploration? What Constraints Should I Consider During Design Exploration?
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Exploration on SUBDESIGN_A
SUBDESIGN_A’s RTL code just became available
16-24
It is a very critical block, and you want to evaluate its performance without waiting for the other blocks
SUBDESIGN_A is a small block
Its parent block will eventually be compiled top-down Its inputs and outputs might not be registered SUBDESIGN_A (40 K gates) PRGRM_CNT
DATA_PATH OUT_BUS [31:0]
IN_BUS [31:0]
10K
20K CONTROL ZERO_FLAG
10K CLK
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
How To Constrain SUBDESIGN_A
MAJOR_BLOCK_1 will be compiled top-down later...
16-25
…after code for A, B, C, D becomes available and stable Inputs and outputs of subdesigns might not be registered
How do we constrain SUBDESIGN_A for a standalone compile at this level? MAJOR_BLOCK_1 (140 K gates)
IN_BUS [31:0]
SUBDESIGN_A (40K gates)
SUBDESIGN_B (30K gates)
OUT_BUS [31:0]
D Q SUBDESIGN_C (50K gates)
SUBDESIGN_D (20K gates)
CLK
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
How To Constrain SUBDESIGN_A (cont)
16-26
How do we constrain SUBDESIGN_A for a standalone compile at this level?
Use what you know
Clock period Operating Conditions
Estimate what you don’t know
Input drives, Output loads, Wire load model, Time Budget
create_clock -period 10 [get_ports CLK] set_dont_touch_network [get_clocks CLK] set_operating_conditions SLOW_COMMERCIAL set_wire_load_model -name 140Kgates -mode top set_driving_cell -lib_cell NAND2 -pin Y $all_in_ex_clk set_load [expr [load_of TECH_LIB/NAND2/A] * 4] $all_in_ex_clk set_load [expr [load_of TECH_LIB/NAND2/A] * 6] [all_outputs]
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
How To Constrain SUBDESIGN_A: I/O
16-27
What about I/O timing?
Are your inputs driven by blocks with registered-outputs? Are your outputs registered? Do you have purely combinational paths in your design?
MAJOR_BLOCK_2 SUBDESIGN_A A
32
W
32
RECEIVING_BLOCK
DRIVING_BLOCK B
32
X
32
C
32
Y
32
D
32
Z
32
?
?
?
?
CLK Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
I/O Timing Constraint Options
16-28
# Assume every block has registered outputs, same 10ns clock
set_input_delay
-max
$clk_to_q
-clock CLK $all_in_ex_clk
set_output_delay -max [expr 10 - $clk_to_q] -clock CLK [all_outputs]
MY_DESIGN
DRIVING_BLK D Q FF0 QB
A
D Q FF1 QB
RECEIVING_BLK D Q FF2 QB
Z
D Q FF3 QB
CLK
# Assume every block has registered outputs, same 10ns clock
set_input_delay -max
[expr $CLK_PER * 0.1] -clock CLK $all_in_ex_clk
set_output_delay -max [expr $CLK_PER * 0.9] -clock CLK [all_outputs] Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
I/O Timing Constraint Options (cont)
16-29
# Assume blocks do not have registered outputs; split delay equally among both sides # This is the typical case when exploring smaller, lower-level blocks
set_input_delay
-max [expr $CLK_PER * 0.5] -clock CLK $all_in_but_clk
set_output_delay -max [expr $CLK_PER * 0.5] -clock CLK [all_outputs]
MY_DESIGN
DRIVING_BLK D Q FF0 QB
A
D Q FF1 QB
RECEIVING_BLK D Q FF2 QB
Z
D Q FF3 QB
CLK
How much “margin” is built into these constraints?
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Exploring Combinational Paths set_input_delay
16-30
-max [expr $CLK_PER * 0.5] -clock CLK $all_in_ex_clk
set_output_delay -max [expr $CLK_PER * 0.5] -clock CLK [all_outputs] MY_DESIGN
A
D Q FF1 QB
D Q FF2 QB
Z
CLK B
COMBO
Y
How do these constraints affect the combinational path from B to Y? Do they affect optimization of MY_DESIGN? Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
User-Defined Path Groups
16-31
Custom path groups allow more control over optimization
Each path group is optimized independently Worst violator in one path group doesn’t prevent optimization in another
Path groups can be given different priorities
Register-to-Register Paths Input Paths
A
D Q FF1 QB
D Q FF2 QB
Z
Output Paths
CLK
B
COMBO
Combinational Paths Synopsys 31833-000-S16
Y
Design Exploration Chip Synthesis Workshop
Creating Custom Path Groups
16-32
DO IN A LAB! Use group_path to group paths of interest group_path -name INPUTS -from [all_inputs] group_path -name OUTPUTS -to [all_outputs] group_path -name COMBO -from [all_inputs] -to [all_outputs]
In which path group will register-to-register timing paths be? In which path group will combinational timing paths be? How does this affect a compile? How can you remove the user defined path groups?
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Two Path Group Options
16-33
# Avoid getting stuck on one path in the reg-reg group group_path -name INPUTS -from [all_inputs] group_path -name OUTPUTS -to [all_outputs] group_path -name COMBO -from [all_inputs] -to [all_outputs] group_path -name clk -critical_range 0.3
A
D Q FF1 QB
D Q FF2 QB
Z
CLK B
COMBO
Y
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Path Groups vs Critical Range
16-34
Path Group
Path Groups will allow path improvements in a given group which degrade another group’s worst violator, IF the overall cost function is improved
Adding a path group can INCREASE the worst violator in a design
Critical Range
Critical Range will not allow improvements to near-critical paths that worsen the worst violator in a path group
To optimize all critical endpoints in a design, giving each endpoint its own path group usually runs faster than using a very large critical_range, but runtime can be excessive for either case if many paths are involved
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
When Do I Exit Design Exploration?
16-35
Completion Criteria for all major subblocks Timing violations less than 10% of actual goals Good design partitioning No test rule violations Accurate wireload models Single-cycle timing exceptions identified Additional, user-defined criteria
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Review
16-36
Be Proactive! Anticipate Problems as early as possible.
Perform design exploration
Validate your tool flow
Floorplan early
Check accuracy of wire load models
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 4 DAY 4
Unit
17-1
Topic
15
Compiling a Large Design
16
Design Exploration
17
Synthesizing for Test
18
Conclusion
Lab
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
17-2
After completing this unit, you should be able to:
List at least two benefits of using the compile scan command
State the command that checks a design for testability violations
State the command that shows the estimated fault coverage of your circuit
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Chip Defects: They’re Not My Fault!
17-3
My chip was well designed and functionally correct. It simulated and synthesized just fine, but when the chip was manufactured, it didn’t work!
WHY?
.
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Manufacturing Defects
17-4 Electrical Effects
Physical Defects Silicon Defects Photolithography Defects Mask Contamination Process Variations Defective Oxide
Shorts (Bridging Faults) Opens Transistor Stuck On/Open Resistive Short/Open Changes in Threshold Voltage
Logical Effects Logic Stuck-at-0/1 Slower Transitions (Delay Fault) AND-bridging, OR-bridging
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Why Test for Manufacturing Defects?
The manufacturing test is created to detect manufacturing defects and reject those parts before shipment
Debug manufacturing process
Improve process yield
17-5
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
How Is Manufacturing Test Performed?
DUT
Outputs
Automatic Test Equipment (ATE) applies input stimulus to the Device Under Test (DUT) and measures the output response Inputs
17-6
If the ATE observes a response different from the expected response, the DUT fails the manufacturing test
The process of generating the input stimulus and corresponding output response is known as Automated Test Pattern Generation (ATPG) Synthesizing for Test
Synopsys 31833-000-S16
Chip Synthesis Workshop
The Stuck-At Fault Model
17-7
Output Stuck At Logic 1 (SA1)
Input Stuck At Logic 0 (SA0)
Stuck-At Fault (SAF): A logical model representing the effects of an underlying physical defect.
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Algorithm for Detecting a SAF
17-8
If this SA0 fault is present then U1/Y stays at logic 0 If not present, then U1/Y is driven to its normal value A SA0
B
U1
Z
C
D
We can exploit this “either/or behavior” to detect the fault. Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Controllability
17-9
The ability to set internal nodes to a specific value
1/0
0
U1
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Observability
17-10
The ability to propagate the fault effect from an internal node to a primary output port 0/1
1 1/0
0
Observable Discrepancy
U1
1/0
0
0
0 Enabling Input
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Fault Coverage
Fault coverage =
17-11
number of detectable faults total number of possible faults
High fault coverage correlates to high defect coverage
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Testing a Multistage, Pipelined Design
17-12
Can create a lot more complications for you Test for SA0 fault here 1
Need to observe results at the output of the design.
0 0 1
Need to set input pins to specific values so that nets within pipeline can be set to values which test for a fault Each fault tested requires a predictive means for both controlling the input and observing the results downstream from the fault. Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Scan Chains Help
17-13
Scan chain initializes nets within the design (adds controllability) Scan chain captures results from within the design (adds observability) Inserting a scan chain involves replacing all Flip-Flops with scannable Flip-Flops Test for SA0 fault here.
Scan_Ena Scan_In
Scan Flip-Flop
1 0 0 1
What effect will the mux and scan chain have on circuit timing? Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Inaccuracy Due to Scan Replacements 17-14 If you plan to include internal scan, you must account for the impact of scan registers on a design early in the design cycle Larger area than non-scan registers; optimistic wire load model selection Larger setup time requirement
Additional fanout and capacitive loading TI
TI
1
DI
0
1
DO
DI
0
TE CLK
CLK
Multiplexed Scan Register Chain Non-Scan Register Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Use One-Pass Scan Synthesis
17-15
Regular registers are replaced with scannable ones, but not chained
Include the scan style in the constraint script file
set_scan_configuration -style multiplexed_flip_flop
Perform one-pass test scan compile
compile -scan Scan Register Used During Initial Compile
Benefits
Accurate area, timing, and loading modeled up front Easier synthesis flow -- scan cell insertion performed in one compilation step
TI
1
TO DO
DI
0
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Result of Test-Ready Compile: Example 17-16 dc_shell> compile -scan Scan cells inserted during compile A
D TI “0”
Q
D
TE
E
D TI
B “0”
Q
TE
CLK
Loading effect of scan chain modeled Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
DFT Checking: Example
17-17
D
Q
dc_shell> check_test Warning: Clock/enable pin CP of cell u0 (FD1) has multiple sources (TEST-126) Information: A source of the violation is port IN2 (TEST-182) Information: A source of the violation is pin Q of cell u0 (TEST-180) Information: A source of the violation is port CLK (TEST-182) Information: Test design rule checking completed with 1 warning(s) and error(s)
0
If a warning or error is returned, it is up to the user to correct the circuit so that there are no scan design rule violations. Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Testability Violation: Example D
17-18
Q
What would happen in the circuit above, if, during test, a ‘1’ were shifted into the Flip-Flop?
A: We would never be able to “clock” the Flip-Flop! The Flip-Flop, therefore, cannot be allowed to be part of a scan chain. Logic in ‘N’ cannot be tested (controlled).
The above circuit:
Violates good “design for test” practices Reduces the “fault coverage” Synthesizing for Test
Synopsys 31833-000-S16
Chip Synthesis Workshop
Running ATPG
17-19
create_test_patterns activates the ATPG function of DC
Execute ATPG after compile -scan and check_test dc_shell> create_test_patterns -dft -sample 11 Warning: Violations occurred during test design rule checking. (TEST-124) Building test generation network
No. of detected faults No. of abandoned faults No. of tied faults No. of redundant faults No. of untested faults Total no. of faults Fault coverage No. of test patterns
Non-collapsed 1423 2 4 2 0 1431 99.86
Collapsed 1356 2 4 2 0 1364 99.85
174
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
What Is DFTC?
17-20
DFTC bundles together expert logic-synthesis capability plus all the design-for-test features you need to:
compile “scan-ready” logic blocks
check synthesized logic for scan compliance
insert scan chains, top-down or bottom-up
preview fault coverage on a scanned block
Design-for-Test Compiler (DFTC)
DFTC enables designers to do constraint-based scan synthesis!
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
DFTC Flow at a Glance
17-21
DFTC Methodology for a Typical Block: compile -scan
HDL
Scan-Ready Synthesis
Constraints: Scan style, speed, area
check_test insert_scan Pre-Scan DRC
Insert Scan
Technology Library: Gates, flip-flops, scan equivalents
check_test Post-Scan DRC
Run ATPG
Constraint-Based Scan Synthesis: Routing, balancing, gate-level optimization
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Test Tools Summary
17-22
DC-XP
Test Compiler
compile -scan
X
X
check_test
X
X
create_test_patterns -dft (coverage)
X
X
insert_scan
X
X
create_test_patterns (ATPG) write_test (for ATE and gate-level sim)
X X
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesizing for Test Summary
Test is a design methodology
17-23
It has its own testability design rules
Most problems associated with test can be anticipated and corrected in advance, during the initial compile of the HDL code
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 4 DAY 4
Unit
18-1
Topic
15
Compiling a Large Design
16
Design Exploration
17
Synthesizing for Test
18
Conclusion
Lab
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
18-2
After completing this unit, you should be able to:
List at least four steps to take before compiling a design
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Some Thoughts on Coding Poor Start Point
18-3
Better Start Point Best Start Point
Goal
Spend more time writing good HDL code so you spend less time optimizing the design
If you’ve written your code so that the critical path is reduced to a single gate, and the design still does not meet the timing, then it is not your code that’s wrong
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis Quality Depends on Algorithms! 18-4
Solution to a design problem is typically based on a particular algorithm
From that algorithm, you specify a hardware architecture to solve the problem
Your high-level design decisions provide the starting point for DC’s translation, optimization, and mapping
DC’s HLO techniques can NOT change the algorithm or architecture you choose to implement!
Single-cycle vs. Pipelined over several cycles Serial vs. parallel FIR vs. IIR, etc…
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Classic Algorithms, Architectures, & Tradeoffs 18-5
Frequency Analysis: DFT vs. FFT
Sorting Algorithms: Bubblesort vs. Quicksort
Sine wave generator: Difference Equation vs. Counter + Lookup Table
Finite State Machines: 1-hot encoding vs. Binary
Microprocessor Design: RISC vs. CISC
Like circuits, algorithms also involve tradeoffs between speed, area, memory, code size/complexity, etc...
Choose the algorithm, architecture, and implementation to match the performance goals of your design. Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Reflections on Synthesis
18-6
There is no “golden’ script” for synthesis
Physics dictates what will fit between two registers
The random setting of optimization switches and constraints to meet your speed goals is not a credible methodology
Most timing problems are not caused by wrong compile switches!
Compile switches are a vehicle to fix compile problems late in the design cycle
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Pre-Compile Checklist
18-7
Good Synthesizable HDL Code
Good Synthesis Partitioning Realistic Constraints & Attributes False Paths Identified Wireloads Reflect Physical Placement (discussed in Advanced CHIP)
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
What Do You Do First?
18-8
1. Satisfy the items on the checklist. Use what you have learned in this workshop. 2. If adding margin, do not overconstrain by more than 10%. 3. Always, always, always (always!) start with the default compile. compile <-scan>
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Compile Strategy
18-9
Start Analyze and Elaborate HDL Apply Constraints = Small Violations (10-25%)
compile
= Larger Violations
compile -map high
compile -map high -incremental
Good Yes Results ?
Done! Rewrite HDLCode
No Analyze Analyzeto to identify problem, identify problem, then then......
Specify critical_range
Characterize Block
Repartition Block
Modify Flatten & Structure Options
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Analysis to Diagnose the Problem 18-10 Spot the whales in the timing report: Where are they? What are they? And why? Point clock (input port clock) (rise edge) input external delay addr31 (in) u_proc/address31 (proc) u_proc/u_dcl/int_add[7] (dcl) u_proc/u_dcl/U159/Q (NAND3H) u_proc/u_dcl/U160/Q (NOR3F) u_proc/u_dcl/U186/Q (AND3F) u_proc/u_dcl/U86/Q (INVF) u_proc/u_dcl/U135/Q (NOR3B) u_proc/u_dcl/U136/Q (INVF) u_proc/u_dcl/U100/Q (NBF) u_proc/u_dcl/U95/Q (BF) u_proc/u_dcl/U96/Q (BF) u_proc/u_dcl/U94/Q (NBF) u_proc/u_dcl/U93/Q (NBF) u_proc/u_dcl/ctl_rs_N (dcl) u_proc/u_ctl/ctl_rs_N (ctl) u_proc/u_ctl/U126/Q (NOR3B) u_proc/u_ctl/U120/Q (NAND2B) u_proc/u_ctl/U99/Q (NBF) u_proc/u_ctl/U122/Q (OR2B) u_proc/u_ctl/read_int_N (ctl) u_proc/int_cs (proc) u_int/readN (int) u_int/U39/Q (NBF) u_int/U17/Q (INVB) u_int/U16/Q (AOI21F) u_int/U60/Q (AOI22B) u_int/U68/Q (INVB) u_int/int_flop_0/D (DFF) data arrival time
Incr 0.00 22.40 0.00 1.08 0.00 0.62 0.75 1.33 0.64 1.36 0.49 0.87 0.44 0.45 0.84 0.94 0.00 0.00 1.78 1.07 0.88 10.72 0.00 0.00 0.00 1.29 1.76 2.49 1.43 1.81 0.00
Path 0.00 22.40 22.40 23.48 23.48 24.10 24.85 26.18 26.82 28.17 28.67 29.54 29.98 30.43 31.27 32.21 32.21 32.21 33.98 35.06 35.94 46.67 46.67 46.67 46.67 47.95 49.71 52.20 53.63 55.44 55.44 55.44
f f f f r f f r f r r f r r r r r f r r r r r r r f r f r r
Rather late arrival for a 30 ns period! Six buffers back to back?!
11 ns delay for an OR gate is not good. Four hierarchical partitions.
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Look Back at the Past Several Days
18-11
Setup, Libraries, GUI, Coding for Synthesis (Day 1)
Describing the synthesis environment (Day 2)
Optimization and Compile Techniques (Day 3)
Design Exploration and DFT (Day 4)
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Need More Training?
VHDL Coding Styles for Synthesis
Verilog Coding Styles for Synthesis
Advanced Chip Synthesis Workshop
PrimeTime Workshops
Advanced Verilog & VHDL Workshops
And more...
18-12
1-800-793-3448 www.synopsys.com/services/education Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Advanced Chip Synthesis RTL
RTL .db
DC
Lib WLM
18-13
.v, .vhdl, .sdf, etc.
compile
Floorplanner .db
Iterate
.db DC
PrimeTime
CLWM
RC SDF PDEF
Ultra
create_wire_load
PrimeTime
Computed Data ForwardAnnotate Placement PDEF
.db
DC
Ultra
reoptimize_design
ECO Iterate Actual Data
Place&Route RC SDF PDEF
GDSII Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Coding Styles for Synthesis
18-14
A_Temp = A; Count = 8; reg [7:0] Count; for (Level=0; Level<=2; Level= Level+1)
always @(posedge Clock) begin begin Count = Count >> 1; // Divide by 2 if (Reset) process (In_A, In_B) for (K = 0; K <= (Count - 1); K = K + 1) begin Count <= 8'b0;
A_Temp[K] = A_Temp[K * 2] +else A_Temp[(K * 2) + 1]; if In_A = '1' then Count <= Count + 1; Out_Z <= '0'; end Sum_Out = A_Temp[0]; else if In_B = '1' then always @(Count) Out_Z <= '1'; begin else And_Bits = &Count; Out_Z <= '-'; Or_Bits = |Count; end if; end if; Xor_Bits = ^Count;
end
end end process; Synopsys 31833-000-S16
Conclusion Chip Synthesis Workshop
Need More Information or Help?
Synopsys on the Web:
Services:
SOLD
Workshops
solv-Net
Support Center
Application Consultants
Technical Articles
Application Notes
Release Notes
18-15
ESNUG
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Synopsys on the World Wide Web
18-16
Next SNUG City:___________ Date:___________
Synopsys Web Server www.synopsys.com
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
How to Use solv-NET
18-17
Web Page: www.synopsys.com Follow the solv-NET link Enter your solv-NET ID
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Human Sources for Information and Help 18-18
Contact the Support Center:
Click “Enter A Call” on the Synopsys Web page [email protected] 1-800-245-8005
Application Consultants:
Web E-mail Phone
Process and tool expertise available worldwide Contact your sales representative for more details
Consultants
Available for in-depth, on-site, dedicated, custom consulting Contact your sales representative for more details
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Other Sources for Information and Help 18-19
ESNUG Independent Email Synopsys User’s Group Customer problems, workarounds, cool scripts Updates on John Cooley’s love life, housecleaning, etc
[email protected] www.deepchip.com
www.eda.org Links to VHDL, Verilog Archives Links to EDA companies Links to other EDA sites
Newsgroups: comp.cad.synthesis comp.lang.verilog comp.lang.vhdl comp.lsi.cad comp.arch.fpga
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
That’s all Folks!
18-20
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit 1: Introduction to Synthesis Unit Objectives .................................................................................................................. 1-2 Just What Is “Synthesis”? .................................................................................................. 1-3 Synthesis is Constraint-Driven............................................................................................ 1-7 Synthesis is Path-Based...................................................................................................... 1-8 Chip Synthesis Process ..................................................................................................... 1-9 Design Compiler Interfaces............................................................................................... 1-10 Need Help? .................................................................................................................... 1-11 Search in Acrobat Reader ................................................................................................ 1-12 Module Synthesis Roadmap ............................................................................................. 1-13 Analyze, Elaborate - Read................................................................................................ 1-14
Unit 2: Setup, Libraries, and Objects Chapter O verview.............................................................................................................. 2-3 Synthesis Review ............................................................................................................... 2-4 Technology Library............................................................................................................ 2-5 Target Library.................................................................................................................... 2-6 Link Library Variable ......................................................................................................... 2-7 Use link to Resolve Design References ............................................................................... 2-9 The search_path Variable ................................................................................................. 2-10 Design Compiler Interfaces............................................................................................... 2-13 Design Compiler Three Initialization Files.......................................................................... 2-14 .synopsys_dc.setup File: Example..................................................................................... 2-15 .synopsys_dc_setup: Tcl and dcsh Mode.......................................................................... 2-16 Design Objects: VHDL Perspective.................................................................................. 2-18 Design Objects: Verilog Perspective ................................................................................. 2-19
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Table of Contents Design Objects: Schematic Perspective............................................................................. 2-20 Multiple Objects with the Same Name.............................................................................. 2-21 The get Command............................................................................................................ 2-22 What Is a List?................................................................................................................. 2-23 Other Handy List Commands........................................................................................... 2-25 Finding objects with dc_shell-t.......................................................................................... 2-26 Appendix - Synopsys DesignWare................................................................................... 2-32
Unit 3: Partitioning for Synthesis What is Partitioning?........................................................................................................... 3-3 Why Partition a Design? .................................................................................................... 3-4 Partitioning Within the HDL Descrip tion.............................................................................. 3-5 Eliminate Unnecessary Hierarchy........................................................................................ 3-6 No Hierarchy Dividing Combinational Paths........................................................................ 3-7 Partition at Register Boundaries .......................................................................................... 3-9 Avoid Glue Logic: Example .............................................................................................. 3-10 Balance Block Size With Run Times ................................................................................. 3-12 Separate Core Logic, Pads, Clocks, and JTAG ................................................................ 3-14 Partitioning Within Design Compiler.................................................................................. 3-15 The group Command ....................................................................................................... 3-16 The ungroup Command.................................................................................................... 3-17 Partitioning Strategies for Synthesis................................................................................... 3-19
Unit 4: Coding for Synthesis The Importance of Quality of Source .................................................................................. 4-3 RTL Coding Guide............................................................................................................. 4-4 The Big Picture: Think Hardware! ...................................................................................... 4-5 The Big Picture: Think Synchronous! ................................................................................. 4-6 The Big Picture: Think RTL! .............................................................................................. 4-7 RTL Synthesis Cookbook .................................................................................................. 4-8 Synthesis of if Statements............................................................................................... 4-9 if-else Statements ............................................................................................................. 4-10 if Statements and Latches ................................................................................................. 4-12 if-then-elseif Statements.................................................................................................... 4-13 Priority Interrupt Circuit - Synthesis Results ...................................................................... 4-15 31833-000-S16B
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Table of Contents When NOT to Use if-then-elseif ...................................................................................... 4-16 Synthesis of case Statements ........................................................................................... 4-17 case Statements .............................................................................................................. 4-18 Synthesis of loop Statements ............................................................................................ 4-25 Unrolling Loops ............................................................................................................... 4-26 Tradeoffs with Loops....................................................................................................... 4-27 Hardware Result .............................................................................................................. 4-28 Recoded Loop................................................................................................................. 4-29 Synthesis of Flip-Flops..................................................................................................... 4-30 Inferring Sequential Devices.............................................................................................. 4-31 Synthesis of Arithmetic Circuits......................................................................................... 4-34 Inferring Arithmetic Parts.................................................................................................. 4-35 DesignWare Arithmetic Resources.................................................................................... 4-36 DesignWare Implementation Selection.............................................................................. 4-37 Implying a Structure by Operand Placement...................................................................... 4-39 Verilog Preprocessor Directive ......................................................................................... 4-41 Appendix: Verilog Inference and Instantiation.................................................................... 4-44
Day 2: Constraining the Design Unit 5: Timing and Area RTL Block Synthesis.......................................................................................................... 5-3 Specifying an Area Goal..................................................................................................... 5-4 Timing Goals: Synchronous Designs.................................................................................... 5-5 Defining a Clock ................................................................................................................ 5-7 Defining a Clock in Design Compiler................................................................................... 5-8 Timing Goals: Synchronous Designs, I/O............................................................................. 5-9 Constraining the Input Paths ............................................................................................. 5-10 set_input_delay: Effect on Input Paths............................................................................... 5-13 Constraining Output Paths of a Design.............................................................................. 5-14 set_output_delay: Effect on Output Paths.......................................................................... 5-17 Useful Commands............................................................................................................ 5-19
Unit 6: Environmental Attributes RTL Block Synthesis.......................................................................................................... 6-3 31833-000-S16B
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Table of Contents Constraining for Timing— What’s Missing? ........................................................................ 6-4 Describing Environmental Attributes.................................................................................... 6-5 Modeling Capacitive Load ................................................................................................. 6-6 set_load examples.............................................................................................................. 6-7 Modeling Input Drive Strength............................................................................................ 6-8 set_driving_cell Examples .................................................................................................. 6-9 Variations in cell delays .................................................................................................... 6-10 Operating Conditions ....................................................................................................... 6-11 Net delays ....................................................................................................................... 6-14 What is a Wire load model? ............................................................................................ 6-15 Specifying Wire Loads in Design Compiler ....................................................................... 6-17 Wireload Model Mode .................................................................................................... 6-18 Check Your Constraints .................................................................................................. 6-19 Appendix - Create an Operating Condition....................................................................... 6-25
Unit 7: Time and Load Budgeting RTL Block Synthesis.......................................................................................................... 7-3 Time Budgeting .................................................................................................................. 7-4 Load Budgeting.................................................................................................................. 7-8 Summary of Describing Constraints.................................................................................. 7-14
Unit 8: Timing Analysis Does Your Design Meet its Goals?..................................................................................... 8-3 Timing Analysis: What Tool Do I Use? .............................................................................. 8-4 Static Timing Analysis......................................................................................................... 8-5 Timing Paths in Design Compiler......................................................................................... 8-6 Organizing Timing Paths Into Groups .................................................................................. 8-7 Schematic Converted to a Timing Graph........................................................................... 8-10 Components of Static Timing Analysis .............................................................................. 8-11 How DesignTime Calculates Delays ................................................................................. 8-12 Non-Linear Delay Model................................................................................................. 8-13 Wire Delay Calculations and Topology............................................................................. 8-15 Operating Conditions ....................................................................................................... 8-16 Edge Sensitivity in Path Delays ......................................................................................... 8-17 Setup Relationship Between Flip-Flops............................................................................. 8-18 31833-000-S16B
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Synopsys Chip Synthesis Workshop
Table of Contents DesignTime Timing Reports.............................................................................................. 8-19 Timing Report: Path Information Section........................................................................... 8-20 Timing Report: Path Delay Section.................................................................................... 8-21 Timing Report: Path Required Section............................................................................... 8-22 Timing Report: Summary Section...................................................................................... 8-23 Timing Report: Options .................................................................................................... 8-24 Timing Analysis: Diagnose Synthesis Results...................................................................... 8-25
Unit 9: DC Shell – Tcl Interface What is Tcl?....................................................................................................................... 9-4 Why Tcl? .......................................................................................................................... 9-5 Converting from dc_shell to dc_shell –t............................................................................... 9-6 Executing DC-Tcl Script.................................................................................................... 9-7 Getting Help....................................................................................................................... 9-8 Comments in DC-Tcl....................................................................................................... 9-11 Nesting Commands and Quoting ...................................................................................... 9-12 Using Wildcards............................................................................................................... 9-13 Tcl Data Types ................................................................................................................ 9-14 Using Variables................................................................................................................ 9-15 Arithmetic Expressions ..................................................................................................... 9-17 Using Lists in dc_shell-t.................................................................................................... 9-18 Definitions: Objects and Attributes.................................................................................... 9-19 Definitions: Collections & Collection Handle ..................................................................... 9-20 Creating Collections ......................................................................................................... 9-21 Manipulating Collections................................................................................................... 9-23 Filtering Collections.......................................................................................................... 9-26 Running dc_shell –t Interactively ....................................................................................... 9-27
Day 3: Synthesizing the Design Unit 10: Timing Revisited Timing Goals: Part Two.................................................................................................... 10-5 Modeling Clock Trees...................................................................................................... 10-6 Modeling Uncertainty on Clock Edges.............................................................................. 10-7 set_clock_uncertainty and Setup Timing............................................................................ 10-8 31833-000-S16B
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Table of Contents Modeling Source Latency................................................................................................. 10-9 Pre/Post Layout Clock................................................................................................... 10-10 Multiple Clocks - Synchronous....................................................................................... 10-11 Synchronous Multiple Clock Designs.............................................................................. 10-12 Creating a Virtual Clock................................................................................................. 10-14 Timing Goals for Multiple Clock Designs ........................................................................ 10-15 Hints for Multiple Clock Designs ................................................................................... 10-20 Multiple Clocks - Asynchronous..................................................................................... 10-21 Asynchronous Multiple Clock Designs............................................................................ 10-22 Synthesizing with Asynchronous Clocks.......................................................................... 10-23 The set_false_path command.......................................................................................... 10-24 Timing Goals Summary................................................................................................... 10-26 check_timing.................................................................................................................. 10-27 Appendix: Multi-Cycle Behavior..................................................................................... 10-29
Unit 11: Optimization Three Phases of Optimization........................................................................................... 11-3 Architectural Optimization ................................................................................................ 11-4 Arithmetic Operators........................................................................................................ 11-5 DesignWare Implementation Selection.............................................................................. 11-6 Other High-Level Optimizations........................................................................................ 11-8 Sharing Common Sub Expressions ................................................................................... 11-9 Coding To Force Sharing ............................................................................................... 11-10 Resource Sharing: Example ............................................................................................ 11-11 Operator Reordering ...................................................................................................... 11-13 Reordering Operators for Fast Design ............................................................................ 11-14 High-Level Synthesis is Constraint-Driven ...................................................................... 11-15 Logic-Level Optimization ............................................................................................... 11-16 What is Structuring? ...................................................................................................... 11-18 What is Flattening? ........................................................................................................ 11-19 Structuring vs. Flattening................................................................................................. 11-20 Three Phases of Optimization......................................................................................... 11-21 Combinational Mapping................................................................................................. 11-22 Sequential Mapping ....................................................................................................... 11-23 Fixing Design Rule Violations.......................................................................................... 11-24
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Table of Contents Unit 12: Compile Strategies Compile Completion ........................................................................................................ 12-3 User Interrupt.................................................................................................................. 12-5 Compile Report ............................................................................................................... 12-6 Compile Strategies........................................................................................................... 12-7 Constraint and Timing Analysis ......................................................................................... 12-8 Things to Look for........................................................................................................... 12-9 Use Re-Compile ............................................................................................................ 12-12 Change the Effort Level.................................................................................................. 12-13 Use Incremental Mapping............................................................................................... 12-16 When You Have Design Rule Violations ........................................................................ 12-19 What if You Have Hold Time Violations? ...................................................................... 12-20 Checking For Hold Time Violations ............................................................................... 12-23 Use Simultaneous Min-Max .......................................................................................... 12-24 Apply set_input_delay For Hold Time ........................................................................... 12-25 Apply set_output_delay For Hold Time .......................................................................... 12-26 Calculation of set_output_delay...................................................................................... 12-27 Fixing Hold Violations .................................................................................................... 12-28
Unit 13: Compiling a Hierarchical Design Compiling a Hierarchical Design— Under the Hood........................................................... 13-3 Compiling a Hierarchy ..................................................................................................... 13-4 First Phase of Compile ..................................................................................................... 13-5 Second Phase of Compile ................................................................................................ 13-6 Resolving Multiple Instances............................................................................................. 13-7 Designs Instantiated More Than Once .............................................................................. 13-8 check_design................................................................................................................... 13-9 Methods to Resolve Multiple Instances........................................................................... 13-10 Method #1: uniquify ....................................................................................................... 13-11 Method 2: compile + dont_touch.................................................................................... 13-13 Using set_dont_touch..................................................................................................... 13-15 uniquify vs. compile + dont_touch.................................................................................. 13-16
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Table of Contents Unit 14: DC-Tcl Procedures Control Flow: Examples................................................................................................... 14-3 Looping Structures........................................................................................................... 14-4 Tcl Procedures................................................................................................................. 14-6 Scope of Variables........................................................................................................... 14-8 Procedure Information...................................................................................................... 14-9 Tcl Procedure Example .................................................................................................. 14-10
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Table of Contents Day 4: Post-Synthesis Processes Unit 15: Compiling a Large Design Techniques for Compiling a Hierarchical Design ................................................................ 15-3 Hierarchical Compile Techniques: Types........................................................................... 15-4 Top-Down Compile Methodology.................................................................................... 15-5 Advantages of Top-Down................................................................................................ 15-6 Simple Compile Mode ..................................................................................................... 15-7 Hierarchical Compile Techniques...................................................................................... 15-8 Bottom-Up Compile Methodology................................................................................... 15-9 Pros & Cons of Bottom-Up Compile ............................................................................. 15-12 Techniques for the Second-Pass Compile ....................................................................... 15-14 Problems After the First-Pass Compile ........................................................................... 15-15 Use report_constraint -all............................................................................................... 15-16 Use report_timing........................................................................................................... 15-17 Build a New Design Budget............................................................................................ 15-22 characterize.................................................................................................................... 15-23 Appendix - Design Budgeter .......................................................................................... 15-30
Unit 16: Design Exploration Traditional Reactive Flow................................................................................................. 16-4 Proactive Design Methodology......................................................................................... 16-6 Design Exploration........................................................................................................... 16-7 Typical Compile Script (Basic) ....................................................................................... 16-11 Special WLM for Ports.................................................................................................. 16-13 set_max_capacitance ..................................................................................................... 16-15 set_max_transition.......................................................................................................... 16-16 set_max_fanout.............................................................................................................. 16-17 Fanout Loads................................................................................................................. 16-18 Fastest Runtimes for Design Exploration......................................................................... 16-21 Scenarios: Exploring Subdesigns..................................................................................... 16-23 I/O Timing Constraint Options........................................................................................ 16-28 Exploring Combinational Paths ....................................................................................... 16-30 User-Defined Path Groups ............................................................................................. 16-31
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Table of Contents Path Groups vs Critical Range........................................................................................ 16-34
Unit 17: Synthesizing for Test Chip Defects: They’re Not My Fault! ............................................................................... 17-3 Manufacturing Defects...................................................................................................... 17-4 Why Test for Manufacturing Defects? .............................................................................. 17-5 How Is Manufacturing Test Performed? ........................................................................... 17-6 The Stuck-At Fault Model ............................................................................................... 17-7 Controllability................................................................................................................... 17-9 Observability.................................................................................................................. 17-10 Fault Coverage .............................................................................................................. 17-11 Testing a Multistage, Pipelined Design............................................................................. 17-12 Scan Chains Help .......................................................................................................... 17-13 Use One-Pass Scan Synthesis ........................................................................................ 17-15 DFT Checking: Example ................................................................................................ 17-17 Testability Violation: Example......................................................................................... 17-18 Running ATPG............................................................................................................... 17-19 What Is DFTC?............................................................................................................. 17-20 Test Tools Summary ...................................................................................................... 17-22 Synthesizing for Test Summary ......................................................................................... 17-2
Unit 18: Conclusion Some Thoughts on Coding ............................................................................................... 18-3 Synthesis Quality Depends on Algorithms!........................................................................ 18-4 Classic Algorithms, Architectures, & Tradeoffs ................................................................. 18-5 Reflections on Synthesis: .................................................................................................. 18-6 Pre-Compile Checklist..................................................................................................... 18-7 What Do You Do First? .................................................................................................. 18-8 Compile Strategy ............................................................................................................. 18-9 Timing Analysis to Diagnose the Problem........................................................................ 18-10 Need More Training? .................................................................................................... 18-12 Advanced Chip Synthesis............................................................................................... 18-13 Coding Styles for Synthesis ............................................................................................ 18-14 Need More Information or Help? .................................................................................. 18-15 Synopsys on the World Wide Web ................................................................................ 18-16 31833-000-S16B
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Synopsys Chip Synthesis Workshop
Table of Contents How to Use solv-NET! ................................................................................................. 18-17 Human Sources for Information and Help ....................................................................... 18-18 Other Sources for Information and Help ......................................................................... 18-19
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i-1 For BHNEC internal use only.
Chip Synthesis Workshop
Synopsys Customer Education Services © 2000 Synopsys, Inc. All Rights Reserved Introduction Synopsys 31833-000-S16
For BHNEC internal use only.
Chip 31833-000-S16 Synthesis Workshop
First Things First ?
Instructor Introduction
?
Student Guide
?
Lab Guide
?
Measurement of Learning Objectives
i-2
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Workshop Goal
i-3
Acquire the basic skills to synthesize a design using Synopsys Design Compiler
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Workshop Prerequisites ?
Understanding of digital IC design
?
Some knowledge of Verilog or VHDL
?
Familiarity with UNIX and X-Windows
?
Familiarity with a Unix-based text editor
i-4
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Workshop Target Audience
i-5
?
Board, FPGA, or ASIC-level Digital Designers
?
Some Verilog or VHDL knowledge
?
Little or no formal experience with Design Compiler
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
4 Day Workshop Agenda
i-6
Day
1
Pre-synthesis Processes
Day
2
Constraining the Design
Day
3
Synthesizing the Design
Day
4
Post-synthesis Processes
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Icons Used in this Workshop
i-7
Lab Exercise
Caution
Question
Note
Hint, Tip, or Suggestion
Remember
Checklist
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Abbreviations and Acronyms: Exercise
Acronym
Meaning
Acronym
DC DC
HDL HDL
RTL RTL
GTECH GTECH
SOLD SOLD
SDF SDF
PDEF PDEF
DFT DFT
ATPG ATPG
Tcl Tcl
i-8
Meaning
Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 1 DAY 1
Unit
1-1
Topic
1
Introduction to Synthesis
2
Setup, Libraries, and Objects
3
Partitioning for Synthesis
4
Coding for Synthesis
Lab
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
1-2
After completing this unit you should be able to: ?
List the basic steps of synthesis
?
Describe advantages of synthesis
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Just What Is Synthesis?
1-3
Synthesis is the transformation of an idea into a manufacturable device to carry out an intended function
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Levels of Abstraction Idea Idea captured on back of envelope
Functional Graphical or textual description
1-4 Register Transfer Architectural HDL
Gate-Level Netlist
Our focus will be here Behavioral HDL and simulation language
Physical Device Silicon Introduction to Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
For Our Purposes, Synthesis is
1-5
Synthesis = Translation + Optimization + Mapping residue = 16’h0000; if (high_bits == 2’b10) residue = state_table[index]; else state_table[index] = 16’h0000;
Translate
HDL Source Optimize + Map
Generic Boolean (GTECH)
Target Technology Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Why Synthesis?
1-6 Reusability
Design Tricks DC knows plenty, tries them in context of loads, fanouts, library limitations
Parameterized code; Building-block approach; Retarget new libraries;
Why Me?
Abstraction Focus on high-level issues; tool & computer do dirty work to meet constraints
Verifiable Validate, implement, & verify in same language, Less error-prone entry
Portability IEEE standards; HDL portable across tools; technology-independent designs
Prestige
Productivity 6
How else to do 10 gates in 6 months?
Impress friends; hot skill on resume; job security; wealth and fame
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis is Constraint-Driven
1-7
Large
• Area
• • Small Short
• Delay
•
• High
You set the goals (through constraints) Design Compiler optimizes the design to meet your goals Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis is Path-Based
1-8
Design Compiler uses Static Timing Analysis (STA) to calculate the timing of the paths in the design.
MY_DESIGN A
CLK
D Q FF2 QB
D Q FF3 QB
Z
How many timing paths do you see in MY_DESIGN?
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Chip Synthesis Process
1-9
Chip Specification
Integrate Blocks
Partition Chip
Insert Test
Floorplan
Floorplan
RTL Block Synthesis
Place & Route
Final Verification Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Compiler Interfaces
1-10
Three ways to interface to Design Compiler (DC): 1
dc_shell-t (DC-Tcl)
2
dc_shell (DCSH)
3
Design Analyzer
4
Design Vision in 2000.11 release Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Need Help?
1-11
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Chip Synthesis Workshop
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Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Module Synthesis Roadmap GTECH
target_library
gtech.db
core_slow.db
my_chip.v(hd)
Y=A+B MY_CHIP
MY_CHIP
scripts
mapped
constraints.scr
my_chip.db my_chip.edif
my_chip.db
TRANSLATION
e writ
include
unmapped
DC_MEMORY compile
rea d
read analyze/ elaborate wr it e
HDL source
DC_MEMORY
1-13
OPTIMIZATION + MAPPING Introduction to Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Analyze, Elaborate - Read mychip.vhd
1-14
analyze -f vhdl mychip.vhd
mychip.v analyzed read -f verilog mychip.v
DC MEMORY
mychip.syn mychip.sim(VHDL) mychip.mra elaborate MYCHIP
Y=A+B MYCHIP write -ouput ./unmapped/mychip.db -hier unmapped mychip.db
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary: Exercise
1-15
Synthesis = __________ + __________ + __________
Advantages of Synthesis: ____________________ ____________________ ____________________
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 1: Introduction
1-16 Bring in the design
LAB
25 min
Run through the basic Synthesis Flow using scripts
Constrain the design
Synthesise the design
Inspect the design
Save the design
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Appendix
1-17
Synopsys Physical Synthesis
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Physical Challenge
Wire
Gate
Percentage of Delay
1-18
1.0 ?
0.5 ?
0.25 ?
0.18 ?
Silicon Technology
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Physical Synthesis 0.8?
1-19 0.5? to 0.35?
Logic
Logic
Synthesis
Synthesis
Place & Route
Place & Route
? 0.25?
Physical Synthesis Flow Place & Route
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Synopsys Physical Synthesis
Chip Architect: •Budgeting •Estimation •Floor Planning •IO Placement FlexRoute: •Detailed Top Level Routing •Pin assignment
Micro Controller
M e m o r y
Datapath
Memory Placed Gates Gates
1-20
Module Compiler : •Specialized Datapath Synthesis
Design Compiler : •Logic Synthesis Chip Architect: •Detailed Placement •Coarse Routing
Physical Compiler: •RTL Synthesis & Placement Together
Introduction to Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 1 DAY 1
Unit
2-1
Topic
1
Introduction to Synthesis
2
Setup, Libraries and Objects
3
Partitioning for Synthesis
4
Coding for Synthesis
Lab
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Unit Measurable Objectives
2-2
After completing this unit, you should be able to:
Specify the target library
Create the setup file for DC
Differentiate between the design objects
Find objects in DCSH mode and Tcl mode
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Chapter Overview
2-3
Technology Libraries
DC Setup File
Design Objects
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Synthesis Review
2-4
Recall the 3 steps involved in synthesis:
Translation
Optimization
Mapping
When DC maps a circuit, how will it know which cell library you are using? How will it know the timing of your cells?
Your ASIC vendor must provide a DC-compatible technology library for synthesis!
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Technology Library
2-5
Example of a cell description in .lib Format Cell name cell ( OR2_3 ) { area : 8.000 ; Cell Area pin ( Y ) { direction : output; timing ( ) { related_pin : "A" ; timing_sense : positive_unate ; rise_propagation (drive_3_table_1) { values ("0.2616, 0.2608, 0.2831,..) } rise_transition (drive_3_table_2) { values ("0.0223, 0.0254, ...) . . . . function : "(A | B)"; max_capacitance : 1.14810 ; min_capacitance : 0.00220 ; } pin ( A ) { direction : input; capacitance : 0.012000; . . . .
t
A Y
Y=A|B B
Pin A -> Pin Y nominal delays (look-up table)
Pin Y functionality Design Rules for Output Pin Electrical Characteristics of Input Pins Setup, Libraries, and Objects
Synopsys 31833-000-S16
Synopsys Workshop
Target Library Variable
2-6
The Target Library is the library used by Design Compiler for building a circuit
During mapping, DC will
choose functionally-correct gates from this library
calculate the timing of the circuit using vendor-supplied timing data for these gates
target_library is a reserved variable in DC
Set it to point to the library file(s) provided by your silicon vendor
set target_library my_tech.db
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Link Library Variable
2-7
Used to resolve design references
set link_library {* my_tech.db} DC Memory “*”
Target Library
First DC searches the memory and then the library files specified in the link_library variable
Second DC searches the all paths defined in the search_path variable
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Example
2-8
set target_library my_tech.db set link_library {* my_tech.db} ALU.v
bob/
my_tech.db source/
DECODE.db
TOP.v ALU.v
module ALU (A,B,OUT1); input A, B; output [1:0] OUT1; always @(A or B) begin . . .
UNIX% dc_shell-t dc_shell-t> read_verilog source/ALU.v Loading Loading Loading Loading Current
db file standard.sldb db file gtech.db db file my_tech.db verilog file source/ALU.v design is now ALU Setup, Libraries, and Objects
Synopsys 31833-000-S16
Synopsys Workshop
Use link to Resolve Design References
2-9
set target_library my_tech.db set link_library {* my_tech.db} TOP.v
bob/
my_tech.db source/
DECODE.db
TOP.v ALU.v
module TOP (A,B,OUT1); input A, B; output [1:0] OUT1; ALU U1 (.AIN (A), . . DECODE U2 (.A (BUS0), . .
dc_shell-t> read_verilog source/ALU.v dc_shell-t> read_verilog source/TOP.v dc_shell-t> link Unable to resolve reference ‘DECODE’ in ‘TOP’
How do we tell DC to find DECODE.db in bob? Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Set the search_path Variable
2-10
set target_library my_tech.db set link_library {* my_tech.db} lappend search_path {bob} TOP.v
bob/
my_tech.db source/
DECODE.db
TOP.v ALU.v
module TOP (A,B,OUT1); input A, B; output [1:0] OUT1; ALU U1 (.AIN (A), . . DECODE U2 (.A (BUS0), . .
dc_shell-t> read_verilog source/ALU.v dc_shell-t> read_verilog source/TOP.v dc_shell-t> link Loading db file bob/DECODE.db
dc_shell-t> which DECODE.db /server/my_project/bob/DECODE.db Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Use of analyze / elaborate
2-11
set target_library my_tech.db set link_library {* my_tech.db} lappend search_path {bob} TOP.v
bob/
my_tech.db source/
DECODE.db
TOP.v ALU.v
module TOP (A,B,OUT1); input A, B; output [1:0] OUT1; ALU U1 (.AIN (A), . . DECODE U2 (.A (BUS0), . .
dc_shell-t> analyze -f vhdl source/ALU.vhd dc_shell-t> analyze -f vhdl source/TOP.vhd dc_shell-t> elaborate TOP Loading db file bob/DECODE.db Current design is now ‘TOP’
Where do we specify the directory for the analyzed files? Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Chapter Overview
2-12
Technology Libraries
DC Setup File
Design Objects
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Design Compiler Interfaces
2-13
Four ways to interface to Design Compiler (DC), the Synopsys synthesis engine: design_vision (-tcl)
design_analyzer
Design Vision
Design Analyzer
Tcl mode
dcsh dcsh mode mode Design Compiler (DC)
dc_shell-t
In release 2000.11
dc_shell Setup, Libraries, and Objects
Synopsys 31833-000-S16
Synopsys Workshop
Design Compiler Three Initialization Files 2-14 User’s General Setup
1
~user
2
.synopsys_dc.setup
$SYNOPSYS/admin/setup .synopsys_dc.setup
User’s Specific Project Setup risc_design
Standard Setup
command log
3
.synopsys_dc.setup
./command.log ./view_command.log complete log of DA session Setup, Libraries, and Objects
Synopsys 31833-000-S16
Synopsys Workshop
.synopsys_dc.setup File: Example
2-15
target_library = "tc6a.db" link_library = {"*" tc6a.db opcon.db} symbol_library = "tc6a.sdb" search_path = search_path + "./unmapped” alias h history alias rc report_constraint -all_violators
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
.synopsys_dc.setup: Tcl and dcsh Mode
2-16
# set target_library {tc6a.db} set link_library {* tc6a.db opcon.db} set symbol_library {tc6a.sdb} set search_path “$search_path ./unmapped” alias h history alias rc "report_constraint -all_violators"
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Chapter Overview
2-17
Technology Libraries
DC Setup File
Design Objects
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Design Objects: VHDL Perspective
2-18
Design Clock
entity TOP is
port (A, B, C, D, CLK: in STD_LOGIC; Port OUTI: out STD_LOGIC_VECTOR (1 downto 0)); end TOP; architecture STRUCTURAL of TOP is
... signal INV1, INV0, BUS1, BUS0: STD_LOGIC;
Pin Net
begin U1: ENCODER port map (AIN=>A, . . .
Q1=>BUS1);
Cell U2: INV port map (A => BUS0, Z => INV0); U3: INV port map (A => BUS1, Z=> INV1); U4: REGFILE port map (D0=>INV0, D1=>INV1, . . CLK=>CLK); end STRUCTURAL;
Reference Setup, Libraries, and Objects
Synopsys 31833-000-S16
Synopsys Workshop
Design Objects: Verilog Perspective
2-19
Design module TOP (A,B,C,D,CLK,OUT1); input A, B, C, D, CLK; output [1:0] OUT1; Port
wire INV1,INV0,bus1,bus0;
Clock
Net
ENCODER U1 (.AIN (A), . . . .Q1 (bus1)); Reference INV Cell
U2 (.A (BUS0), .Z( INV0)), U3 (.A( BUS1), .Z( INV1));
Pin
REGFILE U4 (.D0 (INV0), .D1 (INV1), .CLK (CLK) ); endmodule Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Design Objects: Schematic Perspective 2-20 Design
Cell
Net
TOP Port
U4
U1 A B C D
A B C D
AIN
U2 INV
INV0
BUS1
U3 INV
INV1 D1
BIN CIN DIN
Clock
Q0
BUS0
Q1
D0
ENCODER CLK
OUT[1:0]
Q[1:0]
Pin
CLK REGFILE
CLK
Reference and Design
Designs: {TOP, ENCODER, REGFILE} References: {ENCODER, REGFILE , INV} Cells: {U1, U2, U3, U4} Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Multiple Objects with the Same Name
TOP A A B
CLK
U1 AIN ADD S BIN
B
2-21
CLK
U2 SIN D
Q
SUM
DFF
CLK
set_load 5 CLK Does “CLK” refer to a clock, port, net, or pin object? Does it matter onto which object DC places the load?
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
The get Command
2-22
dc_shell-t> set_load 5 [get_nets CLK]
Searches the current_design
Can be used stand-alone or composed with other functions
get commands return a list of object names, if any are found, or an empty list Setup, Libraries, and Objects
Synopsys 31833-000-S16
Synopsys Workshop
What Is a List?
2-23
Lists are a key component of Design Compiler
A list is a special type of character string
A list begins and ends with a “curly brace” {}
Each item is separated by white space
dc_shell-t> set mylist {el1 el2 el3} Information: Defining new variable ‘mylist’ el1 el2 el3
More to lists and objects in Chapter 9 Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
get Command Exercise TOP A
A
B B
2-24
U1 AI ADDS BI
U2 SIN
SOUT D
Q
SUM
DFF
CLK CLK
CLK
Write find commands to do the following: 1. List all of the ports in the design 2. List all of the cells with the letter “U” in their name 3. List all of the nets ending with “CLK” 4. List all of the “Q” pins in the design Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Other Handy List Commands
2-25
List all the input ports of the current design: dc_shell-t> all_inputs
List all the output ports of the current design: dc_shell-t> all_outputs
List all designs in the current design: dc_shell-t> get_designs
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Finding objects with dc_shell-t
2-26
Many of the get commands shown previously have an individual DC-Shell equivalent: Tcl mode
dcsh mode
get_cells *U*
find(cell, *U*)
get_nets *
find(net, “*”)
get_ports CLK
find(port, CLK)
get_clocks CLK
find(clock, CLK)
all_inputs
all_inputs()
all_outputs
all_outputs()
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Lab Details: Directory Structure
2-27
Source code for the CPU has been analyzed, elaborated, and saved (in .db format ) in the unmapped subdirectory
NOTE: Always invoke Design Compiler from the risc_design directory!
risc_design/ source/ vhdl/
unmapped/
scripts/
mapped/ reports/
verilog/
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Lab Details: Hierarchy of RISC_CORE CLK Instrn[31:0]
RISC_CORE
Reset
2-28
EndOfInstrn OUT_VALID PSW[10:0] RESULT_DATA[15:0] Rd_Instr STACK_FULL Xecutng_Instrn[31:0]
RISC_CORE
ALU
PRGRM_CNT_TOP CONTROL
INSTRN_LAT
REG_FILE
DATA_PATH STACK_TOP
PRGRM_CNT
PRGRM_FSM
PRGRM_DECODE Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Lab Details: Design Specifications
Clock Speed
200MHz (5ns)
Clock Skew
300 psec max
Voltage
1.8V ± 0.18V
Operating Temperature
0° ° C to 125° °C
Technology Library
core_slow.db
Symbol Library
core.sdb
2-29
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Lab Details: Exercise
2-30
From the specifications on the previous page, define the library setup variables: set target_library set link_library set symbol_library
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Lab 2: Introduction
2-31 Bring in the design
LAB
60 min
Introduction to Design Analyzer and the Synthesis Flow
Constrain the design
Synthesize the design PRGRM_CNT_TOP PRGRM_CNT
PRGRM_FSM
Inspect the design
PRGRM_DECODE Save the design
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Appendix: Synopsys DesignWare DesignWare®
Star IPs
Complete Source for Commodity IP
2-32
e.g., ARM MIPS IP
Re
ve el i dD s an ool T ing ag DRC ck Pa HDL
Building Blocks Silicon Libraries
MPEG2 USB2.0 PCI-X 8051 PCI 16550...
ls oo ry eT us
Complex IP Cores
>100 Components: memBIST, LFSR, FIFO CTL, etc… + - << >> * Pipeline Mult, Floating Point
Standard Cells
Memories + ProMA™
I/Os
µ 8 µ 1 0. .15 µ 0 .13 0
Memory Generator
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
DesignWare Standard Cells
2-33
0.18µm and 0.15µm Optimized for Design Compiler Optimized for Module Compiler Optimized for Power Compiler Over 600 cells simple and complex gates, buffers, flip flops, latches, complex cells, gated-clock cells
Actual silicon based on DesignWare standard cells
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
DesignWare ProMA Memory Generators
2-34
Single-port synchronous SRAM Dual-port synchronous SRAM Two-port register file ROM
Setup, Libraries, and Objects Synopsys 31833-000-S16
Synopsys Workshop
Synopsys Silicon Libraries Design Creation
High Level
Physical
2-35
Verification & Analysis
Design Compiler Module Compiler Power Compiler Behavioral Compiler
COSSAP VCS, Scirocco Verilog-XL ModelSim VERA, Formality PrimeTime DFT Compiler TetraMAX Synopsys Silicon RailMill Libraries PathMill FlexRoute TimeMill Chip Architect PowerMill Physical Compiler
Apollo Silicon Ensemble
Arcadia Dracula Calibre, Hercules Setup, Libraries, and Objects
Synopsys 31833-000-S16
Synopsys Workshop
Agenda: Day 1 DAY 1
Unit
3-1 Topic
1
Introduction to Synthesis
2
Setup, Libraries, and Objects
3
Partitioning for Synthesis
4
Coding for Synthesis
Lab
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
3-2
After completing this unit you should be able to:
List two effects of partitioning a circuit through combinational logic
State the main guideline for partitioning for synthesis
State how partitions are created in HDL code
List two DC commands for modifying partitions
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
What is Partitioning?
3-3
Partitioning is the process of dividing complex designs into smaller parts
“Divide and conquer!”
Ideally, all partitions would be planned prior to writing any HDL
Initial partitions are defined by the HDL
Initial partitions can be modified using Design Compiler Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Why Partition a Design?
3-4
Partitioning is driven by many (often competing) needs:
Separate distinct functions
Achieve workable size and complexity
Manage project in team environment
Design Reuse
Meet physical constraints
And many, many others ...
Focus will be on partitioning for synthesis Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Partitioning Within the HDL Description entity ADR_BLK is... end; architecture STR of ADR_BLK is U1:DEC port map(ADR, CLK, INST); U2:OK port map(ADR,CLK,AS,OK); end STR; module ADR_BLK (... DEC U1(ADR,CLK,INST); OK U2(ADR,CLK,AS,OK); endmodule
ADR CLK
3-5
ADR_BLK U1 DEC INST U2 OK OK
AS
entity and module statements define hierarchical blocks Instantiation of an entity or module also creates a new level of hierarchy
Inference of Arithmetic Circuits (+, -, *, ..) can create a new level of hierarchy
process and always statements do not create hierarchy Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Eliminate Unnecessary Hierarchy A
C
B REG A
CLK
COMBO LOGIC A
?
3-6
COMBO LOGIC B
?
COMBO REG LOGIC C C CLK
Are these partitions truly needed?
Design Compiler must preserve port definitions
Logic optimization does not cross block boundaries Adjacent blocks of combinational logic cannot be merged
Path from REG A to REG C may be larger and slower than necessary! Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
No Hierarchy in Combinational Paths A
CLK
3-7
C REG A
COMBO LOGIC A & B & C
REG C CLK
Better Partitioning
Related combinational logic is grouped into one block No hierarchy separates combinational functions A, B, and C
Combinational optimization techniques can now be fully exploited Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
No Hierarchy in Combinational Paths (cont) A
3-8
C REG A
COMBO LOGIC A & B & C
CLK
CLK
REG C
Best Partitioning
Related combinational logic is grouped into the same block with the destination register Combinational optimization techniques can still be fully exploited
Sequential optimization may now absorb some of the combinational logic into a more complex Flip-Flop (JK, T, Muxed, Clock-enabled…) Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Partition at Register Boundaries C
B
A
CLK
REG A
3-9
CLK
REG B
CLK
REG C
Good Partitioning Try to design so hierarchy boundaries follow register outputs. Simplifies timing constraints: All inputs to each block arrive with the same relative delay
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Avoid Glue Logic: Example
3-10
TOP C
A COMBO LOGIC A
CLK
REG A
COMBO LOGIC C
REG C CLK
B COMBO LOGIC B
CLK
REG B
Poor Partitioning The NAND gate at the top level serves only to “glue” the instantiated cells: Optimization is limited because the glue logic cannot be “absorbed” Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Remove Glue Logic Between Blocks
3-11
TOP A COMBO LOGIC A
C
CLK
REG A
COMBO REG LOGIC C C CLK + GLUE
B COMBO LOGIC B
CLK
REG B
Nothing but nets at top level
Good Partitioning
The glue logic can now be optimized with other logic
Top-level design is only a structural netlist, doesn’t need to be compiled Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Balance Block Size With Run Times TEENY
3-12
BIG
500 Gates
370,000 Gates
Too Small
100,000 Gates
8,000 Gates
Poor Partitioning
Too Big
If blocks are too small, the designer may be restricting optimization with artificial boundaries
If blocks are too big, compile run times can be very long Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Balance Block Size With Run Times
3-13
BIGGER SMALL 5,000 Gates
BIG 50,000 Gates
150,000 Gates
Good Partitioning
For quick turnaround, partition so that each block has 5,000 - 150,000 gates
Design Compiler has no inherent limit
Match module size to CPU and memory:
Larger modules are fine if sufficient resources are available
Choose smaller sizes when workstation power is limited Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Separate Core Logic, Pads, Clocks, and JTAG 3-14 Partition the Top-Level design into at least three levels of hierarchy: 1. Top-level 2. Mid-level 3. Core
TOP MID
CLOCK GEN JTAG
CORE ASYNCH
This partitioning is recommended due to: • Possible technology-dependent ( “black box”) I/O pad cells • Possible untestable “Divide By” clock generation • Possible technology-dependent JTAG circuitry Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Partitioning within Design Compiler
3-15
The group and ungroup commands modify the partitions in a design
group
ungroup
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
The group Command
3-16
group creates a new hierarchical block U1
U2
U3
group
DES_A
DES_B
DES_C
-design_name NEW_DES -cell_name U23 {U2 U3}
TOP_DESIGN U23 U2
U1
DES_B DES_A
U3
DES_C
NEW_DES
TOP_DESIGN Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
The ungroup Command
3-17
ungroup removes either one or all levels of hierarchy U1
U23 U2
U3
DES_B DES_A
current_design NEW_DES ungroup {U2 U3}
DES_C
NEW_DES TOP_DESIGN U1
DES_A
U23
NEW_DES TOP_DESIGN Partitioning for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
The ungroup Command: Exercise
U1
U23 U2
U3
DES_Y DES_A
DES_Z
3-18
What happens if you ungroup U23? ungroup {U23}
DES_B TOP_DESIGN
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Partitioning Strategies for Synthesis
Do not separate combinational logic across hierarchical boundaries
Place hierarchy boundaries at register outputs
Size blocks for reasonable runtimes
Separate core logic, pads, clocks, and JTAG
3-19
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Partitioning for Synthesis: Summary
3-20
What do we gain by “partitioning for synthesis”?
Better results -- smaller and faster designs
Easier synthesis process -- simplified constraints and scripts
Faster compiles -- quicker turnaround
Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 3: Introduction
LAB
3-21
30 min
group / ungroup
Design Problem: Timing Violation
PRGRM_FSM
PRGRM_ DECODE
PRGRM_CNT
Change Partition for Better Synthesis Results Partitioning for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 1 DAY 1
Unit
4-1
Topic
1
Introduction to Synthesis
2
Setup, Libraries, and Objects
3
Partitioning for Synthesis
4
Coding for Synthesis
Lab
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Measurable Objectives
4-2
After completing this unit you should be able to:
Describe hardware implications for the following coding constructs:
if-else case loops
Compile HDL code and observe the effects in synthesis
Use DesignWare elements in your RTL source code
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
The Importance of Quality of Source Poor Start Point
4-3
Better Start Point Best Start Point
Goal
Code that is functionally equivalent, but coded differently, will give different synthesis results
You cannot rely solely on Design Compiler to “fix” a poorly coded design!
Try to understand the “hardware” you are describing, to give DC the best possible starting point Coding for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
RTL Coding Guide
4-4 The three big picture guidelines
Coding cookbook
L D H
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
The Big Picture, Think Hardware!
Write HDL hardware descriptions
4-5
Think of the topology implied by the code
Do not write HDL simulation models
Yes!
No explicit delays No file I/O
No!
after 20 ns and 2 clock cycles OUTPUT <= IN1 + RAM1; wait 20 ns; ...
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
The Big Picture, Think Synchronous!
4-6
Synchronous designs run smoothly through synthesis, test, simulation, and layout
Asynchronous designs may require hand instantiation and extensive simulation to verify
Isolate asynchronous logic into separately compiled blocks ACK_SET ADDR_IN
ADDR DECODE +5
ACK
AS ACK_CLR
How am I going to synthesize this? Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
The Big Picture, Think RTL!
4-7
RTL = Register Transfer Level
Writing in an RTL coding style means describing
the register architecture, the circuit topology, and the functionality between registers
Design Compiler optimizes logic between registers
It does not optimize the register placement
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
RTL Synthesis Cookbook
4-8
The three big picture guidelines
Coding cookbook
L D H
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis of if Statements
4-9
Synthesis of if statements
Synthesis of case statements
Synthesis of loop statements
Synthesis of Flip-Flops
Synthesis of arithmetic circuits
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
if-else Statements
4-10
The if-else construct implies multiplexing hardware
One output value is selected based on a certain condition
Actual circuit implementation depends on target library and constraints
if (Aflag = '1') then OutData <= A + B; else OutData <= C + D; end if;
A B C D
+
D1 OutData
+
D0 S
Aflag
How could we recode this example so that the multiplexing hardware was before the adder? Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
if-else Statements (cont)
4-11
Location of multiplexing hardware depends on location of if-else construct if (Aflag == 1’b1) begin Op1 <= A; Op2 <= B; end else begin Op1 <= C; Op2 <= D; end
A
D1 Op1
C
D0
S
Aflag B
+
OutData
D1 Op2
D
D0
S
OutData <= Op1 + Op2;
Aflag
What if Aflag was late-arriving? Which circuit is better? What if the else was missing? Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
if Statements and Latches
4-12
To infer latches, use an if statement without an else clause
VHDL/Verilog language definitions require signals to maintain their old value unless a new value is assigned Latches implement this requirement in hardware
LS373: process (ALE, ADBUS)
always @ (ALE or ADBUS)
begin
begin
if (ALE = ‘1’) then
if (ALE)
ABUS <= ADBUS;
ABUS <= ADBUS; end
end if; end process LS373; 8
ADBUS ALE
/
8
D
Q
/
ABUS
G Coding for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
if-then-elseif Statements
4-13
Since VHDL and Verilog if-elseif statements imply priority, they should only be used if priority checking is a circuit requirement
Otherwise, priority control logic will be synthesized Result will be more, and possibly slower logic
Example: Priority Interrupt Controller
One or more of four (input) interrupt lines (int0..int3) may be asserted Only one output should be asserted int0 has the highest priority int0 int1 int2 int3
active[0] active[1] active[2] active[3] Coding for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
if-then-elseif Statements (cont)
4-14
module test(active,int0,int1,int2,int3); input int0,int1,int2,int3; output [3:0] active; Why are the reg int0,int1,int2,int3; outputs active[3:0] reg [3:0] active; initialized to 0? always@(int0 or int1 or int2 or int3) begin active[3:0] <= 4’b0; if (int0) active[0] <= 1’b1; Which flag has the else if (int1) active[1] <= 1’b1; highest priority? else if (int2) active[2] <= 1’b1; else if (int3) active[3] <= 1’b1; end; endmodule
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Priority Interrupt Circuit: Synthesis Results
int0
active[0]
int1
active[1]
4-15
active[2] int2 active[3] int3
Priority Logic
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
When NOT to Use if-then-elseif
When signals have equal priority
When signals are mutually exclusive
4-16
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis of case Statements
4-17
Synthesis of if Statements
Synthesis of case Statements
Synthesis of loop Statements
Synthesis of Flip-Flops
Synthesis of Arithmetic Circuits Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
case Statements
case statements in Verilog
case statements in VHDL
4-18
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
case Statements
4-19
Case statements imply parallel mux function. process (SEL,A,B,C,D) begin case SEL is when “00” => OUTC <= A; when “01” => OUTC <= B; when “10” => OUTC <= C; when others => OUTC <= D; end case; end process;
VHDL Code always@(SEL or A or begin case (SEL) 2’b00 : OUTC = 2’b01 : OUTC = 2’b10 : OUTC = default : OUTC endcase end
00 01 10 11
A B C D
OUTC
B or C or D)
SEL
2
A; B; C; = D;
Note: Actual gates synthesized might not be a 4:1 MUX.
Verilog Code Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Interrupt Vector Address Generator
4-20
Build a logic that takes the signals of the priority interrupt circuit and generates a 16-bit memory address that is unique for each interrupt. interrupt
address to be generated
active[0] active[1] active[2] active[3]
0000000000 00000100b 0000000000 00000110b 0000000000 00001000b 0000000000 00001010b
(0004h) (0006h) (0008h) (000Ah)
Each of the above memory locations contain the starting address of an interrupt handling routine, which is read by the processor at an appropriate time after a valid interrupt is recognized. active[0] active[1] active[2] active[3]
vec[15:0]
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Address Generator: Verilog
4-21
always @(active[3] or active[2] or active[1] or active[0]) begin case ({active[3], active[2], active[1], active[0]}) 4’b1000 : temp = 3’b010; 4’b0100 : temp = 3’b011; 4’b0010 : temp = 3’b100; 4’b0001 : temp = 3’b101; 4’b0000 : temp = 3’b000; default : temp = 3’bxxx; endcase end always vec[15:4] = 12’h000; always vec[0] = 0; always @(posedge clk) vec[3:1] = temp;
What happens if you do not include the default clause? Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Schematic of Address Generator
4-22
A schematic after compiling the source code of the Interrupt Vector Address Generator. active[2] D
Q
vec[3]
active[3] CLK
active[0] D
Q
vec[2]
active[1] CLK
D
clk
Q
vec[1]
CLK
vec[0] vec[15:4]
vec[15:0]
gnd
Without the default clause, the case statement would not be fully specified and infer latches. Can be controlled by compiler directives. Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Compiler Directive full_case
4-23
always @(active[3] or active[2] or active[1] or active[0]) begin case ({active[3], active[2], active[1], active[0]}) //synopsys full_case 4’b1000 : temp = 3’b010; 4’b0100 : temp = 3’b011; 4’b0010 : temp = 3’b100; 4’b0001 : temp = 3’b101; 4’b0000 : temp = 3’b000; endcase end always vec[15:4] = 12’h000; always vec[0] = 0; always @(posedge clk)
vec[3:1] = temp;
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Compiler Directive parallel_case
4-24
always @(active[3] or active[2] or active[1] or active[0]) begin temp = 3’b000; case (1’b1)
//synopsys parallel_case
active[3] : temp = 3’b010; active[2] : temp = 3’b011; active[1] : temp = 3’b100; active[0] : temp = 3’b101; endcase end always vec[15:4] = 12’h000; always vec[0] = 0; always @(posedge clk)
vec[3:1] = temp;
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis of loop Statements
4-25
Synthesis of if Statements
Synthesis of case Statements
Synthesis of loop Statements
Synthesis of Flip-Flops
Synthesis of Arithmetic Circuits Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Unrolling Loops
4-26
In synthesis, for loops are “unrolled” during translation, and then synthesized process process (( a, a, bb )) begin begin for for ii in in 00 to to 33 loop loop out(i) out(i) <= <= a(i) a(i) and and b(3 b(3 -- i); i); end end loop; loop; end process; end process; out(0) out(1) out(2) out(3)
<= <= <= <=
a(0) a(1) a(2) a(3)
and and and and
b(3); b(2); b(1); b(0);
integer integer i; i; always@( always@( aa or or b) b) begin begin for ( i = 0; i for ( i = 0; i <= <= 33 ;; ii == ii ++ 11 )) out[i] out[i] <= <= a[i] a[i] && b[3 b[3 -- i]; i]; end end
a(0) b(3)
out(0)
a(1) b(2)
out(1)
a(2) b(1) a(3) b(0)
out(2) out(3)
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Tradeoffs with Loops process (data) variable sum : integer; begin sum := 0; -- Count the 1’s for i in 0 to 7 loop sum := data(i) + sum; end loop; --check parity odd_parity <= sum mod 2; end process;
4-27
always@(data) begin sum = 0; /* Count the number of ‘1’s */ for (i = 0; i < 8; i = i + 1) sum = sum + data[i]; /* Check if even or odd number */ odd_parity = sum[0]; end;
What does the hardware look like for this example?
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Hardware Result
4-28
Data(2)
+
Data(0)
+ Data(1)
/ 2
...
Data(6) / 2
+
/ 3
+
Data(7)
How could this be recoded?
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Recoded Loop
4-29
VHDL
unrolled
process (data) variable odd_parity : bit; begin odd_parity <= ‘0’; for i in 0 to 7 loop odd_parity <= data(i) xor odd_parity; end loop; end process;
Verilog always@ (data) begin odd_parity = ^data; end optimized design
binary XOR Coding for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis of Flip-Flops
4-30
Synthesis of if Statements
Synthesis of case Statements
Synthesis of loop Statements
Synthesis of Flip-Flops
Synthesis of Arithmetic Circuits Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Inferring Sequential Devices
4-31
“Registering” a signal means clocking it into a Flip-Flop
For DC to infer Flip-Flops, your code must imply signal assignments that take place in response to the edge of another signal
DC requires specific coding templates to infer registers
A B CLK RSTn
How do you: +
D
Q
S1 assign A+B to S1 in response to a rising edge on CLK ? With an asynchronous reset? Coding for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Flip-Flop: Example
4-32
process (CLK, RSTn) begin if (RSTn =‘0’) then -- async reset S1 <= ‘0’; elsif (CLK’event and CLK = ‘1’) then S1 <= A + B; end if; end process;
A B CLK RSTn
+
D
Q
always@(posedge CLK or negedge RSTn) begin if (! RSTn) S1 S1 <= 1’b0; else S1 <= A + B; end
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Inferring Sequential Devices
Design Compiler can synthesize hardware using a wide variety of flip-flops and latches Latch
Latch Latch Latch w/ w/Dual w/Sync Async Async Clr
DFF
DFF DFF DFF w/ w/Dual w/Sync Muxed DFF Async Async Cntl.
MS Latch
JKFF
The registers in your final circuit depend on:
4-33
Coding style (including attributes and directives) Types of registers available in the target_library
(V)HDL Compiler generates an inference report Example: Inference Report for an AR Flip-Flop Register Name Q_reg
Type
Width
Bus
MB
Flip-Flop
1
-
-
AR
AS
SR
SS
ST
Y
N
N
N
N
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis of Arithmetic Circuits
4-34
Synthesis of if Statements
Synthesis of case Statements
Synthesis of loop Statements
Synthesis of Flip-Flops
Synthesis of Arithmetic Circuits Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Inferring Arithmetic Parts
4-35
process (A, B, C, D, addr) begin if (addr = 12) then Result <= A + B; else Result <= C + D; always@ (A or B or C or D or addr) end if; begin end process;
if (addr == 4’d12) Result <= A + B; else Result <= C + D; end
What does the hardware look like in this example? Where do the mathematical circuits come from? Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
DesignWare Arithmetic Resources AND Gates, OR Gates, Flip-Flops...
link_library, target_library
Adders, Multipliers, Comparators...
Technology Library
4-36
synthetic_library
DesignWare Library
What is DesignWare?
Technology-independent “soft macros” such as adders,comparators, etc., which are synthesized into gates from your target library Enables the user to imply large and complex arithmetic operations to be synthesized: if (A1 >= A2) Y <= M * X + B; else Y <= M * X + C; Coding for Synthesis
Synopsys 31833-000-S16
Chip Synthesis Workshop
DesignWare Implementation Selection
4-37
Multiple architectures for each macro allow DC to evaluate speed/area tradeoffs and choose the best implementation fastest
Ripple Carry Select
Z <= A + B; Conditional Sum Synthesis
DW Foundation
Brent-Kung
+
Carry Look-Forward HDL Operator
Carry Look-Ahead smallest
Ripple Carry
DW Basics
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Enabling Faster DW Implementations
4-38
DesignWare components come from synthetic libraries
Synopsys-provided synthetic library files reside in directory $SYNOPSYS/libraries/syn
The synthetic_library variable points to a list of synthetic library database (.sldb) files:
synthetic_library = {dw_foundation.sldb} link_library = link_library + synthetic_library
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Implying a Structure by Operand Placement 4-39
As with if-else blocks, coding style implies a circuit topology
V/HDL Compiler parses expressions from left to right Parentheses will override this default order DesignWare built in this order is the starting point for DC SUM <= A*B + C*D + E + F + G
A B C D
* *
+ E
+ F
+
G
+
SUM
Total Delay = Multiplier + 4 adders
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Implying a Structure by Operand Placement (cont)
4-40
Change the order, or use parentheses to force a different topology: SUM <= E + F + G + C*D + A*B SUM <= (A*B) + E F
+ G C D
(
(C*D) + ((E+F) + G)
+ *
+ A B
+
)
SUM
*
Max Delay = Multiplier + 2 adders
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Verilog Preprocessor Directive
4-41
module IFDEF(out,a,b,clk); output out; input clk,a,b; reg out; always@(posedge clk) begin ‘ifdef SYN out=b && a; ‘else SYN $display (“The output is: “); out=b && a; ‘endif set hdlin_enable_vpp true end analyze -f verilog -d SYN IFDEF.v endmodule elaborate IFDEF -lib WORK Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Documentation
4-42
Synopsys On-Line Documentation
HDL Compiler for Verilog Reference Manual
VHDL Compiler Reference Manual
Guide to HDL Coding Styles for Synthesis
Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! www.synopsys.com -> SNUG -> SNUG Papers -> 2000 San Jose
“full_case parallel_case”, the Evil Twins of Verilog Synthesis www.synopsys.com -> SNUG -> SNUG Papers -> 1999 Boston
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 4: Introduction LAB
4-43
60 min
Examine Coding Style Issues LOOP_BAD IF_BAD
LOOP_GOOD IF_GOOD
LOOP_BEST IF_BEST
Area Path Value
compare_design IF_BAD IF_GOOD Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Appendix
4-44
Inference and Instantiation
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Verilog Inference and Instantiation Inference
4-45
identifier for the resource
always @(A or B) begin :b1 /* synopsys resource r0: map_to_module = "DW02_mult", implementation = "wall", ops = "a1"; */ PROD <= A * B; //synopsys label a1 end;
synthetic module Wallace tree synthesis model
Instantiation // synopsys dc_script_begin // set_implementation wall U1 // synopsys dc_script_end DW02_mult #(Awidth, Bwidth) U1(A, B, TC, PROD); report_resources Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
VHDL Inference and Instantiation
4-46
Inference library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; inside the architecture block: PROD <= A * B; Instantiation library IEEE, DWARE; use IEEE.std_logic_1164.all; use DWARE.DW_Foundation_comp; inside the architecture block: U1: DW01_add
Coding for Synthesis Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 2 DAY 2
Unit
5-1 Topic
5
Timing and Area
6
Environmental Attributes
7
Time and Load Budgeting
8
Timing Analysis
9
DC Tcl - Introduction
Lab
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
5-2
After completing this unit, you should be able to:
Constrain a design for area
Constrain a design for timing
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
RTL Block Synthesis Write RTL HDL Code
Rewrite
No
Analysis
Simulate OK? Yes
Yes Major Violations?
5-3
No
No
Synthesize HDL Code To Gates
Constraints & Attributes Area & Timing Goals
Met Constraints? Yes Timing and Area
Synopsys 31833-000-S16
Chip Synthesis Workshop
Specifying an Area Goal dc_shell-t> dc_shell-t> dc_shell-t> dc_shell-t>
5-4
current_design current_design PRGRM_CNT_TOP PRGRM_CNT_TOP set_max_area set_max_area 100 100
Units are those of target library, defined by the vendor 2-input-NAND-gate transistors square mils
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Goals: Synchronous Designs
5-5
Synchronous Designs:
Data arrives from a clocked device
Data goes to a clocked device
Objective:
Define the timing constraints for all paths within a design:
all input logic paths
the internal (register to register) paths, and
all output paths
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Goals: Synchronous Designs (cont)
5-6
TO_BE_SYNTHESIZED D Q FF1 QB
M
N
D Q FF2 QB
X
D Q FF3 QB
S
T
D Q FF4 QB
Clk
What information must you provide to constrain all the register-to-register paths in your design? Does the duty cycle of your clock matter? Example: Clock Period = 10ns
Setup = 1ns
What is the max delay requirements for the register-to-register paths in the block TO_BE_SYNTHESIZED? Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Defining a Clock
5-7
User MUST Define: Clock Source (port or pin) Clock Period
User may also define: Duty Cycle Offset/Skew Clock Name TO_BE_SYNTHESIZED
Clk N
Period
D Q FF2
X
D Q FF3
S
Clk
1 Clock Cycle Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Defining a Clock in Design Compiler
5-8
dc_shell-t> create_clock -period 10 [get_ports Clk] dc_shell-t> set_dont_touch_network
[get_clocks Clk]
TO_BE_SYNTHESIZED
Clk
Creating a clock constrains timing paths between registers
Use report_clock to see defined clocks and their attributes
set_dont_touch_network tells DC not to “buffer up” the clock net, even if there are too many flip-flops loading it
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Goals: Synchronous Designs, I/O
5-9
Path X constrained by create_clock TO_BE_SYNTHESIZED D Q FF1 QB
M
N
D Q FF2
X
D Q FF3
S
T
D Q FF4 QB
Clk
Paths N & S are still unconstrained!
Method: 1. Define the clocks 2. Define the I/O timing relative to the clocks
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Constraining the Input Paths TO_BE_SYNTHESIZED
External Logic
Launch edge triggers data
M D
5-10
N
A
Q
D
Q
Clk
Next edge captures data
Clk
TClk-q
TM
TN
TSETUP
What information must you provide to constrain the input paths?
Clk Valid new data
A (TClk-q + TM)
(TN + TSETUP)
(Input Delay) Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Constraining Input Paths in DC
5-11
dc_shell-t> set_input_delay -max 4 -clock Clk [get_ports A]
The set_input_delay command constrains input paths Launch Edge
You specify how much time is used by external logic... DC calculates how much time is left for the internal logic
Capture Edge
4
delay of time left for external internal logic logic
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
set_input_delay: Exercise EXTERNAL CIRCUIT
TO_BE_SYNTHESIZED
CLK-OUTPUT 7.4 ns (worst)
Clock (50 MHz)
5-12
A
N Clk
create_clock
U1
_______________________________________
set_dont_touch_network set_input_delay
____________________________
____________________________________ 0.0
Clk
D Q
10.0
20.0
7.4
A Constraint of YOUR input path Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
set_input_delay: Effect on Input Paths EXTERNAL CIRCUIT
Clk (50 MHz)
CLK-OUTPUT 7.4 ns (worst)
5-13
TO_BE_SYNTHESIZED
A N
Clk
D Q
U1
create_clock -period 20 [get_ports Clk] set_dont_touch_network [get_clocks Clk] set_input_delay -max 7.4 -clock Clk [get_ports A]
If U1 has a 1 ns setup requirement: What is the maximum delay for TN? Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Constraining Output Paths of a Design U3 Launches Data
External Logic
TO_BE_SYNTHESIZED U3 D
S
B
T
Q
D
Q
5-14 External Flip-Flop captures data
Clk
TClk-q
Ts
TT
TSETUP
What information must you provide to constrain the output paths? Launch Edge
Capture Edge
Clk B
Valid new data
TClk-q + TS TT + TSETUP (Output Delay) Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Constraining Output Paths in DC
5-15
dc_shell-t> set_output_delay -max 5.4 -clock Clk
[get_port B]
The set_output_delay command constrains output paths You specify how much time is needed by external logic... DC calculates how much time is left for internal logic
Capture Edge
Launch Edge
5.4 Constraint of YOUR output path
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
set_output_delay Exercise
5-16
TO_BE_SYNTHESIZED U3 D
Clk (50 MHz)
EXTERNAL CIRCUIT B
S Q
Setup Requirement: 7.0 ns
Clk
create_clock
_______________________________________
set_dont_touch_network set_output_delay 0.0
_____________________________
___________________________________ 10.0
20.0
Clk 7.0
Gets clocked here
B Data launched here
Must be valid here Timing and Area
Synopsys 31833-000-S16
Chip Synthesis Workshop
set_output_delay: Effect on Output Paths 5-17 TO_BE_SYNTHESIZED U3
D
Q
S
EXTERNAL CIRCUIT
B
Clk
Setup Requirement: 7.0 ns
Clock (50 MHz)
create_clock -period 20 [get_ports Clk] set_dont_touch_network [get_clocks Clk] set_output_delay -max 7.0 -clock Clk [get_ports B]
If U3 has TCLK-Q = 1.0ns: What is the maximum delay for TS? Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Area & Timing Goals Summary: Exercise 5-18 How do you constrain for area?
TO_BE_SYNTHESIZED
Clk
D Q FF1 QB
M
N
D Q FF2 QB
X
D Q FF3 QB
S
T
D Q FF4 QB
How do you constrain the register to register paths? How do you constrain the the I/O paths? Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Useful Commands
5-19
report_port -verbose
Returns all attributes and constraints placed on all input and output ports
report_clock
Returns the source, waveform and period of all clock objects in current_design
reset_design
Removes attributes and constraints from current_design
list_libs
Returns the available libraries in memory
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 5: Introduction
LAB
5-20
30 min unmapped PRGRM_CNT_TOP.db
Apply Timing Constraints
Bring in the design
Constrain the design
unmapped
prgrm_attr.db
Save the design
Timing and Area Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 2 DAY 2
Unit
6-1 Topic
5
Timing and Area
6
Environmental Attributes
7
Time and Load Budgeting
8
Timing Analysis
9
DC Tcl - Introduction
Lab
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
6-2
After completing this unit, you should be able to:
Scale cell delays for Temperature and Voltage extremes
Use Wire Load Models within DC
Use constraints for DC to account for external circuitry
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
RTL Block Synthesis Write RTL HDL Code
Rewrite
No Yes Major Violations?
6-3
Simulate OK?
Yes No
Synthesize HDL Code To Gates
Constraints & Attributes Area & Timing Goals
Netlist Analysis
No
Met Constraints?
Yes Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Constraining for Timing: What’s Missing? TO_BE_SYNTHESIZED
6-4
set_output_delay
set_input_delay N
D Q FF2 QB
X
D Q FF3 QB
S
CLK
create_clock
What physical information about the chip is required in order to accurately calculate the speed of each path?
What information (besides external setup) does DC require in order to ensure logic S meets timing?
What information (besides input delay) does DC require in order to ensure logic N meets timing? Environmental Attributes
Synopsys 31833-000-S16
Chip Synthesis Workshop
Describing Environmental Attributes
6-5
set_operating_conditions set_load
set_driving_cell set_wire_load_model
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Modeling Capacitive Load
6-6
TO_BE_SYNTHESIZED
In order to accurately calculate the timing of an output circuit, DC needs to know the total capacitance driven by the output cells
set_load allows the user to specify the external capacitive load on ports
By default, DC assumes that the external load on ports is 0
You can specify some other constant value, or... The load_of command can be used to specify the external load as the pin load of a cell in your technology library
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
set_load Examples
6-7
Use set_load to specify a load value on an output port: OUT1
set_load 5 [get_ports OUT1]
5
Use set_load load_of(lib/cell/pin) to place the load of a gate from the technology library on the port: A
OUT1
OUT1
A AN2 B
A A
set_load [load_of(my_lib/and2a0/A)] [get_ports OUT1] set_load [expr [load_of(my_lib/inv1a0/A) * 3]] OUT1
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Modeling Input Drive Strength
6-8
In order to accurately calculate the timing of an input circuit, DC needs to know the transition time of the signal arriving at the input port
set_driving_cell allows the user to specify a realistic external cell driving the input ports
By default, DC assumes that the external signal has a transition time of 0
Placing a driving cell on the input ports causes DC to calculate the actual (non-zero) transition time on the input signal as though the specified library cell was driving it TO_BE_SYNTHESIZED
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
set_driving_cell Examples
6-9
TO_BE_SYNTHESIZED ND2 IN1
dc_shell-t> set_driving_cell -lib_cell and2a0 \ [get_ports IN1]
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Variations in Cell Delays
6-10
Library cells are usually characterized using “nominal” voltage and temperature: nom_process : nom_temperature : nom_voltage :
1.0; 25.0; 1.8;
What if the circuit is to operate at a voltage and/or temperature OTHER than nominal?
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Operating Conditions
6-11
Vendors allow for synthesis of circuits which will not operate under “nominal” conditions by embedding operating condition models in the technology libraries
Operating conditions can be placed on your design by using the set_operating_conditions command
During synthesis, “nominal” cell and wire delays will be scaled based on the operating conditions
worst Delay
nominal best Temperature
Delay
worst nominal best
Voltage
Delay
worst nominal best Process Environmental Attributes
Synopsys 31833-000-S16
Chip Synthesis Workshop
Default Operating Conditions
6-12
By default, NO operating conditions are specified for a design
Use report_lib libname to list the vendor-supplied operating conditions
Operating Conditions: Name Library Process Temp Volt ---------------------------------------------------typ_25_1.80 my_lib 1.00 25.00 1.80 slow_125_1.62 my_lib 1.00 125.00 1.62 fast_0_1.98 my_lib 1.00 0.00 1.98
To set operating conditions, enter
dc_shell-t> set_operating_conditions -max “slow_125_1.62” quotes are optional Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Technology Libraries
6-13
ASIC vendors might deliver multiple technology libraries, defining:
best-case and worst-case operating conditions
optimistic and pessimistic WLM
minimum and maximum timing delay
Syntax: set_min_library max_library -min_version min_library Example: dc_shell-t> set_min_library ssc_core_slow -min_version ssc_core_fast dc_shell-t> set_operating_conditions -max slow_125_1.62 \ -min fast_0_1.98 Cannot use -min without -max Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Net delays
6-14 I/O Pad Driver
RAM
Prior to layout, how can the RC delay of nets be estimated?
Receiving Gates
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
What Is a Wire Load Model?
6-15
A wire load model is an estimate of a net’s RC parasitics based on the net’s fanout:
Model is created by your vendor
Estimates are based on statistics from other designs the vendor has fabricated using this process
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Wire Load Model: Standard Format
6-16
Example: Standard Format Name : 160KGATES Location : ssc_core_slow Resistance : 0.000271 Capacitance : 0.00017 Area : 0 Slope : 50.3104 Fanout Length --------------------------------1 31.44 2 81.75 3 132.07 4 182.38 5 232.68 Time Unit
R per unit length C per unit length Extrapolation slope
: 1ns Capacitive Load Unit : 1.000000pf Pulling Resistance Unit : 1kilo-ohm Environmental Attributes
Synopsys 31833-000-S16
Chip Synthesis Workshop
Specifying Wire Loads in Design Compiler 6-17
Manual model selection dc_shell-t> set current_design addtwo dc_shell-t> set_wire_load_model -name 160KGATES
Automatic model selection dc_shell-t> set auto_wire_load_selection true Definition from report_lib: Selection Wire load name min area max area ------------------------------------------0.00 43478.00 5KGATES 43478.00 86956.00 10KGATES 86956.00 173913.00 20KGATES 173913.00 347826.00 40KGATES 347826.00 695652.00 80KGATES Environmental Attributes
Synopsys 31833-000-S16
Chip Synthesis Workshop
Wireload Model Mode
6-18
Specifies wire load model to use for nets that cross hierarchical boundaries. mode = enclosed TOP
mode = top TOP
SUB B1
SUB B2
WLM_SUB
B2
B1
WLM_TOP
less pessimistic mode Example: dc_shell-t> set_wire_load_mode enclosed
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Check Your Constraints
6-19
report_port -v a
check_design
report_design check_timing
write_script
report_clock
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Commands for Data Removal
6-20
You have several useful commands for libraries and designs: reset_design
Erases all attributes and constraints from design
remove_design -design
Removes designs from Design Compiler memory
remove_design -all
Removes designs and libraries from DC memory
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
List Commands
6-21
list_files
Lists all files in DC memory
list_designs
Lists all design names in DC memory
list_lib
Lists all libraries in DC memory
list_license
Lists all licenses uses by this shell
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Exercise: Describe the Environment
6-22
Create a “default” script file which can be applied to each subblock of a large ASIC, using the following specifications: Clock Speed
125 MHz
Input logic use 40% of clock period
3.2 ns
Output logic use 40% of clock period
3.2 ns
Operating at 85° °C and 1.6 volts
oc_85_16
Wireload Model
40KGATES
Cell driving inputs
inv1a0
Output have to drive 5 pF
5 pF Environmental Attributes
Synopsys 31833-000-S16
Chip Synthesis Workshop
Script File: Describe the Environment
6-23
reset_design # Timing
# Environment
Environmental Attributes Synopsys 31833-000-S16
.
Chip Synthesis Workshop
Lab 6: Introduction
6-24 Bring in the design
LAB
30 min unmapped
prgrm_attr.db
Apply Environmental Constraints
Constrain the design
Synthesize the design
mapped PC.db
Inspect the design
Save the design Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Appendix
6-25
Create an Operating Condition
Environmental Attributes Synopsys 31833-000-S16
Chip Synthesis Workshop
Create Your Own Operating Conditions
6-26
You can create your own operating conditions — without a Library Compiler license — if there are none that satisfy your design requirements extra.lib: library (“extra”) { operating_conditions("SLOW") { process : 1.75 ; temperature : 100; voltage : 1.60 ; tree_type : “worst_case_tree”;} }
After you create your own operating conditions, you must compile them to make them available for use by the Design Compiler
dc_shell-t> dc_shell-t> dc_shell-t> dc_shell-t>
read_lib extra.lib write_lib extra -output extra.db set link_library “* tech_library extra.db” set_operating_conditions SLOW -library extra Environmental Attributes
Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 2 DAY 2
Unit
7-1 Topic
5
Timing and Area
6
Environmental Attributes
7
Time and Load Budgeting
8
Timing Analysis
9
DC Tcl - Introduction
Lab
Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
7-2
After completing this unit, you should be able to:
Create a timing budget for a design block
Use the set_max_capacitance command to limit the input capacitance of a block
Budget the load on the output ports using the set_load command
Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
RTL Block Synthesis Write RTL HDL Code
Rewrite
No Yes Major Violations?
7-3
Simulate OK?
Yes No
Synthesize HDL Code To Gates
Constraints & Attributes Area & Timing Goals
Netlist Analysis
No
Met Constraints?
Yes Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Time Budgeting
7-4
What if you don’t know the delays on your inputs or the setup requirements of your outputs?
D Q FF1
CLK (100 MHz)
ckt Y
MY circuit
ckt X ?
?
N
D Q FF2
X
D Q FF3
S
?
?
D Q FF4
A: Create a Time Budget !
Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Time Budgeting (cont) circuit X D Q
?
7-5
MY circuit N
FF1
CLK (100 MHz)
D Q
X
FF2
40% of clock period
Better to budget conservatively than to compile with paths unconstrained! Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Time Budgeting Example
7-6
# A generic Time Budgeting script file # for MY_BLOCK create_clock -period 10 [get_ports CLK] set_dont_touch_network [get_clocks CLK] set_input_delay -max 6 -clock CLK [all_inputs] remove_input_delay [get_ports CLK] set_output_delay -max 6 -clock CLK [all_outputs] X_BLOCK X
10
D Q FF1
MY_BLOCK S
N
4
D Q FF2
Y_BLOCK X
10
D Q FF3
S
4
N
X
D Q FF4
10
DC still needs to consider delay of FF1 and setup of FF2 Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Time Budgeting Example (cont)
7-7
# Time Budgeting script file # for X_BLOCK and Y_BLOCK create_clock -period 10 [get_ports CLK] set_dont_touch_network [get_clocks CLK] set_input_delay -max 6 -clock CLK [all_inputs] remove_input_delay [get_ports CLK] set_output_delay -max 6 -clock CLK [all_outputs] X_BLOCK X
10
D Q FF1
MY_BLOCK S
4
N
D Q FF2
Y_BLOCK X
10
D Q FF3
S
N
4
X
D Q FF4
10
Would it be easier to specify a time budget if all outputs were registered? Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Load Budgeting
7-8
What if, prior to compiling, the cells driving your inputs, and the loads on your outputs are not known?
D Q FF1
Y_BLOCK
MY_BLOCK
X_BLOCK ?
N
D Q FF2
X
?
D Q FF3
S
?
?
D Q FF4
Z_BLOCK
A: Create a Load Budget! Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Load Budgeting (cont)
7-9
Whatif, if, prior prior to loads on on your outputs, Q: What to compiling, compiling,the the loads your outputs, andthe the cells cells driving areare notnot known? and drivingyour yourinputs inputs known?
A: Create a load budget
Assume a weak cell driving the inputs, to be conservative
Limit the input capacitance of each input port
Estimate the number of other major blocks your outputs may have to drive
How do we limit the input capacitance of an input port?
A: Place restrictive design rules on our input ports
Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Load Budget Example
7-10
Example Specification: Inputs
of any block shall present no more than the load of 10 “AND2” gates to their driving block
Outputs
of any blocks will only be allowed to connect to a maximum of 3 other blocks
Otherwise, output port will need to be replicated in code
1
10x
2 Assume a weak cell driving the inputs
Cinternal
3 10
Limit the load imposed 10x on driving block Cexternal
10x 10x
Keep track of how many other designers are using each output Timing and Load Budgeting
Synopsys 31833-000-S16
Chip Synthesis Workshop
Load Budget Example (cont)
7-11
current_design myblock link source timing_budget.tcl # Assume a weak driving buffer on the inputs set_driving_cell -lib_cell inv1a0 [all_inputs] remove_driving_cell [get_ports Clk] # Limit the input load set MAX_INPUT_LOAD [expr [load_of(tech_lib/and2a0/A) * 10]] set_max_capacitance $MAX_INPUT_LOAD [all_inputs] remove_attribute max_capacitance [get_ports Clk] # Model the max possible load on the outputs, assuming # outputs will only be tied to 3 subsequent blocks set_load [expr [$MAX_INPUT_LOAD * 3]] [all_outputs] Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Exercise: Describe the Environment
7-12
Create a “default” script file which can be applied to each subblock of a large ASIC, using the following specifications: Clock Speed
125 MHz
input / output ports use 40% of clock
3.2 ns
Operating at 85°°C and 1.6V
oc_85_45
Wireload Model
40KGATES
Cell driving inputs
inv1a0
max input capacitance at input ports
10x pin “A” of buf1a0
Output drive no more than 4 blocks
4 blocks
Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Script File: Describe the Environment
7-13
reset_design # Timing
# Environment
Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary of Describing Constraints
7-14
Timing and Area Goals: set_max_area create_clock
set_input_delay set_output_delay set_dont_touch_network
Environmental Attributes: set_driving_cell set_operating_conditions
set_load set_wire_load_model
Design Rules: set_max_capacitance
Reports: report_clock report_port -verbose report_design
write_script
Problems? reset_design
remove_design Timing and Load Budgeting
Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 7: Introduction
7-15 Bring in the design
LAB
45 min unmapped
PRGRM_CNT_TOP.db
Apply Timing and Load Budget
Constrain the design
Synthesize the design
unmapped
prgrm_attr.db
Inspect the design
Save the design Timing and Load Budgeting Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 2 DAY 2
Unit
8-1 Topic
5
Timing and Area
6
Environmental Attributes
7
Time and Load Budgeting
8
Timing Analysis
9
DC Tcl - Introduction
Lab
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
8-2
After completing this unit, you should be able to:
Generate a worst-case (maximum) timing report
Interpret a timing report to determine if you have met timing constraints
Use a timing report to diagnose timing constraint violations
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Does Your Design Meet Its Goals? Write RTL HDL Code
Rewrite
No Yes Major Violations?
8-3
Simulate OK?
Yes No
Synthesize HDL Code To Gates
Constraints & Attributes Area & Timing Goals
Netlist Analysis
No
Met Constraints?
Yes
Use Timing Analysis! Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Analysis: What Tool Do I Use?
8-4
Design Compiler has a built-in static timing analyzer called DesignTime Verilog
VHDL
Design Analyzer HDL Compiler
VHDL Compiler
Design Compiler DesignTime
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Static Timing Analysis Path 1 A
8-5
Path 2 D
Q
Z
CLK
Path 3
Static Timing Analysis can determine if a circuit meets timing constraints without dynamic simulation
This involves three main steps:
Design is broken down into sets of timing paths
The delay of each path is calculated
All path delays are checked to see if timing constraints have been met Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Paths in Design Compiler
8-6
MY_DESIGN A
D Q FF1 QB
D Q FF2 QB
Z
CLK
DesignTime breaks designs into sets of signal paths
Each path has a startpoint and an endpoint
Startpoints: Input ports Clock pins of Flip-Flops or registers
Endpoints: Output ports Data input pins of sequential devices
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Organizing Timing Paths into Groups
8-7
MY_DESIGN
CLK1 path1
A CLK1 CLK2
D Q FF2 QB
path2
D Q path3 FF3 QB
Z
path1
CLK2 path4
Timing Paths
DEFAULT
path2
path3 path4
Path Groups
Paths are grouped by the clocks controlling their endpoints
The default path group contains all paths not captured by a clock
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Path Exercise
8-8
How many timing paths do you see? How many path groups are there?
CLK_1 CLK_2 Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Path Exercise
8-9 12 timing paths 3 path groups
CLK_1 CLK_2
Clock Group 1 Clock Group 2
Default Group Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Schematic Converted to a Timing Graph
8-10
To calculate total delay, Design Time breaks each path into timing arcs
Each timing arc contributes either a net delay or cell delay
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Components of Static Timing Analysis
Look what’s under the hood of this thing!
8-11
What components are used in STA path delay calculations?
Cell delay models Linear and Nonlinear
Wire load models Pre-layout estimates of wire parasitics: How much R? How much C?
Interconnect models (R-C “tree type”) How are R and C distributed?
Design Time
Operating conditions How are the delays affected by process, voltage, and temperature?
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
How DesignTime Calculates Cell Delays
8-12
Cell delay model used by the technology library is chosen by the Vendor Cell delays are calculated using one of several cell delay models:
Nonlinear Delay Model
Linear Delay Model
Others…
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Nonlinear Delay Model
RCell
input transition intrinsic delay
RNet
8-13
CNet
Cpin
output response zero load delay
linear delay model
DSlope + DIntrinsic + RCell (CNet , CPin)
nonlinear delay model
f(TInput , RCell , CNet , CPin) + f(RNet, CNet , CPin)
cell delay from 2D table
time-of-flight WLM Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Cell Delay: Nonlinear Delay Models
In the two-dimensional NLDM, output loading and input transition affect the cell delay and output transition
Output transition becomes the next cell’s input transition
There are typically two NLDM tables per cell Example: Output load = 2 fF Input transition = 10 units 3 ........
Output Load (fF)
0
1
2
0
2
3
4
5
10
3
4.5
6
7
20
5
8
10.7
13
Cell Delay = 6 ps
0
1
2
0
1
10
18
10
2
13
25
20
4
16
39
........
........
Cell Delay (ps)
Input Transition
Output Load (fF)
Input Transition
8-14
........
Output Transition (vendor units)
Output Transition = 25 units Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Wire Delay Calculations and Topology
8-15
WLM determines the amount of R and C for a net Tree-type determines R and C distribution for timing calculations • Interconnect delay (DC) is measured from state change at driver pin to state change at each receiving cell’s input pin (same in every branch!) best_case_tree Optimistic
balanced_tree
Load adjacent to driver (net resistance is zero) DC = 0 Each load pin shares equal portion of net’s R and C R/2 DC = ( Rnet / N ) x ( Cnet / N + Cpin ) where N= fanout
C/2
Default
R/2 C/2
worst_case_tree Pessimistic
Assume a lumped RC load DC = Rnet x ( Cnet + Cpins )
R
C Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Operating Conditions
8-16
STA scales each cell and net delay based on process, voltage, and temperature (PVT) variations
Tree type indicates which interconnect model to use
Operating Conditions: Name Library Process Temp Volt Interconnect --------------------------------------------------------------------slow_125_1.62 ssc_core_slow 1.00 125.00 1.62 balanced_tree slow_125_1.62_WCT ssc_core_slow 1.00 125.00 1.62 worst_case_tree
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Edge Sensitivity in Path Delays
8-17
What is the longest path for the circuit below? What is the shortest? Can’t we just add the longest delays and add the shortest delays? library: pin(Z) intrinsic_rise : 1.2; intrinsic_fall : 0.5;
library: pin(Z) intrinsic_rise : 1.5; intrinsic_fall : 0.3;
There is an “edge sensitivity” (called unateness) in a cell’s timing arc
DesignTime keeps track of unateness in each timing path Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Setup Relationship Between Flip-Flops
8-18
The default behavior of Design Compiler is to assume that all data must go from launch to capture edge in one clock cycle. The path between FF1 and FF2 has a max delay constraint of TCLK - FF2libSetup FF1
FF2
Launch Edge FF1
FF2 Default setup check
Capture Edge Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
DesignTime Timing Reports
8-19
Users will typically access DesignTime via the report_timing command
The report_timing command The design is broken down into individual timing paths Each timing path is timed out twice;
once for a rising edge input, and
once with a falling edge input
The critical path (worst violator) for each clock group is found A timing report for each clock group is echoed to the screen
A DesignTime timing report has four major sections Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report: Path Information Section
8-20
**************************************** Report : timing -path full -delay max -max_paths 1 Design : TT Version: 2000.05 Date : Tue Aug 29 18:22:38 2000 **************************************** Operating Conditions: slow_125_1.62 Wire Load Model Mode: enclosed
Library: ssc_core_slow
Startpoint: data1 (input port clocked by clk) Endpoint: u4 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library -----------------------------------------------TT 5KGATES ssc_core_slow Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report: Path Delay Section Individual Contribution to Path Delay
8-21
Running Total of the Path Delay
Point Incr Path --------------------------------------------clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 1.00 1.00 data1 (in) 0.00 1.00 u2/Y (inv1a1) 0.12 1.12 u12/Y (or2a1) 0.26 1.38 u23/Y (mx2d2) 0.23 1.61 u4/D (fdef1a1) 0.00 1.61 data arrival time 1.61
Signal Transition f f r r f f
Total Delay
Net & Cell Delays 0.12
data1
0.0001
Time-of-flight
D U2
Y U12
U23
U4 Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report: Path Required Section
8-22
Clock Edge Point Incr Path ----------------------------------------------clock clk (rise edge) 5.00 5.00 clock network delay (ideal) 0.00 5.00 U4/CLK (fdef1a1) 0.00 5.00 library setup time -0.19 4.81 data required time 4.81
From the Library
Data must be valid by this time
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report: Summary Section
8-23
-----------------------------------------------data required time 4.81 data arrival time -1.61 -----------------------------------------------slack (MET) 3.20
Either (MET) or (VIOLATED)
Timing margin (slack): negative indicates constraint violation
CLK Data Arrival 0
1.61
Data Required
Slack
4.81
5
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report: Options
8-24
report_timing [ [ [ [ [ [ [
-delay max/min ] -to name_list ] -from name_list ] -through name_list ] -input_pins ] -max_paths path_count ] -nets ]
...
Remember, the default behavior of report_timing is to report the path with the worst slack within each path group
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Analysis: Diagnose Synthesis Results
8-25
Spot the whales in the timing report: Where are they? What are they? And why? Point clock (input port clock) (rise edge) input external delay addr31 (in) u_proc/address31 (proc) u_proc/u_dcl/int_add[7] (dcl) u_proc/u_dcl/U159/Q (NAND3H) u_proc/u_dcl/U160/Q (NOR3F) u_proc/u_dcl/U186/Q (AND3F) u_proc/u_dcl/U86/Q (INVF) u_proc/u_dcl/U135/Q (NOR3B) u_proc/u_dcl/U136/Q (INVF) u_proc/u_dcl/U100/Q (NBF) u_proc/u_dcl/U95/Q (BF) u_proc/u_dcl/U96/Q (BF) u_proc/u_dcl/U94/Q (NBF) u_proc/u_dcl/U93/Q (NBF) u_proc/u_dcl/ctl_rs_N (dcl) u_proc/u_ctl/ctl_rs_N (ctl) u_proc/u_ctl/U126/Q (NOR3B) u_proc/u_ctl/U120/Q (NAND2B) u_proc/u_ctl/U99/Q (NBF) u_proc/u_ctl/U122/Q (OR2B) u_proc/u_ctl/read_int_N (ctl) u_proc/int_cs (proc) u_int/readN (int) u_int/U39/Q (NBF) u_int/U17/Q (INVB) u_int/U16/Q (AOI21F) u_int/U60/Q (AOI22B) u_int/U68/Q (INVB) u_int/int_flop_0/D (DFF) data arrival time
Incr 0.00 22.40 0.00 1.08 0.00 0.62 0.75 1.33 0.64 1.36 0.49 0.87 0.44 0.45 0.84 0.94 0.00 0.00 1.78 1.07 0.88 10.72 0.00 0.00 0.00 1.29 1.76 2.49 1.43 1.81 0.00
Path 0.00 22.40 22.40 23.48 23.48 24.10 24.85 26.18 26.82 28.17 28.67 29.54 29.98 30.43 31.27 32.21 32.21 32.21 33.98 35.06 35.94 46.67 46.67 46.67 46.67 47.95 49.71 52.20 53.63 55.44 55.44 55.44
f f f f r f f r f r r f r r r r r f r r r r r r r f r f r r
Rather late arrival for a 30 ns period! Six buffers back to back?!
11 ns delay for an OR gate is not good
Four hierarchical partitions
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report Exercise dc_shell> dc_shell> report_timing report_timing **************************************** **************************************** Report Report :: timing timing -path -path full full -delay -delay max max -max_paths -max_paths 11 Design Design :: AM2910 AM2910 Version: 1998.08 Version: 1998.08 Date Date :: Thu Thu Feb Feb 11 11 10:53:32 10:53:32 1999 1999 **************************************** ****************************************
8-26 What Whattype typeof ofstartpoint startpointdoes doesthis this path pathhave have(input (inputport portor orregister? register?
What Whattype typeof ofendpoint endpointdoes doesthis this path pathhave? have?
Operating Operating Conditions: Conditions: WCCOM WCCOM Library: lsi10k Library: lsi10k Wire Wire Loading Loading Model Model Mode: Mode: top top Design Wire Library Design Wire Loading Loading Model Model Library ----------------------------------------------------------------------------------------------AM2910 30x30 lsi10k AM2910 30x30 lsi10k Startpoint: Startpoint: U3/OUTPUT_reg[12] U3/OUTPUT_reg[12] (rising (rising edge-triggered edge-triggered Flip-Flop Flip-Flop clocked clocked by by CLOCK) CLOCK) Endpoint: U2/OUTPUT_reg[2] Endpoint: U2/OUTPUT_reg[2] (rising (rising edge-triggered edge-triggered Flip-Flop Flip-Flop clocked clocked by by CLOCK) CLOCK) Path Group: CLOCK Path Group: CLOCK Path Path Type: Type: max max Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report Exercise (cont) Point Incr Path Point Incr Path --------------------------------------------------------------------------------------------------clock 0.00 0.00 clock CLOCK CLOCK (rise (rise edge) edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock network delay (ideal) 0.00 0.00 U3/OUTPUT_reg[12]/CP (FD1) 0.00 0.00 U3/OUTPUT_reg[12]/CP (FD1) 0.00 0.00 rr U3/OUTPUT_reg[12]/Q 3.97 3.97 U3/OUTPUT_reg[12]/Q (FD1) (FD1) 3.97 3.97 rr .. .. .. .. .. .. .. .. .. .. U3/U148/Z 2.90 17.25 U3/U148/Z (IV) (IV) 2.90 17.25 rr U3/ZERO 0.00 17.25 U3/ZERO (REGCNT) (REGCNT) 0.00 17.25 rr U5/REGCNT_ZERO 0.00 17.25 U5/REGCNT_ZERO (CONTROL) (CONTROL) 0.00 17.25 rr U5/U230/Z 0.64 17.88 U5/U230/Z (ND2) (ND2) 0.64 17.88 ff U5/U232/Z 2.77 19.65 U5/U232/Z (XOR2) (XOR2) 2.77 19.65 ff U5/U236/Z 1.75 21.15 U5/U236/Z (IVA) (IVA) 1.75 21.15 rr U5/U193/Z 1.38 22.53 U5/U193/Z (ND4) (ND4) 1.38 22.53 ff U5/Y_CONTROL[1] 0.00 22.53 U5/Y_CONTROL[1] (CONTROL) (CONTROL) 0.00 22.53 ff U4/OPERATION[1] 0.00 22.53 U4/OPERATION[1] (Y) (Y) 0.00 22.53 ff U4/core/MUXOUT[1] 7.24 29.77 U4/core/MUXOUT[1] (Y_core) (Y_core) 7.24 29.77 rr U4/MUXOUT[1] 0.00 29.77 U4/MUXOUT[1] (Y) (Y) 0.00 29.77 rr U2/DATA[12] 0.00 29.77 U2/DATA[12] (UPC) (UPC) 0.00 29.77 rr .. .. .. .. .. .. .. .. .. .. U2/U62/Z 1.92 38.90 U2/U62/Z (AN2) (AN2) 1.92 38.90 ff U2/OUTPUT_reg[2]/D 0.01 38.91 U2/OUTPUT_reg[2]/D (FD1) (FD1) 0.01 38.91 ff data 38.91 data arrival arrival time time 38.91
8-27 How Howmany manylevels levelsof of hierarchy hierarchydoes doesthis this path pathtraverse? traverse?
Do Doany anycells cellsappear appear to tohave haveaarelatively relatively large largedelay? delay?
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Report Exercise (cont)
8-28
Does Doesthe thepath pathmeet meettiming? timing? What Whatis isthe thepercentage percentageviolation? violation?
clock 30.00 30.00 clock CLOCK CLOCK (rise (rise edge) edge) 30.00 30.00 clock network delay (ideal) 0.00 30.00 clock network delay (ideal) 0.00 30.00 clock uncertainty 0.00 30.00 clock uncertainty 0.00 30.00 U2/OUTPUT_reg[2]/CP (FD1) 30.00 U2/OUTPUT_reg[2]/CP (FD1) 30.00 rr library -0.80 29.20 library setup setup time time -0.80 29.20 data required time 29.20 data required time 29.20 ----------------------------------------------------------------------------------------------------------------------------data 29.20 data required required time time 29.20 data arrival time -38.91 data arrival time -38.91 ----------------------------------------------------------------------------------------------------------------------------slack -9.71 slack (VIOLATED) (VIOLATED) -9.71
Timing Analysis Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary
8-29
Use report_timing to get detailed information about the critical path:
clock period
slack
operating condition used
wire load model used
network delay
skew
setup/hold times
partitions
net delay
net names Timing Analysis
Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 2 DAY 2
Unit
9-1 Topic
5
Timing and Area
6
Environmental Attributes
7
Time and Load Budgeting
8
Timing Analysis
9
DC Tcl - Introduction
Lab
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
9-2
After completing this unit, you should be able to:
Use online help to determine the syntax of a command
Define data types supported by DC-Tcl
Use DC-Tcl to assign a value to variables
Write a simple DC-Tcl script to automate common DC tasks, including:
Reading in Designs
Constraining a Design
Compiling a Design
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Tired of Working? Man, I'm tired of sitting at this terminal.
9-3 DC-Tcl script!!
I sure wish I could have my compile done automatically.
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
What is Tcl?
9-4
Tcl = Tool Command Language
An "open", industry-standard language
Developed at UCA Berkeley
Offers many powerful “C-shell” style features
References:
Tcl and the Tk Toolkit, John K. Ousterhout
Practical Programming in Tcl and Tk, Brent B. Welch
Visual Tcl, David Young
www.scriptics.com
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Why Tcl?
Tcl is becoming an industry standard for tools
Tcl is more powerful than dc_shell
9-5
much more extensive online help lists AND arrays are supported user-defined procedures case construct, string manipulation and comparison, file manipulation more
Synopsys tools that use Tcl for consistency:
Design Compiler
Formality
PrimeTime
Physical Compiler
Chip Architect, etc…
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Converting from dc_shell to dc_shell-t
9-6
For users who wish to migrate from "old" dc_shell to DC-Tcl, an automated program has been written UNIX% dc-transcript
my_script.scr
my_script.tcl
Will convert most commands in existing scripts to Tcl
Only goes from DCSH to DC-Tcl
Called from the UNIX prompt
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Executing DC-Tcl Script
9-7
There are two ways to execute commands in DC-Tcl:
Interactively from DC-Tcl: dc_shell-t> dc_shell-t> source source my.tcl my.tcl
Execute from UNIX: UNIX% UNIX% dc_shell-t dc_shell-t -f -f my.tcl my.tcl UNIX% UNIX% dc_shell-t dc_shell-t -f -f my.tcl my.tcl >> my.log my.log UNIX% UNIX% dc_shell-t dc_shell-t -f -f my.tcl my.tcl || tee tee my.log my.log
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Getting Help
9-8
To Get a Basic Summary of all DC-Tcl Commands dc_shell-t> dc_shell-t> help help Procedures: Procedures: Builtins: Builtins: after, after, alias, alias, append, append, apropos, apropos, array, array, break, break, catch, catch, cd, cd, clock, clock, close, close, concat, concat, continue, continue, create_command_group, create_command_group, define_proc_attributes, define_proc_attributes, echo, echo, eof, eof, error, error, error_info, error_info, eval, eval, exec, exec, exit, exit, expr, expr, fblocked, fblocked, fconfigure, fconfigure, .. .. ..
Default Default Command Command Group: Group: add_module, add_module, add_to_collection, add_to_collection, all_clocks, all_clocks, all_cluster_cells, all_cluster_cells, all_clusters, all_clusters, all_connected, all_connected, all_critical_cells, all_critical_cells, all_critical_pins, all_critical_pins, all_designs, all_designs, all_inputs, all_inputs, all_outputs, all_outputs, all_registers, all_registers, analyze, analyze, balance_buffer, balance_buffer, balance_registers, balance_registers, bc_check_design, bc_check_design, .. .. .. DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Getting Help (cont)
9-9
Use a Wildcard to Find a Command dc_shell-t> dc_shell-t> help help *clock *clock clock ## Builtin clock Builtin create_clock ## create_clock create_clock create_clock create_test_clock ## create_test_clock create_test_clock create_test_clock remove_clock ## remove_clock remove_clock remove_clock remove_propagated_clock remove_propagated_clock ## remove_propagated_clock remove_propagated_clock report_clock ## report_clock report_clock report_clock set_propagated_clock ## set_propagated_clock set_propagated_clock set_propagated_clock
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
More Help!
9-10
Use help -verbose for command syntax information: dc_shell-t> help -verbose set_input_delay set_input_delay [-clock clock_name] [-clock_fall] [-level_sensitive] [-rise] [-fall] [-max] [-min] [-add_delay] delay_value port_pin_list
# set_input_delay (relative clock) (delay is relative to falling edge of clock) (delay is from level-sensitive latch) (specifies rising delay) (specifies falling delay) (specifies maximum delay) (specifies minimum delay) (don't remove existing input delay) (path delay) (list of ports and/or pins)
Use Useman mancommand command(from (fromeither eitherthe theUNIX UNIXprompt promptor or dc_shell-t) dc_shell-t)for forthe theentire entireUNIX UNIXmanpage manpageon onaacommand command DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Comments in DC-Tcl
9-11
## Comments Comments in in Tcl Tcl are are line-oriented line-oriented ## If If you you wish wish to to comment comment on on the the same same line, line, be be sure sure to to use use ## aa semicolon semicolon before before the the comment: comment: set set header_str header_str “Output “Output Header”; Header”; ## Same Same line line comment comment
This semicolon is required!
Comment a line in a DC-Tcl script using the ‘#’ character
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Nesting Commands and Quoting
9-12
Commands are nested using square brackets: dc_shell-t> dc_shell-t> set_output_delay set_output_delay 55 -clock -clock CLK CLK [all_outputs] [all_outputs]
Two ways of quoting text:
weak quoting with “ “ dc_shell-t> dc_shell-t> set set aa 55 dc_shell-t> dc_shell-t> set set ss “temp “temp == data[$a]” data[$a]” temp temp == data[5] data[5]
rigid quoting with { } dc_shell-t> dc_shell-t> set set ss {temp {temp == data[$a]} data[$a]} temp temp == data[$a] data[$a] DC Tcl - Introduction
Synopsys 31833-000-S16
Chip Synthesis Workshop
Using Wildcards
9-13
Tcl supports two wildcard characters:
? will match exactly one character (PrimeTime only)
* will match zero to ‘n’ characters
Examples: dc_shell-t> help create* dc_shell-t> set_input_delay 5 -clock CLK [get_ports BUS*]
\
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Tcl Data Types
9-14
DC-Tcl supports the following data types:
Real
Integer
String
Lists
Collections
Tcl also supports arrays containing one or more of these data types
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Using Variables
9-15
Variables are created and assigned using the Tcl set command dc_shell-t> dc_shell-t> set set my_var my_var 10 10 To reference a variable, it must be preceded with a “$” dc_shell-t> dc_shell-t> set set my_New_Var my_New_Var $my_var $my_var To print variables dc_shell-t> dc_shell-t> echo echo $my_var $my_var To remove variables dc_shell-t> dc_shell-t> unset unset my_var my_var DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Using Variables: Exercise
9-16
What will be the result of executing the following commands? dc_shell-t> dc_shell-t> set set clock_period clock_period 10 10 10 10 dc_shell-t> dc_shell-t> echo echo clock_period clock_period ______________________ ______________________
dc_shell-t> dc_shell-t> echo echo “clock “clock period period == ““ $clock_period $clock_period ______________________ ______________________
dc_shell-t> dc_shell-t> echo echo “Frequency “Frequency == ““ 1/$clock_period 1/$clock_period ______________________ ______________________
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Arithmetic Expressions
9-17
Tcl is string-oriented
To evaluate arithmetic expressions, use the expr command
dc_shell-t> dc_shell-t> set set period period 10.0 10.0 10.0 10.0
necessary whitespace
dc_shell-t> dc_shell-t> set set freq freq [expr [expr (1 (1 // $period)] $period)] 0.1 0.1 dc_shell-t> dc_shell-t> echo echo “Freq “Freq =“ =“ [expr [expr $freq $freq ** 1000] 1000] “MHz” “MHz” Freq Freq == 100.0 100.0 MHz MHz dc_shell-t> dc_shell-t> set_load set_load [expr [expr [load_of [load_of cba_core/and2a0/A] cba_core/and2a0/A] ** 5] 5] \\ [all_outputs] [all_outputs]
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Using Lists in dc_shell-t
9-18
Lists are a component of Tcl
A list is one string, containing items separated by white space dc_shell-t> dc_shell-t> set set L1 L1 {el1 {el1 el2 el2 el3} el3} el1 el1 el2 el2 el3 el3 dc_shell-t> dc_shell-t> echo echo $L1 $L1 el1 el2 el3 el1 el2 el3 dc_shell-t> dc_shell-t> set set Num_of_List_Elements Num_of_List_Elements [llength [llength $L1] $L1] 33 dc_shell-t> dc_shell-t> set set link_library link_library {*} {*} ** dc_shell-t> dc_shell-t> lappend lappend link_library link_library tc6a.db tc6a.db opcon.db opcon.db ** tc6a.db tc6a.db opcon.db opcon.db dc_shell-t> dc_shell-t> echo echo $link_library $link_library ** tc6a.db tc6a.db opcon.db opcon.db DC Tcl - Introduction
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Chip Synthesis Workshop
Definitions: Objects and Attributes
Recall that designs consist of objects
designs, cells, references, ports, pins, clocks, and nets
In order to keep track of circuit functionality and timing, DC attaches many attributes to each of these objects
9-19
ports can have the following attributes: direction
driving_cell
max_capacitance
others. . .
designs can have the following attributes: area
operating_conditions_max
max_area
others…
Standard Tcl data formats (lists, strings) are not adequate to keep track of circuit elements and their attributes! DC Tcl - Introduction
Synopsys 31833-000-S16
Chip Synthesis Workshop
Definitions: Collection & Collection Handle
9-20
In order to keep track of circuit objects and their attributes, DC-Tcl contains an extension to standard Tcl -- collections
Collection:
A set of design objects which DC internally stores and refers to by a name, the collection handle
Collections are created by a get_ or all_ commands
Collection handle:
A handle, or pointer, to a collection
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Creating Collections
9-21
Here is a partial list of DC-Tcl commands that create collections: get_cells get_cells get_clocks get_clocks get_designs get_designs get_libs get_libs get_nets get_nets get_pins get_pins get_ports get_ports
## Create Create aa collection collection of of cells cells ## Create Create aa collection collection of of clocks clocks ## Create Create aa collection collection of of designs designs ## Create a collection of libraries Create a collection of libraries ## Create Create aa collection collection of of nets nets ## Create Create aa collection collection of of pins pins ## Create Create aa collection collection of of ports ports
all_clocks all_clocks all_designs all_designs all_inputs all_inputs all_outputs all_outputs all_registers all_registers
## Create Create aa collection collection of of all_clocks all_clocks ## Create Create aa collection collection of of all_designs all_designs ## Create Create aa collection collection of of all_inputs all_inputs ## Create Create aa collection collection of of all_outputs all_outputs ## Create Create aa collection collection of of all_registers all_registers
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Collections Are Referenced by a Handle 9-22 dc_shell-t> dc_shell-t> set set mylist mylist {a {a bb hello hello world} world} aa bb hello hello world world dc_shell-t> dc_shell-t> llength llength $mylist $mylist 44 dc_shell-t> dc_shell-t> set set foo foo [all_inputs] [all_inputs] {"Clk", {"Clk", "Reset", "Reset", "Crnt_Instrn[31]", "Crnt_Instrn[31]", ... ... "Crnt_Instrn[0]"} "Crnt_Instrn[0]"} dc_shell-t> dc_shell-t> llength llength $foo $foo 11 dc_shell-t> dc_shell-t> echo echo $foo $foo Collection Handle _sel5 _sel5 dc_shell-t> dc_shell-t> sizeof_collection sizeof_collection $foo $foo 34 34 dc_shell-t> dc_shell-t> query_objects query_objects $foo $foo {"Clk", {"Clk", "Reset", "Reset", "Crnt_Instrn[31]", "Crnt_Instrn[31]", ... ... "Crnt_Instrn[0]"} "Crnt_Instrn[0]"}
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Manipulating Collections
9-23
dc_shell-t> dc_shell-t> help help *collection* *collection* add_to_collection add_to_collection compare_collections compare_collections copy_collection copy_collection filter_collection filter_collection
## Add Add object(s) object(s) ## compares compares two two collections collections ## Make Make aa copy copy of of aa collection collection ## Filter Filter aa collection, collection, resulting resulting in in aa new new collection collection foreach_in_collection foreach_in_collection ## Iterate Iterate over over aa collection collection index_collection ## Extract index_collection Extract object object from from collection collection remove_from_collection remove_from_collection ## Remove Remove object(s) object(s) from from aa collection collection sizeof_collection ## Number sizeof_collection Number of of objects objects in in aa collection collection sort_collection ## Create sort_collection Create aa sorted sorted copy copy of of aa collection collection
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Manipulating Collections (cont)
Add objects to a collection using add_to_collection
Remove objects from a collection using remove_from_collection
9-24
dc_shell-t> dc_shell-t> set set pci_ports pci_ports [get_ports [get_ports “DATA*”] “DATA*”] dc_shell-t> dc_shell-t> set set pci_ports pci_ports [add_to_collection [add_to_collection $pci_ports $pci_ports \\ [get_ports [get_ports “CTRL*”]] “CTRL*”]] dc_shell-t> \\ dc_shell-t> set set all_inputs_except_clk all_inputs_except_clk [remove_from_collection [remove_from_collection [all_inputs] [all_inputs] [get_ports [get_ports “CLK”]] “CLK”]] DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Collection Usage: Example
9-25
## Constrain Constrain aa design design for for timing, timing, using using aa time time budget budget set set CLK_PER CLK_PER set time_budget set time_budget
10.0; 10.0; ## clock clock period period (ns) (ns) 40.0; # percentage of 40.0; # percentage of clock clock period period ## allowed for input/output allowed for input/output logic logic
## calculate calculate intermediate intermediate variables variables set set IO_DELAY IO_DELAY [expr [expr (( (1-$time_budget/100.0) (1-$time_budget/100.0) ** $CLK_PER)] $CLK_PER)] set set all_except_clk all_except_clk [remove_from_collection [remove_from_collection \\ [all_inputs] [all_inputs] [get_ports [get_ports CLK] CLK] ]] ## constrain constrain the the design design for for timing timing create_clock -period $CLK_PER create_clock -period $CLK_PER -name -name MY_CLOCK MY_CLOCK [get_ports [get_ports Clk] Clk] set_input_delay set_input_delay $IO_DELAY $IO_DELAY -max -max -clock -clock MY_CLOCK MY_CLOCK \\ $all_except_clk $all_except_clk set_output_delay set_output_delay $IO_DELAY $IO_DELAY -max -max -clock -clock MY_CLOCK MY_CLOCK \\ [all_outputs] [all_outputs] DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Filtering Collections
9-26
Use the filter_collection command 1
filter_collection filter_collection [get_cells] [get_cells] “ref_name “ref_name == == AN2” AN2” 2
filter_collection filter_collection [get_cells] [get_cells] “is_mapped “is_mapped == == true” true”
Use -filter option 3
get_cells get_cells -filter -filter “@dont_touch “@dont_touch == == true” true” 4
set set fastclks fastclks [get_clocks [get_clocks -filter -filter “@period “@period << 10”] 10”] DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Running dc_shell-t Interactively
9-27
Name common UNIX commands can you run in dc_shell-t? dc_shell-t> dc_shell-t> ___ ___ ;; ___ ___ ;; ___ ___
What are the commands for these tasks? Show Showthe thehistory historyof ofcommands commandsentered: entered: dc_shell-t> ___ dc_shell-t> ___ Repeat Repeatlast lastcommand: command: dc_shell-t> dc_shell-t> ___ ___ Execute Executecommand commandno. no.77from fromthe thehistory historylist: list: dc_shell-t> dc_shell-t> ___ ___ Execute Executethe thelast lastreport_ report_command: command: dc_shell-t> dc_shell-t> ___ ___ DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 9: Introduction LAB
9-28
60 min
Create two generic Tcl scripts unmapped PRGRM_CNT_TOP.db
constraints.tcl create_clock set_input_delay ...
runit.tcl read_db ... source constraints.tcl compile report_constraint write . . .
DC Tcl - Introduction Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 3 DAY 3
Unit
10-1
Topic
10
Timing Revisited
11
Optimization
12
Compile Strategies
13
Compiling a Hierarchical Design
14
DC Tcl - Procedures
Lab
Timing Revisited Synopsys 31833-000-S16
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Unit Objectives
10-2
After completing this unit, you should be able to:
Model non-ideal clock effects
Create and use virtual clocks
Constrain a multiple clock design (synchronous clocks)
Constrain a multiple clock design (asynchronous clocks)
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
RTL Block Synthesis Write RTL HDL Code
Rewrite
No Yes Major Violations?
10-3
Simulate OK?
Yes No
Synthesize HDL Code To Gates
Constraints & Attributes Area & Timing Goals
Netlist Analysis
No
Met Constraints?
Yes Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Recall Timing Constraints From Unit 5
10-4
TO_BE_SYNTHESIZED D Q FF1 QB
M
N
D Q FF2 QB
X
D Q FF3 QB
T
S
D Q FF4 QB
Clk
set_output_delay
set_input_delay create_clock ( period )
create_clock ( period )
create_clock ( period )
Method: 1. Define the clock 2. Define the I/O timing relative to the clock Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Goals: Part Two
10-5
Modeling Real-Life Clocks
Multiple Clocks - Synchronous
Multiple Clocks - Asynchronous
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Modeling Clock Trees
10-6
Design Compiler is NOT used for synthesis of the clock tree. Clock tree synthesis is usually done by the vendor, based on physical placement data.
D_In D_In
D Q FF1
D Q FF2
D Q FF1 D Q FF2
CLK CLK
Logical Circuit
Post-Layout Circuit
What design considerations need to be taken into account by the synthesis tool, prior to layout? Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Modeling Uncertainty on Clock Edges D_In
10-7
D Q FF1 D Q FF2
CLK TU
Post-Layout Circuit
To account for varying delays between the clock network branches (commonly called clock skew): set_clock_uncertainty TU [get_clocks CLK] placed on clock objects
Default clock skew is zero Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
set_clock_uncertainty and Setup Timing 10-8 Example: create_clock -period 10 [get_ports CLK] set_clock_uncertainty 0.5 [get_clocks CLK] D Q FF1
X
D Q FF2
FF1 Data Launch Edge (No uncertainty!)
FF2 setup check at: 10 - 0.5 - 0.2 = 9.3
/ /
0
5 Max allowable delay for block “X”
9.3 9.5 10 Assume lib setup = 0.2ns Timing Revisited
Synopsys 31833-000-S16
Chip Synthesis Workshop
Model Source Latency
10-9
Source latency is the propagation time from the actual clock origin to the clock definition point in the design
Use for either ideal or propagated clocks
create_clock -per 10 [get_ports CLK] set_clock_latency -source 3 CLK set_propagated_clock CLK YOUR_DESIGN Network Latency CLK 3ns
1ns
D
Q
CLK
Origin of Clock Source Latency Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Pre/Post Layout Clock
10-10
ideal clock
uncertainty
transition
latency [ jitter 0.2 + skew 0.4 ] 抖动 ＋ 时滞
pre-layout create_clock -p 30 -n MCLK Clk set_clock_uncertainty 0.6 MCLK set_clock_latency -source 4 MCLK
post-layout set_propagated_clock MCLK
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Clocks: Synchronous
10-11
Modeling Real-Life Clocks
Multiple Clocks - Synchronous
Multiple Clocks - Asynchronous
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Synchronous Multiple Clock Designs
10-12
TO_BE_SYNTHESIZED CLKD
CLKA
N
D Q FF2 QB
X
D Q FF3 QB
S
CLKC
CLKB
CLKE
What is different? A: Multiple clock sources All derived from the same clock source Some clocks do not have a corresponding clock port on our design Multiple constraints on a single port What do we do now? Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Answer: Use Virtual Clocks!
10-13
What are virtual clocks? A: Clocks in the environment of the design to be synthesized that:
Are defined clock objects within Design Compiler’s memory Do not clock any sequential devices within the current_design
Serve as references for input or output delays
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Creating a Virtual Clock
10-14
How do I create a virtual clock? A: It’s the same as defining a clock, but don’t specify a clock pin or port You must name your virtual clock, since there’s no clock port for the virtual clock Example: create_clock Must be named
-name vTEMP_CLK
-period 20
No source pin or port!
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Goals for Multiple Clock Designs ÷9 ÷6 ÷4 ÷3
300 MHz
10-15
CLKA CLKC CLKD CLKE
TO_BE_SYNTHESIZED
N
CLKA (33 Mhz)
D Q FF2
CLKC (50 Mhz)
X
D
Q
S
CLKD (75 Mhz)
FF3
CLKE (100 Mhz)
Method is the same as that for single clock designs: 1. Define the clock(s), using virtual clocks if necessary 2. Specify I/O delays relative to the clock(s)
Design Compiler will determine which clock imposes the most restrictive constraint on the design Timing Revisited
Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Clock Input Delay: Example
10-16
create_clock create_clock -period -period 30 30 -name -name CLKA CLKA create_clock create_clock -period -period 20 20 [get_ports [get_ports CLKC] CLKC] set_dont_touch_network set_dont_touch_network [get_clocks [get_clocks CLKC] CLKC] set_input_delay set_input_delay 5.5 5.5 -clock -clock CLKA CLKA -max -max [get_ports [get_ports IN1] IN1]
5.5 ns TO_BE_SYNTHESIZED
IN1 300 MHz
CLKA ÷9 ÷6
0.5 ns CLK-Q
5 ns
N CLKC
tN
CLKC
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Clock Input Delay Example -Waveforms 300 MHz
10-17 ÷6
CLKC
÷9
CLKA
CLKA
CLKC 0
10
20
30
40
50
60
10 ns
For the example shown, input logic cloud of TO_BE_SYNTHESIZED must meet:
tN < 10 - 5.5 - tsetup Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Clock Output Delay: Example
10-18
create_clock -period [expr (1.0/75*1000)] -name CLKD create_clock -period 10
-name CLKE
set_dont_touch_network
÷4 ÷6 ÷3
300 MHz
create_clock -period 20 [get_ports CLKC] [get_clocks CLKC]
CLKD CLKC CLKE
set_output_delay -max 2.5 -clock CLKD [get_ports OUT1] set_output_delay -max 4.5 -clock CLKE -add_delay [get_ports OUT1] 2.5 ns TO_BE_SYNTHESIZED
2ns
0.5 ns SETUP
OUT1
S
CLKD
tS CLKC
4 ns
0.5 ns SETUP
CLKE 4.5 ns Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Clock Output Delay Example -Waveforms
300 MHz
10-19 ÷4 ÷6 ÷3
CLKD CLKC CLKE
6.7
CLKD CLKC CLKE 10
0
20
30
40
10
For the example shown, output logic cloud of TO_BE_SYNTHESIZED must meet: tS < 10 - 4.5
AND
tS < 6.7 - 2.5 Timing Revisited
Synopsys 31833-000-S16
Chip Synthesis Workshop
Hints for Multiple Clock Designs
10-20
By definition, all clocks used with Design Compiler are synchronous
You can not create asynchronous clocks with the create_clock command.
DC will determine every possible data launch/data capture time, and synthesize to the most conservative
DC builds a common base period for all clocks
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multiple Clocks: Asynchronous
10-21
Modeling Real-Life Clocks
Multiple Clocks - Synchronous
Multiple Clocks - Asynchronous
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Asynchronous Multiple Clock Designs
10-22
TO_BE_SYNTHESIZED CLKD
CLKA
CLKB
N
D Q FF2 QB
X
D Q FF3 QB
S
CLKC CLKE
What is different? A: Multiple clock sources & sinks All Asynchronous Clocks do not have a corresponding clock port on our design What do we do now? Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesizing with Asynchronous Clocks 10-23
It is the user’s responsibility to account for the metastability Instantiate double-clocking, metastable-hard Flip-Flops dual-port FIFO etc..
The user must then disable timing-based synthesis on any path which crosses an asynchronous boundary
This will prevent DC from wasting time trying to get the asynchronous path to “meet timing”
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
The set_false_path command
10-24
How do we disable timing-based synthesis for asynchronous paths? A: Use the set_false_path command
A false path is a path for which we wish to ignore timing constraints
set_false_path can be used to disable timingbased synthesis on a path-by-path basis
Useful for:
Constraining asynchronous paths
Constraining logically false paths
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
set_false_path: Example
10-25
TOP Des_A
Des_B
CLKA (100 Mhz from OSC1)
N
D
Q
D Q
X
D Q
CLKB (100 Mhz from OSC2)
current_design TOP /* Make sure register-register paths meet timing */ create_clock -period 10 [get_ports CLKA] create_clock -period 10 [get_ports CLKB] /* Don’t optimize logic crossing clock domains */ set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB] compile Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Goals Summary
10-26 Defines output timing requirements set_output_delay
Define input arrival time relative to clock set_input_delay
Models skew on clock source set_clock_uncertainty
Define clock source create_clock set_dont_touch_network
LOGIC CLOUD
LOGIC CLOUD
Exceptions to single-cycle behavior: set_false_path
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
check_timing
10-27
Paths which are not completely or properly constrained may not appear in violation reports
Analysis should flag unconstrained paths so the problems can be corrected, e.g., by adding constraints dc_shell-t> dc_shell-t> check_timing check_timing
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 10: Introduction
10-28
45 min LAB
Add skew and run timing reports constraints.tcl
runit.tcl
mapped
compile
PRGRM_CNT_TOP.db
Run timing reports
Timing Report
Timing Report
Timing Report
Timing Report
default
min
pins
nets Timing Revisited
Synopsys 31833-000-S16
Chip Synthesis Workshop
Appendix
10-29
Multicycle Paths
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multi-Cycle Behavior
10-30
Situation: Not all paths operate at the target frequency of the design
SYSTEM_SYNCH_SET FF4
DATA
FF1
64 x 64 MULTIPLIER
FF2
CLK
Choose one of the following options: 1. Add pipeline stage(s) to divide the logic into single-cycle paths 2. Ease off the single-cycle requirement: allow more clock cycles
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Checks on Multicycle Paths
10-31
The hold check is related to the setup check
The default hold check is one edge before the setup 0
1
2
2-cycle example
setup check default hold check Tp < delay < 2Tp
dc_shell-t> set_multicycle_path 2 -from A -to B
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Multicycle Path: Example
10-32
We want Design Compiler to allow two clock cycles for BIG_LOGIC: FF3
FF1
AD
BIG_LOGIC
FF4
FF2
CLK
set_multicycle_path 2 -setup -from [get_cells FF1] -to [get_cells FF2]
set_multicycle_path 1 -hold -from [get_cells FF1] -to [get_cells FF2]
Timing Revisited Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 3 DAY 3
Unit
11-1
Topic
10
Timing Revisited
11
Optimization
12
Compile Strategies
13
Compiling a Hierarchical Design
14
DC Tcl - Procedures
Lab
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
11-2
After completing this unit, you should be able to:
List the three phases of optimization
List three architecture-level optimizations
List two types of logic-level optimizations
Identify the two gate-level optimizations
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Three Phases of Optimization
11-3
Optimization can occur at each of three levels: HDL Description or unmapped db
mapped db
Architectural
Logic-Level
Gate-Level
High-Level Synthesis
Structure & Flatten
Mapping
Optimized Netlist Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Architectural Optimization
HDL Description or unmapped db
11-4
DesignWare Implementation Selection
Architectural
Sharing Common Subexpressions Resource Sharing
mapped db
Reordering Operators
Logic-Level
Gate-Level
Structure & Flatten
Mapping
Optimized Netlist Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Arithmetic Operators
11-5
For the code: if (int0) y <= busA + busB; else y <= busC + busD;
What type of circuit is implied by the “+” sign? What type of adder should be synthesized? How many adders will appear in the final circuit?
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
DesignWare Implementation Selection
11-6
Multiple architectures for each macro allow DC to evaluate speed/area tradeoffs and choose the best implementation fastest
Ripple Carry Select
Z <= A + B; Conditional Sum Synthesis
DW Foundation
Brent-Kung
+
Carry Look-Forward HDL Operator
Carry Look-Ahead smallest
Ripple Carry
DW Basics
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
DesignWare Foundation
AND Gates, OR Gates, Flip-Flops...
target_library
Technology Library
Adders, Multipliers, Comparators...
11-7
synthetic_library
DesignWare Library
Hardcoding of {standard.sldb} is implicit to always provide basic implementations of +, -, *, >=, <, <= etc…
The synthetic_library variable points to a list of synthetic library database files (.sldb):
set synthetic_library “dw_foundation.sldb” Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Other High-Level Optimizations
Sharing Common Subexpressions
Resource Sharing
Operator Reordering
11-8
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Sharing Common Sub-Expressions
11-9
DC can “share” common mathematical sub-expressions B C A
A
SUM1 <= A + B + C; SUM2 <= A + B + D; SUM3 <= A + B + E;
E A
B
C
+
+
Implies D
B D A
B E
+
+
+
+
SUM1
SUM2
SUM3
E
+ +
+
+
SUM1
SUM2
SUM3
Share
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Coding To Force Sharing
11-10
Remember HDL coding can force a specific topology to be synthesized To force a shared topology directly: temp SUM1 SUM2 SUM3
:= <= <= <=
A + B; temp + C; temp + D; temp + E;
B
A
C
D
E
+ +
+
+
SUM1
SUM2
SUM3
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Resource Sharing: Example Given the following HDL description, two different structures might be synthesized:
A
A
+
C SUM
C D
if (SEL = ‘1’) then SUM <= A + B; else SUM <= C + D; end if;
More area-efficient implementation:
Implied implementation:
B
11-11
+
SEL
+
SUM
B D
SEL Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Resource Sharing
11-12
A resource is a DesignWare Component
The following HDL operators imply resources that can be shared:
* + >
>=
<
<=
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Operator Reordering
11-13
Design Compiler can automatically reorder arithmetic operators to produce the fastest designs Example: Z
<=
A + B + C + D
(where Z is time constrained)
Initial ordering is left to right: A B C D
+ + +
Z
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Reordering Operators for Fast Design A
If inputs arrive at the same time, Design Compiler will create a balanced tree architecture
If signal A is late arriving, Design Compiler may reorder the operators
Remember:
11-14
+
B
Z
+ C
+
D
B C D Late A
+ + +
Z
Coding style can force a particular order Z = ( (B+C) + D) + Late_A; Optimization
Synopsys 31833-000-S16
Chip Synthesis Workshop
High-Level Synthesis Is Constraint-Driven 11-15 High-level synthesis is based on design constraints and coding style Very important to specify realistic constraints Design Compiler makes high-level synthesis decisions to produce area-efficient results that meet timing High-Level Synthesis takes place only when optimizing an unmapped design
It will not occur when reoptimizing a gate-level netlist EXCEPTION: DesignWare incremental implementation selection can recur after mapping to gates
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Logic-Level Optimization HDL Description or unmapped db Architectural-Level
mapped db Logic-Level
Gate-Level
11-16
High-Level Synthesis
Structure Flatten
Mapping
Optimized Netlist
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Logic-Level Optimization (cont)
After high-level optimization, circuit function is represented by GTECH parts
Two optimization processes can occur during Logic- Level optimization:
11-17
1. Structuring 2. Flattening
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
What Is Structuring?
11-18
The use of intermediate terms to create a multilevel implementation of a design that satisfies constraints Useful for speed optimization as well as area optimization This is the default logic-level optimization strategy C B A STR
D Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
What Is Flattening?
11-19
The reduction of combinational logic paths to a two-level, sum-of-products (SOP) circuit Useful for speed optimization; may be very area-intensive A B C D SOP
set_flatten true -effort low | medium | high Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Structuring vs. Flattening
11-20
A B C
C B A
vs.
D
D
Structuring
Flattening
Creates intermediate structures to implement design
Removes intermediate structures — reduces design to SOP
Is constraint-based
Is done independent of constraints
Can help both area and speed of a design
Can be very area-intensive
No guarantee that flattening will actually map to a two-level SOP (possible library limitations)
set_structure true | false
set_flatten true | false Optimization
Synopsys 31833-000-S16
Chip Synthesis Workshop
Three Phases of Optimization
11-21
Optimization can occur at each of three levels: Architectural, Logical, and Gate
HDL Description or unmapped db Architectural-Level
High-Level Synthesis
mapped db Logic-Level
Phases of Gate-Level Optimization: 1. Delay 2. DRC I 3. DRC II 4. Area
Structure & Flatten
Combinational
Gate-Level
and Sequential Mapping
Optimized Netlist Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Combinational Mapping
11-22
The process of using gates from the target library to generate a design that meets timing and area goals A B C
A B C
F
A B
gG
F
A B
Gg
A C B A SLOW B
Q
A B
A B SLOW
C
Q
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Sequential Mapping
11-23
Process by which Design Compiler maps to sequential cells from the technology library
Tries to save speed and area by using a more complex sequential cell
0
A
A SEL
D ENA
1
CLK SEL CLK
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Fixing Design Rule Violations
11-24
Technology libraries contain vendor-specific design rules for each cell, e.g. max_capacitance
During mapping, Design RuleConstraints (DRCs) are checked Phases of Gate-Level Optimization: 1. Delay 2. DRC I 3. DRC II 4. Area
Design Compiler tries to fix all design rule violations without affecting area or speed
If no other way can be found, Design Compiler fixes design rule violations at the expense of timing and area
Design Compiler inserts buffers and resizes cells to correct design rule violations Optimization
Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary
11-25
HDL Description or unmapped db
Architectural
mapped db
Logic-Level
Gate-Level
High-Level Synthesis
Structure & Flatten
Mapping
Optimized Netlist
Optimization Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 3 DAY 3
Unit
12-1
Topic
10
Timing Revisited
11
Optimization
12
Compile Strategies
13
Compiling a Hierarchical Design
14
DC Tcl - Procedures
Lab
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
12-2
After completing this unit, you should be able to: Interrupt compilation List the default priority of constraints Enable DC to work harder on the critical path Explain the difference between a compile and an incremental compile Fix hold time violations
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Compile Completion
12-3
Compile Completion
Compile Strategies
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Compile Complete
12-4
Compiling stops when: All constraints are met Design Compiler reaches a point of diminishing returns User interrupt
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
User Interrupt
12-5
Typing a Ctrl-C during delay optimization will result in the following menu appearing: Please Please type type in in one one of of the the following following option: option: 11 to to Write Write out out the the current current status status of of the the design design 22 to to Abort Abort optimization optimization 33 to to Kill Kill the the process process 44 to to Continue Continue optimization optimization Please Please enter enter aa number: number:
Pressing Ctrl-C three times kills the dc_shell process
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Compile Report
12-6
Beginning Delay Optimization Phase ---------------------------------ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- ------- --------- --------- ------------------0:10:04 2761.7 1.38 3.20 18.1 Zro_Flag_reg/D 0:10:05 2761.7 1.38 3.20 18.1 Zro_Flag_reg/D 0:10:08 2761.7 1.28 3.10 18.1 Zro_Flag_reg/D 0:10:12 2761.7 1.26 3.06 18.1 Zro_Flag_reg/D
Critical Path timing violations
Sum of all timing violations
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Compile Strategies
12-7
Compile Completion
Compile Strategies
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Constraint and Timing Analysis You have performed a default compile. The reports indicate remaining violations. report_constraint -all_violators
12-8
good starting point
Reports all constraints which have been violated in the design Includes design rules, setup, hold and area
report_timing -delay max
Reports the worst timing path for each path group for setup time constraints
report_timing -delay min
Reports the worst timing path for each path group for hold time constraints
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Things to Look for
12-9
During constraint / timing analysis, what should you look for? How large is the worst negative slack (WNS)? Do you have design rule violations? Do you have hold time violations? How many paths are violating timing?
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Big Violations
12-10
dc_shell> report_constraint -all Information: Updating design information... (UID-85) **************************************** Report : constraint -all_violators Design : RISC_CORE Version: 1999.05 Date : Thu Nov 11 09:38:42 1999 **************************************** max_delay/setup ('Clk' group)
A rather big violation
Required Actual Endpoint Path Delay Path Delay Slack --------------------------------------------------------------------------RESULT_DATA[1] 1.20 2.84 r -1.64 (VIOLATED) RESULT_DATA[2] 1.20 2.84 r -1.64 (VIOLATED) RESULT_DATA[8] 1.20 2.84 r -1.64 (VIOLATED) RESULT_DATA[14] 1.20 2.84 r -1.64 (VIOLATED) RESULT_DATA[5] 1.20 2.84 r -1.64 (VIOLATED) RESULT_DATA[11] 1.20 2.84 r -1.64 (VIOLATED)
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
What Should I Do Next?
12-11
Check the constraints Check the partition
Re-compile the optimized netlist Re-compile using a higher effort Change the HDL source code Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Use Re-Compile HDL Architectural
12-12 Entire design will be returned to a GTECH representation
Logic-Level
Gate-Level
Optimized Netlist
dc_shell-t> compile
Logic-level optimization will be performed Gate-level optimization will be performed DesignWare Implementations may still be changed
A successive compile will probably not help, unless you change something!
Modify the constraints Change the set_structure or set_flatten options Change the map effort of compile Compile Strategies
Synopsys 31833-000-S16
Chip Synthesis Workshop
Change the Effort Level compile
12-13
-map_effort (low | medium | high)
Controls how “hard” DC works on the critical path during gate-level optimization low:
Do NOT use for production work or as starting point for other optimizations
medium:
Always start with medium compile effort Default Should produce good results most of the time
high:
Activates additional algorithms Very CPU intensive
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Start from a Changed HDL Source
HDL Architectural
Logic-Level
12-14
Runs through all levels of optimization Takes changes in the HDL source fully into account
Gate-Level
Optimized Netlist
Caveat: The source code might not be available or cannot be changed anymore.
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Small Violations
12-15
dc_shell> report_constraint -all Information: Updating design information... (UID-85) **************************************** Report : constraint -all_violators Design : RISC_CORE Version: 1999.05 Date : Thu Nov 11 09:38:42 1999 **************************************** max_delay/setup ('Clk' group)
Assuming your constraints and partitions are correct, what should you do?
Required Actual Endpoint Path Delay Path Delay Slack --------------------------------------------------------------------------RESULT_DATA[1] 1.20 1.30 r -0.10 (VIOLATED) RESULT_DATA[2] 1.20 1.26 r -0.06 (VIOLATED) RESULT_DATA[8] 1.20 1.26 r -0.06 (VIOLATED) RESULT_DATA[14] 1.20 1.22 r -0.02 (VIOLATED) RESULT_DATA[5] 1.20 1.22 r -0.02 (VIOLATED) RESULT_DATA[11] 1.20 1.22 r -0.02 (VIOLATED)
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Use Incremental Mapping Architectural
Logic-Level
compile
-incremental_mapping
Only gate-level optimization is done
Gate-Level
Optimized Netlist
12-16
The design is not taken back to GTECH” No logic-level optimization DesignWare Implementations may still be changed
Incremental is much faster than regular compile
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Incremental Mapping (cont) compile
Architectural
Logic-Level critical Gate-Level
path
-inc
12-17 -map high
Algorithm only accepts solutions that reduce critical path slack The design will most likely get better or stay the same
Optimized Netlist
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
The set_critical_range Command
12-18
set_critical_range 2 current_design() timing 2ns
paths
This command causes DC to optimize all violating paths within 2ns of the critical path Very CPU and memory intensive. Use with caution!
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
When You Have Design Rule Violations
12-19
Design rule violations may cause timing violations Use the following report commands
report_constraint -all_violators report_net -connections -verbose report_timing -net (for fanout) Added buffer to fix DR
set_max_capacitance 0.1 A
A CLK
N
D Q FF2 QB
A
N
D Q FF2 QB
CLK
compile -only_design_rule Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
What if You Have Hold Time Violations? 12-20 My design works fine for worst case conditions, but when I check it for best case, I have minimum delay violations!
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Hold Time Violations
12-21
What is the minimum delay requirement from FF2 to FF3?
N
(assume 0.5 ns hold requirement on FF3)
D Q FF2 QB
X
D Q FF3 QB
S
CLK
0
0.5
FF2/CLK FF3/CLK FF3/D
VALID Hold
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Let’s Complicate the Picture What is the minimum delay requirement now?
N
12-22
D Q FF2 QB
X
D Q FF3 QB
S
CLK 0.5 0
0.5
1.0
FF2/CLK FF3/CLK VALID
FF3/D
Hold
Hold time requirements are affected by Synopsys 31833-000-S16
Skew on the clock tree network Operating Conditions FF Hold Time
Compile Strategies Chip Synthesis Workshop
Checking for Hold Time Violations
12-23
Typically, you will fix hold time violations after layout
Clock tree timing is not accurate until layout
Fixing “phantom” hold time violations may cause setup violations and increase area
Often, pre-layout hold violations are “fixed” when real net delays are used for hold time analysis
Best-Case operating conditions may assume zero net delay!
Sometimes you may need to fix hold time violations before layout
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Use Simultaneous Min-Max
12-24
Simultaneous Min-Max Optimization
Environment and timing constraints supported for BOTH min and max values Fixes hold time without violating setup time constraints
What constraints should you specify before analyzing and fixing hold time violations? set_clock_uncertainty -hold set_input_delay -min set_output_delay -min set_operating_conditions -min -max
Specify min and max technology library set_min_library max_library -min_version min_library
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Apply set_input_delay for Hold Time
12-25
min 0.3ns TO_BE_SYNTHESIZED D Q FF1 QB
M
N
D Q FF2
X
D Q FF3
S
T
D Q FF4 QB
Clk
set_input_delay -min describes the fastest arrival time of the external logic on the input ports create_clock create_clock -period -period 10 10 [get_ports [get_ports Clk] Clk] set_input_delay set_input_delay -min -min 0.3 0.3 -clock -clock Clk Clk $all_in_ex_clk $all_in_ex_clk If FF2 has THOLD = 1ns: What is the min delay allowed for N? Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Apply set_output_delay for Hold Time 0.3ns
12-26 0.5ns Hold Time Requirement
TO_BE_SYNTHESIZED D Q FF1 QB
M
N
D Q FF2
X
D Q FF3
S
T
D Q FF4 QB
Clk
set_output_delay -min describes the hold time requirement of the external logic on the output ports
If FF has THOLD = 0.5ns and TT = 0.3ns: What is the min output delay?
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Calculation of set_output_delay
12-27
Tmin 0.3ns D Q FF3
S
T
setup = 0.8 hold = 0.5 D Q FF4 QB
Clk
set_output_delay -max (Tmax + FF4setup) set_output_delay -min (Tmin - FF4hold)
create_clock -period 5 [get_ports Clk] set_output_delay -min (0.3-0.5) -clock Clk [all_outputs] -0.2 Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Fixing Hold Violations
12-28
set_fix_hold [all_clocks] compile -only_design_rule By default, DC does NOT fix hold time violations
Use set_fix_hold to tell DC to fix hold time violations
Use compile -only_design_rule
DC only adds buffers or resizes cells
DC fixes only design rule and hold time violations
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary: Example Script
12-29
read_db read_db Top_meetsSetup.db Top_meetsSetup.db source source TimingConstraints_max.tcl TimingConstraints_max.tcl set_operating_conditions set_operating_conditions -max -max WORST WORST -min -min BEST BEST set set ALL_IN_EX_CLOCK ALL_IN_EX_CLOCK [remove_from_collection [remove_from_collection \\ [all_inputs] [all_inputs] [get_ports [get_ports Clk]] Clk]] set_input_delay set_input_delay -min -min 0.2 0.2 -clock -clock Clk Clk $ALL_IN_EX_CLOCK $ALL_IN_EX_CLOCK set_output_delay set_output_delay -min -min -0.1 -0.1 -clock -clock Clk Clk [all_outputs] [all_outputs] set_clock_uncertainty set_clock_uncertainty -hold -hold 0.5 0.5 [get_clocks [get_clocks Clk] Clk] report_timing report_timing -delay -delay min min ## Fix Fix min min timing timing violations violations set_fix_hold set_fix_hold [all_clocks] [all_clocks] compile compile -only_design_rule -only_design_rule redirect redirect top.rpt top.rpt {report_constraint {report_constraint -all_violators} -all_violators} Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 12: Introduction
12-30
45 min LAB
Practice Optimization Techniques source
source
calculation.v calculation.vhd
converter.v converter.vhd
Compile Strategies Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 3 DAY 3
Unit
13-1 Topic
10
Timing Revisited
11
Optimization
12
Compile Strategies
13
Compiling a Hierarchical Design
14
DC Tcl - Procedures
Lab
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
13-2
After completing this unit, you should be able to:
List two methods of resolving multiple instances
List one advantage and one disadvantage of using each method
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Compiling a Hierarchical Design
13-3
Compiling a Hierarchical DesignUnder The Hood
Resolving Multiple Instances
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Compiling a Hierarchy
13-4
D_design U1
U2 Ades
Bdes
Y= A+B
Y= A+B
U3 Cdes Y= A+B
Designs in the hierarchy are mapped to gates in two phases… Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
First Phase of Compile
13-5
The first phase of compile maps all blocks to gates without regard to constraints. D_design
D_design
U1 Ades
U2 Bdes
U1 Ades
U2 Bdes
Y=A+B U3 Cdes Y=A+B
U3 Cdes Y=A+B
D_design U1 Ades
U2 Bdes
U3 Cdes
Hierarchy is Preserved During a Compile Compiling a Hierarchical Design
Synopsys 31833-000-S16
Chip Synthesis Workshop
Second Phase of Compile
13-6
During the second phase, Design Compiler
optimizes logic to meet timing and area constraints
fixes violations caused by the surrounding blocks D_Design U1 Ades
U2 Bdes
U3 Cdes
What if a design is instantiated more than once?
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Resolving Multiple Instances
13-7
Compiling a Hierarchical DesignUnder the Hood
Resolving Multiple Instances
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Designs Instantiated More Than Once
13-8
In this example, Ades is used in two different locations Only one copy of the Ades exists in DC memory D_design U1
U2
Ades
Bdes
Y=A+B
Y=A+B
U3
Ades Y=A+B Ades
Bdes
Y=A+B
Y=A+B Design Compiler Memory
Which environmental attributes and constraints should DC use for Ades during compile? Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
check_design
13-9
dc_shell-t> dc_shell-t> check_design check_design
Returns warnings if your current design:
has multiple instantiations
has unconnected pins
compile terminates if multiple instantiations are not resolved!
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Methods to Resolve Multiple Instances
13-10
1.uniquify 2.compile + dont_touch D_design U1
U2 Ades
Bdes
Y=A+B
Y=A+B U3 Ades Y=A+B Bdes
Ades
Y=A+B
Y=A+B Design Compiler Memory
You must resolve multiple instances using one of these methods! Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Method #1: uniquify
13-11
uniquify makes a copy of each multiply-instantiated design (one copy for each instance)
Each instance gets a unique design name DC can now map each instance to its own specific environment D_Design U1 Ades_0 Y=A+B
U2 Bdes Y=A+B Bdes
Ades_0 Y=A+B
U3 Ades_1
Y=A+B
Y=A+B Ades_1 Y=A+B Design Compiler Memory Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Method #1: uniquify (cont)
13-12
D_Design U2
U1 Ades_0
Bdes
Y=A+B
Y=A+B
U3 Ades_1 Y=A+B
current_design D_design source D_constraints.tcl uniquify compile
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Method 2: compile + dont_touch
13-13
1. Constrain and compile Ades 2. Place a dont_touch attribute on the compiled Ades 3. Compile D_design D_design U1
U2
Ades
Bdes
Y=A+B
Y=A+B
U3 Ades Y=A+B Bdes
Ades
Y=A+B
Y=A+B Design Compiler Memory dont_touch
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Method 2: compile + dont_touch
13-14
read_db read_db unmapped/A_des.db unmapped/A_des.db current_design current_design Ades Ades link link source source Aconstraints.tcl Aconstraints.tcl compile compile read_db read_db unmapped/D_design.db unmapped/D_design.db current_design current_design D_design D_design set_dont_touch set_dont_touch [get_designs [get_designs Ades] Ades] source source Dconstraints.tcl Dconstraints.tcl compile U1 compile
D_design U2
Ades
Bdes Y=A+B U3
Ades
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Using set_dont_touch U1 Ades
13-15 U2 Bdes
U3 Ades
D_design
set_dont_touch can be assigned to design objects
It prevents modification of that design object Caution: If placed on an unmapped design, the design will remain unmapped
To resolve the multiple instantiation, set_dont_touch on the design Ades
Prevents any further optimization of instances U1 and U3 Compiling a Hierarchical Design
Synopsys 31833-000-S16
Chip Synthesis Workshop
uniquify vs. compile + dont_touch D_design
D_design U1
U2
Ades
13-16
Bdes
U3
U1
U2
Ades
Bdes
U3
Ades
Ades
uniquify
dont_touch
_________
__________
Which could take more time to compile? _________
__________
Which would offer you better results?
__________
Which solution would be easier to implement?
_________
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary current_design D_design source Dconstraints.tcl uniquify
13-17 Method #1
compile current_design Ades source Aconstraints.tcl compile current_design D_design set_dont_touch [get_designs Ades] source Dconstraints.tcl compile
Method #2
Use uniquify unless you are concerned about:
compile run times (large blocks or tightly constrained blocks)
memory limitations (large blocks or many instances)
laying out the block only once Compiling a Hierarchical Design
Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 13: Introduction LAB
13-18
45 min
Compiling a Hierarchical Design unmapped STACK_TOP.db
uniquify
dont_touch
mapped
mapped
STACK_TOP_ UNIQUIFY.db
STACK_TOP_ DONT_TOUCH.db
Compiling a Hierarchical Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 3 DAY 3
Unit
14-1
Topic
10
Timing Revisited
11
Optimization
12
Compile Strategies
13
Compiling a Hierarchical Design
14
DC Tcl - Procedures
Lab
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
14-2
After completing this unit, you should be able to:
Use Tcl commands to build loops and control flows
Write procedures for a DC-Tcl script for constraining a design
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Control Flow: Examples
14-3
if if [file [file exists exists My_Design.db] My_Design.db] {{ read_db read_db My_Design.db My_Design.db }} else else {{ echo echo Could Could not not read read My_Design.db My_Design.db }}
must be on same line as else!
set set FTYPE FTYPE [file [file type type My_Design.db] My_Design.db] switch switch $FTYPE $FTYPE {{ file {read_db file {read_db My_Design.db} My_Design.db} link {echo link {echo db db file file is is aa symbolic symbolic link} link} default default {echo {echo File File is is not not aa valid valid type type for for reading} reading} }}
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Looping Structures
14-4
## foreach foreach loop loop example example -- iterates iterates over over ## elements elements of of aa list: list: set set MYlist MYlist {Hello {Hello World} World} foreach foreach list_element list_element $MYlist $MYlist {{ echo echo $list_element $list_element }} ## while while loop loop example example set set idx idx 00 set set clk_per clk_per 10.0 10.0 ## Create Create divided divided clocks clocks on on ports ports CLK0 CLK0 -- CLK9 CLK9 while {$idx < 10} { while {$idx < 10} { create_clock create_clock -period -period $clk_per $clk_per [get_ports [get_ports CLK$idx] CLK$idx] incr incr idx idx set set clk_per clk_per [expr [expr (2 (2 ** $clk_per)] $clk_per)] }} Results shown in the Notes section Synopsys 31833-000-S16
DC Tcl - Procedures Chip Synthesis Workshop
Iterating over a Collection: Example
14-5
read_db read_db mapped/PRGRM_CNT_TOP.db mapped/PRGRM_CNT_TOP.db set set CellColl CellColl [get_cells [get_cells *] *] set set Count Count 11 ## Print Print aa list list of of all all cells cells in in the the Design Design foreach_in_collection foreach_in_collection SingleCell SingleCell $CellColl $CellColl {{ set set CellName CellName [get_object_name [get_object_name $SingleCell] $SingleCell] echo echo Cell Cell $Count $Count is is $CellName $CellName incr incr Count Count }} Results shown in the Notes section
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Tcl Procedures
Tcl allows the user to write their own “built-in” commands
14-6
Commands are written using a Tcl procedure
Powerful capabilities of procedures:
Allow you to define your own commands
Allow any number of arguments
user can define default values
Can have variable number of arguments
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Tcl Procedure Syntax myproc.tcl
14-7 necessary whitespace same line
proc proc CALC_PERIOD CALC_PERIOD {Clock_Freq} {Clock_Freq} {{ ## Convert Convert clock clock frequency frequency (Mhz) (Mhz) to to period period (ns) (ns) return return [expr [expr (( (1.0 (1.0 // $Clock_Freq) $Clock_Freq) ** 1000)] 1000)] }} dc_shell-t> dc_shell-t> source source myproc.tcl myproc.tcl dc_shell-t> dc_shell-t> CALC_PERIOD CALC_PERIOD 125.0 125.0 8.0 8.0 dc_shell-t> dc_shell-t> create_clock create_clock \\ -period -period [CALC_PERIOD [CALC_PERIOD 125.0] 125.0] \\ [get_ports [get_ports Clk] Clk] DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Scope of Variables
14-8
Variables created in a procedure only live for the duration of the procedure, (local scope)
Any variable defined outside any procedure is a global variable
Global variables are not visible to a procedure unless the global scope keyword is used when defining the variables in the procedure dc_shell-t> dc_shell-t> proc proc SP SP {} {} {{ global global search_path search_path set set search_path search_path “$search_path “$search_path ./scripts” ./scripts” }} dc_shell-t> dc_shell-t> SP SP dc_shell-t> dc_shell-t> echo echo $search_path $search_path {... {... slow_core.db slow_core.db ./scripts} ./scripts} DC Tcl - Procedures
Synopsys 31833-000-S16
Chip Synthesis Workshop
Procedure Information
14-9
Display the procedures in memory dc_shell-t> dc_shell-t> info info procs procs .. .. .. CALC_PERIOD CALC_PERIOD dc_shell-t> dc_shell-t>
Display the contents of a procedure dc_shell-t> dc_shell-t> info info body body CALC_PERIOD CALC_PERIOD ## Convert Convert clock clock frequency frequency (Mhz) (Mhz) to to period period (ns) (ns) return return [expr [expr (( (1.0 (1.0 // $Clock_Freq) $Clock_Freq) ** 1000)] 1000)] dc_shell-t> dc_shell-t>
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Tcl Procedure: Example
14-10 procs.tcl
proc TimeBudget
{clock_freq time_budget}
{
# Constrain a design for timing, using a time budget # clock_freq # time_budget # #
clock frequency in Mhz percentage of clock period allowed for delay of input/output logic in design being constrained
# calculate intermediate variables set CLK_PER [expr ((1/$clock_freq) * 1000)] set MY_IO_CONSTRAINT [expr ($CLK_PER*($time_budget/100.0)) ] set IO_DELAY [expr ($CLK_PER - $MY_IO_CONSTRAINT)] set all_except_clk [remove_from_collection \ [all_inputs] [get_ports Clk*] ] # constrain the design for timing DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Tcl Procedure: Example (cont)
14-11
# constrain the design for timing # create clock on clock port create_clock -period $CLK_PER -name MY_CLOCK [get_ports Clk*]
\
# constrain the inputs set_input_delay $IO_DELAY -max -clock MY_CLOCK \ $all_except_Clk # constrain the outputs set_output_delay $IO_DELAY -max -clock MY_CLOCK [all_outputs] };
\
# end of TimeBudget
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Tcl Procedure: Example (cont)
14-12
source procs.tcl read_db PRGRM_CNT_TOP.db current_design PRGRM_CNT_TOP # constrain design for Timing # using a clock period of 100 Mhz # and 40% of the clock period for IO timing TimeBudget 100.0 40.0 # constrain design for environmental attributes
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 14: Introduction LAB
14-13
30 min
Create two generic Tcl procedures unmapped PRGRM_CNT_TOP.db
myprocs.tcl proc TimeBudget proc LoadBudget
runit.tcl read_db ... TimeBudget LoadBudget compile report_constraint write...
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Check for errors
14-14
check_error -verbose dc_shell-t> dc_shell-t> check_error check_error -reset -reset dc_shell-t> dc_shell-t> source source my_script.tcl my_script.tcl dc_shell-t> dc_shell-t> check_error check_error -v -v 00 dc_shell-t> dc_shell-t>
check_error -reset dc_shell-t> dc_shell-t> check_error check_error -reset -reset dc_shell-t> dc_shell-t> source source my_script.tcl my_script.tcl dc_shell-t> dc_shell-t> check_error check_error -v -v {CMD-010} {CMD-010} dc_shell-t> dc_shell-t> error_info error_info
DC Tcl - Procedures Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 4 DAY 4
Unit
15-1 Topic
15
Compiling a Large Design
16
Design Exploration
17
Synthesizing for Test
18
Conclusion
Lab
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
15-2
After completing this unit, you should be able to:
Execute a top-down compile
Execute a bottom-up compile
Determine a second-pass compile strategy
Execute the characterize command
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Techniques for Compiling a Hierarchical Design 15-3
Techniques for Compiling a Hierarchical Design
Techniques for the Second-Pass Compile
characterize
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Hierarchical Compile Techniques: Types 15-4
There are two strategies for compiling a large hierarchical design:
Top-down
Bottom-up
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Top-Down Compile Methodology 1. 2. 3. 4. 5. 6.
Read in the entire design Resolve multiple instances Apply top-level constraints Compile Assess results Save design
15-5
DATA_PATH
INSTRN_LAT
PRGRM_CNT_TOP
STACK_TOP
ALU
REG_FILE
RISC_CORE top-down.tcl analyze -format vhdl {alu.vhd reg_file.vhd ... risc_core.vhd } elaborate RISC_CORE uniquify source scripts/top_level.tcl compile report_constraint -all write -format db -hierarchy -output mapped/RISC.db quit Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Advantages of Top-Down
15-6
"push-button" approach Intermodule dependencies are taken care of automatically Fewer man-hours spent “driving the tool”
Most productive approach when practical
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Simple Compile Mode
15-7
For designs without aggressive timing constraints • Run time can be reduced • Multiple instantiations are mapped once during compile • At the end of optimization, you get an automatically uniquified netlist analyze -format vhdl {alu.vhd... risc_core.vhd} elaborate RISC_CORE source scripts/top_level.tcl /* Do NOT execute uniquify */ set_simple_compile_mode true compile set_simple_compile_mode false
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Hierarchical Compile Techniques
15-8
There are two strategies for compiling a large hierarchical design:
Top-down
Bottom-up
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Bottom-Up Compile Methodology
15-9
1. Constrain and compile subblocks independently RISC_CORE
2. Make sure all subblocks meet their initial constraints 3. Read in the entire compiled design and apply top-level constraints
ALU
PRGRM_CNT_TOP
. . . REG_FILE
4. Check constraint report: if your design passes, you’re are done!
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Bottom-Up Compile Methodology
15-10
Compile each subblock to meet their respective budget
analyze analyze -format -format vhdl vhdl {PRGRM_CNT.vhd {PRGRM_CNT.vhd ... ... PRGRM_CNT_TOP.vhd} PRGRM_CNT_TOP.vhd} elaborate elaborate PRGRM_CNT_TOP PRGRM_CNT_TOP source source constraints.tcl constraints.tcl compile compile report_constraint report_constraint -all -all >> reports/PRGRM_CNT_TOP.rpt reports/PRGRM_CNT_TOP.rpt /* /* MAKE MAKE SURE SURE timing timing has has been been met! met! If If not, not, recode recode or or recompile recompile */ */ write write -format -format db db -hier -hier -output -output mapped/PRGRM_CNT_TOP.db mapped/PRGRM_CNT_TOP.db
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Bottom-Up Compile Methodology (cont) 15-11 Perform top-level integration and constraint analysis read_vhdl read_vhdl source/RISC_CORE.vhd source/RISC_CORE.vhd /* /* Bring Bring in in compiled compiled .db .db files files */ */ link link /* /* SYSTEM-LEVEL SYSTEM-LEVEL Constraints Constraints */ */ source source Top_level.tcl Top_level.tcl /* /* Check Check for for timing timing violations violations */ */ report_constraint report_constraint -all -all >> reports/RISC_CORE.rpt reports/RISC_CORE.rpt write write -format -format db db -hier -hier -output -output mapped/RISC_CORE.db mapped/RISC_CORE.db
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Pros & Cons of Bottom-Up Compile
15-12
Advantages:
Large designs are compiled with the “divide and conquer” approach Not limited by available memory
Disadvantages:
May require iterations until block-to-block interfaces are stable
Requires careful revision control
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary
15-13
Use top-down for “smaller” designs An overnight compile is considered a reasonable compile run time
Use bottom-up for all other designs Make time and load budgets as accurate and conservative as possible
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Techniques for the Second-Pass Compile 15-14
Techniques for Compiling a Hierarchical Design
Techniques for the Second-Pass Compile
characterize
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Problems After the First-Pass Compile
15-15
What if there were still timing violations after the first-pass top-down compile? What if there were timing violations during top-level integration after the bottom-up compile? RISC_CORE
ALU
CONTROL
DATA_PATH
PRGRM_CNT_TOP
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Use report_constraint -all dc_shell>
15-16
report_constraint -all
*************************** Report : constraint -all_violators Design : RISC_CORE Version: 1999.05 Date : Fri Nov 12 11:57:30 1999 ***************************
The violationis roughly 15% of the timing constraints.
max_delay/setup ('Clk' group) Required Actual Endpoint Path Delay Path Delay Slack ---------------------------------------------------------------------I_ALU/Zro_Flag_reg/D0 9.34 10.78 r -1.44 (VIOLATED) I_ALU/Neg_Flag_reg/D0 9.31 10.39 f -1.09 (VIOLATED) I_ALU/Lachd_Result_reg[15]/D0 9.31 10.31 f -1.00 (VIOLATED) OUT_VALID 1.20 2.16 r -0.96 (VIOLATED) I_ALU/Lachd_Result_reg[14]/D0 9.31 9.89 f -0.59 (VIOLATED)
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Use report_timing
15-17
Point Incr Path -------------------------------------------------------------------------clock Clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 I_DATA_PATH/Oprnd_B_reg[3]/CLK (fdmf1a2) 0.00 0.00 r I_DATA_PATH/Oprnd_B_reg[3]/Q (fdmf1a2) 0.85 0.85 f I_DATA_PATH/Oprnd_B[3] (DATA_PATH) 0.00 0.85 f I_ALU/Oprnd_B[3] (ALU) 0.00 0.85 f I_ALU/add_72/plus/A[3] (ALU_DW01_add_16_1) 0.00 0.85 f I_ALU/add_72/plus/U124/Y (inv1a0) 0.34 1.19 r I_ALU/add_72/plus/U79/Y (inv1a2) 0.32 1.51 f I_ALU/add_72/plus/U180/Y (nor2a2) 0.20 1.71 r
• • •
I_ALU/U564/Y (ao3e1) I_ALU/U509/Y (mx2d2) I_ALU/Lachd_Result_reg[14]/D0 (fdm1a1)
0.60 0.28 0.00
data arrival time
9.61 r 9.89 f 9.89 f 9.89
All of the combinational logic causing the violation is fully contained in ALU.
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Next Steps
15-18
A more aggressive second-pass top-down compile
compile -incremental -map_effort high
Compile only top-level violations
Check the partitions
Build a new design budget for the design ALU
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Compile only Top-Level Violations
15-19
What if after bottom-up compile we have timing violations at the top-level?
compile -top
Fixes timing violations on top-level paths only
Less memory and CPU intensive than a top-level compile -incremental
A good compile strategy to fix integration problems due to small discrepancies in design budgets Compiling a Large Design
Synopsys 31833-000-S16
Chip Synthesis Workshop
Check Your Partitions
15-20
How would you compile this design? RISC_CORE CONTROL
PRGRM_CNT ALU
40 k gates
20 k gates
DATA_PATH
Glue 5k 100 k gates
data_bus 32 30 k gates
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Top-Level Partitions
15-21
Compile top-down on as large a design as is reasonable for compile run times and floorplan issues Motivation: Often produces better results in less time than a design budgeting/bottom-up strategy
Partition at register outputs for timing-critical paths and major hierarchical blocks
Generating design budgets is greatly simplified
Design Compiler will not optimize logic across hierarchical boundaries
To repartition change your HDL source or use group/ungroup. Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Build a New Design Budget
15-22
Design Budgeting!
“Tighten” the budget for time, load, and drive budgets for each block to meet
Compile each block to meet that budget
Integration at top level should cause no problems if: All blocks compiled and met their budget Budget was accurate and sufficiently constrained the design
How can we automate the process of generating new design budgets?
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
characterize
15-23
Techniques for Compiling a Hierarchical Design
Techniques for the Second-Pass Compile
characterize
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
The characterize Command
15-24
characterize calculates the actual attributes and constraints imposed on a design by its surroundings characterize then places those constraints on the design TOP U1 A
U2
U3 C
Output Load and Delay Constraints
B
Input Delay Times and Drive on Inputs
current_design TOP characterize -constraints find(cell, U2) current_design B compile -inc -map high Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Viewing the Results of characterize
15-25
write_script outputs a script containing all of the constraints that have been set on the current_design /****************************************************** Created by write_script() on Mon Oct 12 18:44:54 1998 ******************************************************/ /* Set the current_design */ current_design ALU create_clock -name "my_clock" -period 10 -waveform {0 5} find(port,"Clk") set_dont_touch_network find(clock, "my_clock") set_input_delay 2.2439 -max -rise -clock "my_clock" find(port,"Latch_Flags") set_input_delay 2.28963 -max -fall -clock "my_clock" find(port,"Latch_Flags") set_output_delay 5.77132 -max -rise -clock "my_clock" find(port,"Carry_Flag") set_output_delay 5.80142 -max -fall -clock "my_clock" find(port,"Carry_Flag") set_load -pin_load 0.343 find(port, "Reset") set_wire_load "tc6a120m2" -library "cba_core" -port_list find(port, "Reset") set_driving_cell -lib_cell buf1a4 -pin "Y" -no_design_rule find(port,"Reset") set_max_capacitance 2.4 find(port, "Reset") Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Recompile HDL Source after characterize 15-26
Create a script to characterize and recompile design B TOP U1 A
current_design TOP characterize -cons U2 current_design B write_script > B_w.tcl remove_design -hier B
U3 U2 B
C
read -f verilog B.v current_design B source B_w.tcl compile write -hier -o B.db current_design TOP report_constraints
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
characterize Limitations
15-27
characterize can only be used when all blocks are mapped to gates
characterize can NOT be used to derive first-pass compile design budgets
characterize can only be done one block at a time Once a block has been characterized and recompiled, there are “new” cells driving/loading other subblocks
characterize “pushes away” any margin that may exist on block-block interface
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Summary
15-28
Use the Top-Down methodology if feasible
The second-pass compile strategy depends on the kind of violations in the design
characterize allows to generate detailed blocklevel constraints from the interblock requirement
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Lab 15: Introduction LAB
60 min
Resolve Timing Violations
15-29
RISC_CORE
ALU
CONTROL
DATA_PATH
PRGRM_CNT_TOP
This exercise is a review of the last few labs, so spend some time thinking about the various compile steps. Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Appendix
15-30
Design Budgeter
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Budgeter
15-31 Allocate Budgets U1 U4 U5
Compile U1
Compile U4
Compile U5
Reassemble Modules Verify Timing
Designs Best Suited for Budgeting Hierarchical Designs Large Designs Designs with subblocks that are not fully registered Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Budgeter Methodology Build initial constraints
RTL
bottom-up compile
compile compile compile
constraints
15-32
GTECH database
budgeter Pass Zero
compile compile compile
refined constraints
budgeter Pass One
remove false_path
compile -inc
Pass Two
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Build the Initial Timing Constraints
65
15-33
35
virtual clock
create_clock -period n -name vclock; create_clock -period n -name reg2reg clk_ports; set_input_delay -clock vclock 0.35*n \ $all_inports_except_clockports; set_output_delay -clock vclock 0.65*n [all_outputs]; set_false_path -from reg2reg -to reg2reg; Do not use the -max or -min options ! Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Example U1
15-34 U3
U4
Timing Model
U5
U2 dont_touch
allocate_budget -write_context {U1 U4 U5} Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Command Flow
15-35
Pass Zero budget_shell> read_db mapped/TOP.db budget_shell> allocate_budgets -check_only budget_shell> allocate_budgets -write_context {U1 U4 U5} budget_shell> sh ls U1.ptsh U4.ptsh U5.ptsh
Pass One budget_shell> budget_shell> budget_shell> budget_shell> budget_shell>
critical design read_db unmapped/U1.db source U1.ptsh compile allocate_budgets -write_context U1 write -f db -hier -out mapped/U1.db
Pass Two budget_shell> budget_shell> budget_shell> budget_shell>
current_design U1 source U1.ptsh compile -inc write -f db -hier -out mapped/U1.db Compiling a Large Design
Synopsys 31833-000-S16
Chip Synthesis Workshop
How to Access Design Budgeter?
15-36
PrimeTime (Tcl) pt_shell> allocate_budgets
Design Budget Shell (Tcl) budget_shell> allocate_budgets
Note: allocate_budget is not supported in dc_shell-t; use the budget_shell instead.
Compiling a Large Design Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 4 DAY 4
Unit
16-1
Topic
15
Compiling a Large Design
16
Design Exploration
17
Synthesizing for Test
18
Conclusion
Lab
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
16-2
After completing this unit, you should be able to:
Perform a Design Exploration compile
Fine-tune the Design Constraints
Build user-defined Path Groups
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Classic Six-Month Design Flow
Plan: Three Months for Coding and Simulating
16-3 HDL Coding
Functional Simulation Functionally Correct?
No
Code Freeze Yes
Synthesis Plan: Three Months for Implementing the Design
Test Insertion Physical Design
How Long Has it Taken You to do it This Way?
Gate-Level Analysis & Signoff Design Exploration
Synopsys 31833-000-S16
Chip Synthesis Workshop
Traditional Reactive Flow
16-4
Traditional Flows address problems reactively, after they occur
Functional Simulation
HDL Coding Functionally Correct?
Bad budgets “painted you into a corner”
No
Yes
Synthesis
Failed
Test Insertion Failed Physical Design
Failed
Final Analysis & Signoff Failed
Couldn’t meet timing (inefficient RTL code) Fault Coverage <10% (uncontrollable reset) Unroutable (too congested) Couldn’t meet timing after place and route Design Exploration
Synopsys 31833-000-S16
Chip Synthesis Workshop
Identify and Resolve Problems Early!
16-5
Degrees of Freedom Library, Algorithm, Architecture System-Level Constraints
Cost $
Code, Partitions, BOA, HLO
$$$$
DC switches, BRT
$$$$$$
LBO/FPM
$$$$$$$$$$$$ Layout
Proactive Design Exploration • Discover and resolve performance issues early in the flow • Fix problems at the source code level whenever possible • Plan for the speed and area impact of scan insertion • Anticipate the problems of slow top-level interconnects Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
The Proactive Design Methodology Logical Design
16-6
Physical Design Check Tool Flow
Code RTL
Validate Design
Early Floorplan / P&R Functional Simulation Check WLM’s Design Exploration
Create Custom WLM
Code Freeze?
Implement Design
Compile Major Subblocks
Floorplan
Integrate Chip
Create Custom WLM
Reoptimize Design
Place & Route
Final Analysis & Signoff
ECO P&R Design Exploration
Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Exploration
16-7
A quick, exploratory synthesis run to gauge design performance against goals
When is Design Exploration performed?
In parallel with functional simulation, not at the end!!! Any time code changes enough to impact performance On small blocks of code where the problem is self-contained and easily fixable Logical Design Code RTL Functional Simulation Design Exploration
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Exploration Goals
Use the fastest, default-effort compiles possible to:
Verify that code is synthesizable
Verify that code is close to meeting constraints (10-15%)
Verify that constraints are realistic and sufficient
Identify and declare timing exceptions
Identify partitioning problems
Identify testability problems
Account for the impact of inserting scan cells
Ensure that your wire load models are “reasonable”
16-8
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Why 10% and Not 0%?
16-9
You are simply validating that you are close to meeting timing with the code you have, so you don’t have to recode later.
Design Compiler was not meant to fix bad code Garbage In ==> Garbage Out
You can reasonably expect advanced compile strategies to fix violations that are 10-15% over timing
More efficient HDL code (better algorithms and architectures) is often required to fix larger violations
You are performing exploration on code that may not be stable yet.
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
What Is the Design Exploration Flow? New
16-10
Constrain
HDL code Recode HDL
Test-ready compile
Repartition Design FIX
Analyze timing, partitioning, & test rule violations GOOD Initial Floorplan, Create custom wire load model
FIX
Design Exploration
Continue
Analyze timing violations GOOD
Simulation
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Typical Constraint Script (Basic)
16-11
my_block_constraints.tcl # Define clock create_clock -period 5 [get_ports CLK] set_dont_touch_network [all_clocks] # Delay and drive strength on input ports set all_inputs_but_clk [remove_from_collection [all_inputs] CLK] set_input_delay $clk_to_q -clock CLK $all_inputs_but_clk set_driving_cell -lib_cell $my_register $all_inputs_but_clk # Delay and load on output ports set_output_delay [expr 5 - $clk_to_q] -clock CLK [all_outputs] set_load [expr $pessimistic_load * 3] [all_outputs] A # Describe environment B set_operating_conditions WCCOM CLK set_wire_load_model -name 100k_WLM -mode top
Y
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Detailed Modeling of External Loads
16-12
set pessimistic_load [expr load_of(TECH_LIB/inv1a1/A)] # Account for Pin Load and Wire Load on Outputs set_load [expr $pessimistic_load * 3] [all_outputs]
# pins
set_port_fanout_number 3 [all_outputs]
# wires
# Account for Pin Load and Wire Load on Inputs too! set_load $pessimistic_load $all_inputs_but_clk
# pins
set_port_fanout_number 1 [all_inputs]
# wires
MY_BLOCK
A
A
inv1a1
A A
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Special WLM for Ports (Global Nets)
16-13
# Describe different WLMs for internal nets vs. global nets set_wire_load_mode top 100k_WLM set_wire_load_model -name GLOBAL_NET_WLM [get_ports *] TOP BLOCK_1
BLOCK_2
BLOCK_3
BLOCK_4
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Rule Constraints
DC respects design rules as highest priority of all
Certain design rules may exist on library cell pins
16-14
max_capacitance max_transition max_fanout
You can apply design rules to entire designs to:
Anticipate the interface environment your block will see
Prevent the design from operating cells close to their limits, where performance degrades rapidly
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
set_max_capacitance
16-15
my_dr_cons.tcl # Find the max capacitive load allowed on your expected driver set DRIVE_PIN TECH_LIB/inv1a27/Y set MAX_CAP [get_attribute
$DRIVE_PIN
max_capacitance]
3.600 # Add some margin so DC won’t fully load the driver set CONSERVATIVE_MAX_CAP [expr $MAX_CAP / 2.0] 1.800 set_load 1.2 [get_ports IN1] set_max_capacitance $CONSERVATIVE_MAX_CAP [get_ports IN1] # max internal load DC can put on IN1 is [1.8 - 1.2 = 0.6pf]
inv1a27 Y A
IN1
1.2pf Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
set_max_transition
16-16 my_dr_cons.tcl
# Find the max transition allowed on your expected driver set DRIVE_PIN TECH_LIB/inv1a27/Y set MAX_TRANS [get_attribute
$DRIVE_PIN
max_transition]
0.400 # Add some margin so DC won’t fully load the driver set CONSERVATIVE_MAX_TRANS [expr $MAX_TRANS / 2.0] 0.200 set_max_transition $CONSERVATIVE_MAX_TRANS [get_ports IN1] # DC accounts for the driving_cell type and external load on it, # limits internal loads placed on IN1 to meet your design rule
inv1a27 Y A
IN1
1.2pf Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
set_max_fanout
16-17
set_max_fanout 6 [get_ports IN1]
A IN1
Y inv1a1 inv1a1 inv1a1 inv1a27 inv1a27
Is the max_fanout design rule on port IN1 met? How many cells might port IN1 have to drive? Does it matter what the cell type is?
get_attribute TECH_LIB/inv1a1/A fanout_load 0.25 # DC might load port IN1 with 6 / 0.25 = 24 inv1a1 cells! get_attribute TECH_LIB/inv1a27/A fanout_load 3.00 # DC can only load port IN1 with 6 / 3.00 = 2 inv1a27 cells! Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Fanout Loads
16-18
•set_max_fanout uses fanout_load, NOT absolute fanout number! • Sum of fanout_load on a port must be less than max_fanout design rule constraint A = 0.25 = 0.25
IN1
= 0.25 = 3.00 = 3.00
Y inv1a1 inv1a1 inv1a1 inv1a27 inv1a27
Some cell/pins have no fanout_load attribute
DC then checks library for default_fanout_load attribute
If neither exists, DC assumes a value of zero This may allow infinite fanout on an input port! Design Exploration
Synopsys 31833-000-S16
Chip Synthesis Workshop
Controlling Port Fanout
16-19
How can I force port fanout to only one real load? # Easiest case set_max_fanout 1 [all_inputs] # Trickier case set SMALL_CELL TECH_LIB/buf1a1/A set SMALL_FOL get_attribute $SMALL_CELL 0.5000 set_max_fanout $SMALL_FOL [all_inputs]
Does my library have the necessary attribute? get_attribute 0.0000 # Uh-oh!
TECH_LIB
default_fanout_load
If not, how can I set it? set_attribute TECH_LIB -type float 1.0000
Synopsys 31833-000-S16
fanout_load
default_fanout_load
1.0 \
Design Exploration Chip Synthesis Workshop
Typical Compile Script (Basic)
16-20
compile_flow.tcl # Read in source files and build initial Gtech design if (You_are_using_VHDL) { analyze -format vhdl {file1.vhd file2.vhd file3.vhd TOP.vhd} elaborate TOP } else { read_verilog {file1.v file2.v file3.v TOP.v} } # Constrain the Gtech design source my_block_constraints.tcl source my_dr_cons.tcl # Optimize and map the design compile # Save the design and exit write -format db -hierarchy -output my_block.db quit Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Fastest Runtimes for Design Exploration
16-21
current_design MY_BLOCK reset_design source time_and_load_budget_constraints.tcl remove_attribute MY_BLOCK “max_area” if (You_Have_DesignWareFoundation_and_Plan_To_Use_It) { set synthetic_library dw_foundation.sldb append link_library “ $synthetic_library” } set_simple_compile_mode true set compile_dw_simple_mode true set_scan_configuration -style multiplexed_flip_flop
compile
-area_effort none
-scan
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Additional Runtime Speed-ups
16-22
New in v2000.05: “Presto” RTL code reader
Average 6x faster Verilog elaboration than in v1999.10 Presto’s VHDL support due in v2000.10 release Average 35% less memory usage Supports additional Verilog language constructs
dc_shell-t> set hdlin_enable_presto true
New in v2000.05: New Verilog netlist reader
Average 3x faster than v1999.10 Average 3x memory reduction compared to v1999.10
dc_shell-t> set enable_verilog_netlist_reader dc_shell-t> read_verilog -netlist mapped.v
true
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Scenarios: Exploring Subdesigns
16-23
What Compile Technique Should I Use During Design Exploration? What Constraints Should I Consider During Design Exploration?
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Design Exploration on SUBDESIGN_A
SUBDESIGN_A’s RTL code just became available
16-24
It is a very critical block, and you want to evaluate its performance without waiting for the other blocks
SUBDESIGN_A is a small block
Its parent block will eventually be compiled top-down Its inputs and outputs might not be registered SUBDESIGN_A (40 K gates) PRGRM_CNT
DATA_PATH OUT_BUS [31:0]
IN_BUS [31:0]
10K
20K CONTROL ZERO_FLAG
10K CLK
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
How To Constrain SUBDESIGN_A
MAJOR_BLOCK_1 will be compiled top-down later...
16-25
…after code for A, B, C, D becomes available and stable Inputs and outputs of subdesigns might not be registered
How do we constrain SUBDESIGN_A for a standalone compile at this level? MAJOR_BLOCK_1 (140 K gates)
IN_BUS [31:0]
SUBDESIGN_A (40K gates)
SUBDESIGN_B (30K gates)
OUT_BUS [31:0]
D Q SUBDESIGN_C (50K gates)
SUBDESIGN_D (20K gates)
CLK
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
How To Constrain SUBDESIGN_A (cont)
16-26
How do we constrain SUBDESIGN_A for a standalone compile at this level?
Use what you know
Clock period Operating Conditions
Estimate what you don’t know
Input drives, Output loads, Wire load model, Time Budget
create_clock -period 10 [get_ports CLK] set_dont_touch_network [get_clocks CLK] set_operating_conditions SLOW_COMMERCIAL set_wire_load_model -name 140Kgates -mode top set_driving_cell -lib_cell NAND2 -pin Y $all_in_ex_clk set_load [expr [load_of TECH_LIB/NAND2/A] * 4] $all_in_ex_clk set_load [expr [load_of TECH_LIB/NAND2/A] * 6] [all_outputs]
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
How To Constrain SUBDESIGN_A: I/O
16-27
What about I/O timing?
Are your inputs driven by blocks with registered-outputs? Are your outputs registered? Do you have purely combinational paths in your design?
MAJOR_BLOCK_2 SUBDESIGN_A A
32
W
32
RECEIVING_BLOCK
DRIVING_BLOCK B
32
X
32
C
32
Y
32
D
32
Z
32
?
?
?
?
CLK Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
I/O Timing Constraint Options
16-28
# Assume every block has registered outputs, same 10ns clock
set_input_delay
-max
$clk_to_q
-clock CLK $all_in_ex_clk
set_output_delay -max [expr 10 - $clk_to_q] -clock CLK [all_outputs]
MY_DESIGN
DRIVING_BLK D Q FF0 QB
A
D Q FF1 QB
RECEIVING_BLK D Q FF2 QB
Z
D Q FF3 QB
CLK
# Assume every block has registered outputs, same 10ns clock
set_input_delay -max
[expr $CLK_PER * 0.1] -clock CLK $all_in_ex_clk
set_output_delay -max [expr $CLK_PER * 0.9] -clock CLK [all_outputs] Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
I/O Timing Constraint Options (cont)
16-29
# Assume blocks do not have registered outputs; split delay equally among both sides # This is the typical case when exploring smaller, lower-level blocks
set_input_delay
-max [expr $CLK_PER * 0.5] -clock CLK $all_in_but_clk
set_output_delay -max [expr $CLK_PER * 0.5] -clock CLK [all_outputs]
MY_DESIGN
DRIVING_BLK D Q FF0 QB
A
D Q FF1 QB
RECEIVING_BLK D Q FF2 QB
Z
D Q FF3 QB
CLK
How much “margin” is built into these constraints?
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Exploring Combinational Paths set_input_delay
16-30
-max [expr $CLK_PER * 0.5] -clock CLK $all_in_ex_clk
set_output_delay -max [expr $CLK_PER * 0.5] -clock CLK [all_outputs] MY_DESIGN
A
D Q FF1 QB
D Q FF2 QB
Z
CLK B
COMBO
Y
How do these constraints affect the combinational path from B to Y? Do they affect optimization of MY_DESIGN? Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
User-Defined Path Groups
16-31
Custom path groups allow more control over optimization
Each path group is optimized independently Worst violator in one path group doesn’t prevent optimization in another
Path groups can be given different priorities
Register-to-Register Paths Input Paths
A
D Q FF1 QB
D Q FF2 QB
Z
Output Paths
CLK
B
COMBO
Combinational Paths Synopsys 31833-000-S16
Y
Design Exploration Chip Synthesis Workshop
Creating Custom Path Groups
16-32
DO IN A LAB! Use group_path to group paths of interest group_path -name INPUTS -from [all_inputs] group_path -name OUTPUTS -to [all_outputs] group_path -name COMBO -from [all_inputs] -to [all_outputs]
In which path group will register-to-register timing paths be? In which path group will combinational timing paths be? How does this affect a compile? How can you remove the user defined path groups?
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Two Path Group Options
16-33
# Avoid getting stuck on one path in the reg-reg group group_path -name INPUTS -from [all_inputs] group_path -name OUTPUTS -to [all_outputs] group_path -name COMBO -from [all_inputs] -to [all_outputs] group_path -name clk -critical_range 0.3
A
D Q FF1 QB
D Q FF2 QB
Z
CLK B
COMBO
Y
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Path Groups vs Critical Range
16-34
Path Group
Path Groups will allow path improvements in a given group which degrade another group’s worst violator, IF the overall cost function is improved
Adding a path group can INCREASE the worst violator in a design
Critical Range
Critical Range will not allow improvements to near-critical paths that worsen the worst violator in a path group
To optimize all critical endpoints in a design, giving each endpoint its own path group usually runs faster than using a very large critical_range, but runtime can be excessive for either case if many paths are involved
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
When Do I Exit Design Exploration?
16-35
Completion Criteria for all major subblocks Timing violations less than 10% of actual goals Good design partitioning No test rule violations Accurate wireload models Single-cycle timing exceptions identified Additional, user-defined criteria
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Review
16-36
Be Proactive! Anticipate Problems as early as possible.
Perform design exploration
Validate your tool flow
Floorplan early
Check accuracy of wire load models
Design Exploration Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 4 DAY 4
Unit
17-1
Topic
15
Compiling a Large Design
16
Design Exploration
17
Synthesizing for Test
18
Conclusion
Lab
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
17-2
After completing this unit, you should be able to:
List at least two benefits of using the compile scan command
State the command that checks a design for testability violations
State the command that shows the estimated fault coverage of your circuit
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Chip Defects: They’re Not My Fault!
17-3
My chip was well designed and functionally correct. It simulated and synthesized just fine, but when the chip was manufactured, it didn’t work!
WHY?
.
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Manufacturing Defects
17-4 Electrical Effects
Physical Defects Silicon Defects Photolithography Defects Mask Contamination Process Variations Defective Oxide
Shorts (Bridging Faults) Opens Transistor Stuck On/Open Resistive Short/Open Changes in Threshold Voltage
Logical Effects Logic Stuck-at-0/1 Slower Transitions (Delay Fault) AND-bridging, OR-bridging
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Why Test for Manufacturing Defects?
The manufacturing test is created to detect manufacturing defects and reject those parts before shipment
Debug manufacturing process
Improve process yield
17-5
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
How Is Manufacturing Test Performed?
DUT
Outputs
Automatic Test Equipment (ATE) applies input stimulus to the Device Under Test (DUT) and measures the output response Inputs
17-6
If the ATE observes a response different from the expected response, the DUT fails the manufacturing test
The process of generating the input stimulus and corresponding output response is known as Automated Test Pattern Generation (ATPG) Synthesizing for Test
Synopsys 31833-000-S16
Chip Synthesis Workshop
The Stuck-At Fault Model
17-7
Output Stuck At Logic 1 (SA1)
Input Stuck At Logic 0 (SA0)
Stuck-At Fault (SAF): A logical model representing the effects of an underlying physical defect.
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Algorithm for Detecting a SAF
17-8
If this SA0 fault is present then U1/Y stays at logic 0 If not present, then U1/Y is driven to its normal value A SA0
B
U1
Z
C
D
We can exploit this “either/or behavior” to detect the fault. Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Controllability
17-9
The ability to set internal nodes to a specific value
1/0
0
U1
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Observability
17-10
The ability to propagate the fault effect from an internal node to a primary output port 0/1
1 1/0
0
Observable Discrepancy
U1
1/0
0
0
0 Enabling Input
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Fault Coverage
Fault coverage =
17-11
number of detectable faults total number of possible faults
High fault coverage correlates to high defect coverage
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Testing a Multistage, Pipelined Design
17-12
Can create a lot more complications for you Test for SA0 fault here 1
Need to observe results at the output of the design.
0 0 1
Need to set input pins to specific values so that nets within pipeline can be set to values which test for a fault Each fault tested requires a predictive means for both controlling the input and observing the results downstream from the fault. Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Scan Chains Help
17-13
Scan chain initializes nets within the design (adds controllability) Scan chain captures results from within the design (adds observability) Inserting a scan chain involves replacing all Flip-Flops with scannable Flip-Flops Test for SA0 fault here.
Scan_Ena Scan_In
Scan Flip-Flop
1 0 0 1
What effect will the mux and scan chain have on circuit timing? Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Inaccuracy Due to Scan Replacements 17-14 If you plan to include internal scan, you must account for the impact of scan registers on a design early in the design cycle Larger area than non-scan registers; optimistic wire load model selection Larger setup time requirement
Additional fanout and capacitive loading TI
TI
1
DI
0
1
DO
DI
0
TE CLK
CLK
Multiplexed Scan Register Chain Non-Scan Register Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Use One-Pass Scan Synthesis
17-15
Regular registers are replaced with scannable ones, but not chained
Include the scan style in the constraint script file
set_scan_configuration -style multiplexed_flip_flop
Perform one-pass test scan compile
compile -scan Scan Register Used During Initial Compile
Benefits
Accurate area, timing, and loading modeled up front Easier synthesis flow -- scan cell insertion performed in one compilation step
TI
1
TO DO
DI
0
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Result of Test-Ready Compile: Example 17-16 dc_shell> compile -scan Scan cells inserted during compile A
D TI “0”
Q
D
TE
E
D TI
B “0”
Q
TE
CLK
Loading effect of scan chain modeled Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
DFT Checking: Example
17-17
D
Q
dc_shell> check_test Warning: Clock/enable pin CP of cell u0 (FD1) has multiple sources (TEST-126) Information: A source of the violation is port IN2 (TEST-182) Information: A source of the violation is pin Q of cell u0 (TEST-180) Information: A source of the violation is port CLK (TEST-182) Information: Test design rule checking completed with 1 warning(s) and error(s)
0
If a warning or error is returned, it is up to the user to correct the circuit so that there are no scan design rule violations. Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Testability Violation: Example D
17-18
Q
What would happen in the circuit above, if, during test, a ‘1’ were shifted into the Flip-Flop?
A: We would never be able to “clock” the Flip-Flop! The Flip-Flop, therefore, cannot be allowed to be part of a scan chain. Logic in ‘N’ cannot be tested (controlled).
The above circuit:
Violates good “design for test” practices Reduces the “fault coverage” Synthesizing for Test
Synopsys 31833-000-S16
Chip Synthesis Workshop
Running ATPG
17-19
create_test_patterns activates the ATPG function of DC
Execute ATPG after compile -scan and check_test dc_shell> create_test_patterns -dft -sample 11 Warning: Violations occurred during test design rule checking. (TEST-124) Building test generation network
No. of detected faults No. of abandoned faults No. of tied faults No. of redundant faults No. of untested faults Total no. of faults Fault coverage No. of test patterns
Non-collapsed 1423 2 4 2 0 1431 99.86
Collapsed 1356 2 4 2 0 1364 99.85
174
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
What Is DFTC?
17-20
DFTC bundles together expert logic-synthesis capability plus all the design-for-test features you need to:
compile “scan-ready” logic blocks
check synthesized logic for scan compliance
insert scan chains, top-down or bottom-up
preview fault coverage on a scanned block
Design-for-Test Compiler (DFTC)
DFTC enables designers to do constraint-based scan synthesis!
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
DFTC Flow at a Glance
17-21
DFTC Methodology for a Typical Block: compile -scan
HDL
Scan-Ready Synthesis
Constraints: Scan style, speed, area
check_test insert_scan Pre-Scan DRC
Insert Scan
Technology Library: Gates, flip-flops, scan equivalents
check_test Post-Scan DRC
Run ATPG
Constraint-Based Scan Synthesis: Routing, balancing, gate-level optimization
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Test Tools Summary
17-22
DC-XP
Test Compiler
compile -scan
X
X
check_test
X
X
create_test_patterns -dft (coverage)
X
X
insert_scan
X
X
create_test_patterns (ATPG) write_test (for ATE and gate-level sim)
X X
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesizing for Test Summary
Test is a design methodology
17-23
It has its own testability design rules
Most problems associated with test can be anticipated and corrected in advance, during the initial compile of the HDL code
Synthesizing for Test Synopsys 31833-000-S16
Chip Synthesis Workshop
Agenda: Day 4 DAY 4
Unit
18-1
Topic
15
Compiling a Large Design
16
Design Exploration
17
Synthesizing for Test
18
Conclusion
Lab
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Unit Objectives
18-2
After completing this unit, you should be able to:
List at least four steps to take before compiling a design
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Some Thoughts on Coding Poor Start Point
18-3
Better Start Point Best Start Point
Goal
Spend more time writing good HDL code so you spend less time optimizing the design
If you’ve written your code so that the critical path is reduced to a single gate, and the design still does not meet the timing, then it is not your code that’s wrong
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Synthesis Quality Depends on Algorithms! 18-4
Solution to a design problem is typically based on a particular algorithm
From that algorithm, you specify a hardware architecture to solve the problem
Your high-level design decisions provide the starting point for DC’s translation, optimization, and mapping
DC’s HLO techniques can NOT change the algorithm or architecture you choose to implement!
Single-cycle vs. Pipelined over several cycles Serial vs. parallel FIR vs. IIR, etc…
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Classic Algorithms, Architectures, & Tradeoffs 18-5
Frequency Analysis: DFT vs. FFT
Sorting Algorithms: Bubblesort vs. Quicksort
Sine wave generator: Difference Equation vs. Counter + Lookup Table
Finite State Machines: 1-hot encoding vs. Binary
Microprocessor Design: RISC vs. CISC
Like circuits, algorithms also involve tradeoffs between speed, area, memory, code size/complexity, etc...
Choose the algorithm, architecture, and implementation to match the performance goals of your design. Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Reflections on Synthesis
18-6
There is no “golden’ script” for synthesis
Physics dictates what will fit between two registers
The random setting of optimization switches and constraints to meet your speed goals is not a credible methodology
Most timing problems are not caused by wrong compile switches!
Compile switches are a vehicle to fix compile problems late in the design cycle
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Pre-Compile Checklist
18-7
Good Synthesizable HDL Code
Good Synthesis Partitioning Realistic Constraints & Attributes False Paths Identified Wireloads Reflect Physical Placement (discussed in Advanced CHIP)
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
What Do You Do First?
18-8
1. Satisfy the items on the checklist. Use what you have learned in this workshop. 2. If adding margin, do not overconstrain by more than 10%. 3. Always, always, always (always!) start with the default compile. compile <-scan>
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Compile Strategy
18-9
Start Analyze and Elaborate HDL Apply Constraints = Small Violations (10-25%)
compile
= Larger Violations
compile -map high
compile -map high -incremental
Good Yes Results ?
Done! Rewrite HDLCode
No Analyze Analyzeto to identify problem, identify problem, then then......
Specify critical_range
Characterize Block
Repartition Block
Modify Flatten & Structure Options
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Timing Analysis to Diagnose the Problem 18-10 Spot the whales in the timing report: Where are they? What are they? And why? Point clock (input port clock) (rise edge) input external delay addr31 (in) u_proc/address31 (proc) u_proc/u_dcl/int_add[7] (dcl) u_proc/u_dcl/U159/Q (NAND3H) u_proc/u_dcl/U160/Q (NOR3F) u_proc/u_dcl/U186/Q (AND3F) u_proc/u_dcl/U86/Q (INVF) u_proc/u_dcl/U135/Q (NOR3B) u_proc/u_dcl/U136/Q (INVF) u_proc/u_dcl/U100/Q (NBF) u_proc/u_dcl/U95/Q (BF) u_proc/u_dcl/U96/Q (BF) u_proc/u_dcl/U94/Q (NBF) u_proc/u_dcl/U93/Q (NBF) u_proc/u_dcl/ctl_rs_N (dcl) u_proc/u_ctl/ctl_rs_N (ctl) u_proc/u_ctl/U126/Q (NOR3B) u_proc/u_ctl/U120/Q (NAND2B) u_proc/u_ctl/U99/Q (NBF) u_proc/u_ctl/U122/Q (OR2B) u_proc/u_ctl/read_int_N (ctl) u_proc/int_cs (proc) u_int/readN (int) u_int/U39/Q (NBF) u_int/U17/Q (INVB) u_int/U16/Q (AOI21F) u_int/U60/Q (AOI22B) u_int/U68/Q (INVB) u_int/int_flop_0/D (DFF) data arrival time
Incr 0.00 22.40 0.00 1.08 0.00 0.62 0.75 1.33 0.64 1.36 0.49 0.87 0.44 0.45 0.84 0.94 0.00 0.00 1.78 1.07 0.88 10.72 0.00 0.00 0.00 1.29 1.76 2.49 1.43 1.81 0.00
Path 0.00 22.40 22.40 23.48 23.48 24.10 24.85 26.18 26.82 28.17 28.67 29.54 29.98 30.43 31.27 32.21 32.21 32.21 33.98 35.06 35.94 46.67 46.67 46.67 46.67 47.95 49.71 52.20 53.63 55.44 55.44 55.44
f f f f r f f r f r r f r r r r r f r r r r r r r f r f r r
Rather late arrival for a 30 ns period! Six buffers back to back?!
11 ns delay for an OR gate is not good. Four hierarchical partitions.
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Look Back at the Past Several Days
18-11
Setup, Libraries, GUI, Coding for Synthesis (Day 1)
Describing the synthesis environment (Day 2)
Optimization and Compile Techniques (Day 3)
Design Exploration and DFT (Day 4)
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Need More Training?
VHDL Coding Styles for Synthesis
Verilog Coding Styles for Synthesis
Advanced Chip Synthesis Workshop
PrimeTime Workshops
Advanced Verilog & VHDL Workshops
And more...
18-12
1-800-793-3448 www.synopsys.com/services/education Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Advanced Chip Synthesis RTL
RTL .db
DC
Lib WLM
18-13
.v, .vhdl, .sdf, etc.
compile
Floorplanner .db
Iterate
.db DC
PrimeTime
CLWM
RC SDF PDEF
Ultra
create_wire_load
PrimeTime
Computed Data ForwardAnnotate Placement PDEF
.db
DC
Ultra
reoptimize_design
ECO Iterate Actual Data
Place&Route RC SDF PDEF
GDSII Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Coding Styles for Synthesis
18-14
A_Temp = A; Count = 8; reg [7:0] Count; for (Level=0; Level<=2; Level= Level+1)
always @(posedge Clock) begin begin Count = Count >> 1; // Divide by 2 if (Reset) process (In_A, In_B) for (K = 0; K <= (Count - 1); K = K + 1) begin Count <= 8'b0;
A_Temp[K] = A_Temp[K * 2] +else A_Temp[(K * 2) + 1]; if In_A = '1' then Count <= Count + 1; Out_Z <= '0'; end Sum_Out = A_Temp[0]; else if In_B = '1' then always @(Count) Out_Z <= '1'; begin else And_Bits = &Count; Out_Z <= '-'; Or_Bits = |Count; end if; end if; Xor_Bits = ^Count;
end
end end process; Synopsys 31833-000-S16
Conclusion Chip Synthesis Workshop
Need More Information or Help?
Synopsys on the Web:
Services:
SOLD
Workshops
solv-Net
Support Center
Application Consultants
Technical Articles
Application Notes
Release Notes
18-15
ESNUG
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Synopsys on the World Wide Web
18-16
Next SNUG City:___________ Date:___________
Synopsys Web Server www.synopsys.com
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
How to Use solv-NET
18-17
Web Page: www.synopsys.com Follow the solv-NET link Enter your solv-NET ID
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Human Sources for Information and Help 18-18
Contact the Support Center:
Click “Enter A Call” on the Synopsys Web page [email protected] 1-800-245-8005
Application Consultants:
Web E-mail Phone
Process and tool expertise available worldwide Contact your sales representative for more details
Consultants
Available for in-depth, on-site, dedicated, custom consulting Contact your sales representative for more details
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
Other Sources for Information and Help 18-19
ESNUG Independent Email Synopsys User’s Group Customer problems, workarounds, cool scripts Updates on John Cooley’s love life, housecleaning, etc
[email protected] www.deepchip.com
www.eda.org Links to VHDL, Verilog Archives Links to EDA companies Links to other EDA sites
Newsgroups: comp.cad.synthesis comp.lang.verilog comp.lang.vhdl comp.lsi.cad comp.arch.fpga
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
That’s all Folks!
18-20
Conclusion Synopsys 31833-000-S16
Chip Synthesis Workshop
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