Iphone 7plus Schematis

8

7

6

5

4

3

2

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

1

REV

ECN

CK APPD

DESCRIPTION OF REVISION

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DATE

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

0006532879

ENGINEERING RELEASED

2016-07-06

D11 MLB - PVT LAST_MODIFICATION=Wed Jul

6 08:55:26 2016

D

D PAGE

1

TABLE OF CONTENTS

<SYNC_MASTER1>

2

2

SYSTEM:BOM TABLES

<SYNC_MASTER2>

3

3

4

4

5

5

6

6

7

7

DATE <SYNC_DATE1>

PAGE



SYNC

CONTENTS

DATE <SYNC_DATE46>

46

46

LARGE FORM FACTOR SPECIFIC

47

47

I2C MAP: AP, TOUCH, HOMER, I2C5

48

48

I2C MAP AOP

<SYNC_MASTER48>

49

49

I2C TABLE

<SYNC_MASTER49>

50

50

spare

<SYNC_MASTER50>

spare

51

51

spare

<SYNC_MASTER51>

SOC:JTAG,USB,XTAL

52

52

MLB UNIQUE

<SYNC_MASTER52>

8

SOC:PCIE

53

53

CELL,WIFI,NFC

<SYNC_MASTER53>

9

9

SOC:MIPI AND ISP

54

54

page1

10

10

SOC:LPDP

55

55

NFC

SOC:SERIAL

56

56

page1

SOC:GPIO & UART

57

57

METROCIRC [2]

SOC:AOP

58

58

UAT MATCH AND TUNER [3]

SOC:POWER (1/3)

59

59

WIFI_MLB SCHEMATIC

SOC:POWER (2/3)

60

60

PERENNIAL

61

61

WIFI FRONT-END [77]

62

62

page1

SYSTEM POWER:PMU (1/3)

63

63

BOM_OMIT_TABLE

SYSTEM POWER:PMU (2/3)

64

64

PMU: CONTROL AND CLOCKS

SYSTEM POWER:PMU (3/3)

65

65

PMU: SWITCHERS AND LDOS

SYSTEM POWER:CHARGER

66

66

BASEBAND: POWER2

SYSTEM POWER:BATTERY CONN

67

67

BASEBAND: CONTROL

SYSTEM POWER:BOOST

68

68

BASEBAND GPIOS

SENSORS

69

69

TRANSCEIVER0/1: POWER

B2B FILTERS: UTAH

70

70

TRANSCEIVER0/1: TX PORTS

71

71

TRANSCEIVER0/1: PRX PORTS

<SYNC_MASTER71>

72

72

RECEIVE MATCHING

<SYNC_MASTER72>

TRINITY:FF SPECIFIC

73

73

LOWER ANTENNA & COUPLERS

<SYNC_MASTER73>

B2B:FOREHEAD

74

74

DIVERSITY RECEIVE ASM'S

<SYNC_MASTER74>

75

75

DIVERSITY RECEIVE LNA'S

d

AUDIO:CALTRA CODEC (1/2)

76

76

UPPER ANTENNA FEEDS

AUDIO:CALTRA CODEC (2/2)

77

77

PMU: ET MODULATOR

AUDIO:SPEAKER AMP 2

78



TEST POINTS & BOOT CONFIG

<SYNC_MASTER78>

11 12 13 14 15 16 17 18

11

12

13

14

15

16

17

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

B

SYNC

1

8

C

CONTENTS

32

SYSTEM:EEEE CALLOUTS

<SYNC_MASTER3>

SYSTEM:MECHANICAL COMPONENTS

<SYNC_MASTER4>

SYSTEM: BOARDID

<SYNC_MASTER5>

<SYNC_DATE2> <SYNC_DATE3> <SYNC_DATE4> <SYNC_DATE5>

SOC:POWER (3/3) NAND

CAMERA:STROBE DRIVER <SYNC_DATE27>

Accessory: Buck Circuit

<SYNC_DATE30>

B2B:NEVADA

<SYNC_DATE48> <SYNC_DATE49> <SYNC_DATE50> <SYNC_DATE51> <SYNC_DATE52> <SYNC_DATE53>

C

33

33

34

34

AUDIO:SPEAKER AMP 1

79



TDD TRANSMIT

<SYNC_MASTER79>

35

35

ARC:DRIVER

80



FDD TRANSMIT

<SYNC_MASTER80>

36

36

ARC:MAGGIE

81



ICEFALL, SIM, DEBUG_CONN

<SYNC_MASTER81>

37

37

DISPLAY & MESA:POWER



<SYNC_MASTER82>

38

38

B2B:ORB & MESA



<SYNC_MASTER83>

39

39

B2B FILTERS: DISPLAY & TOUCH



<SYNC_MASTER84>

40

40

TRISTAR 2



<SYNC_MASTER85>

41

41

B2B:DOCK FLEX



<SYNC_MASTER86>

42

42

spare



<SYNC_MASTER87>

43

43

spare



<SYNC_MASTER88>

44

44

B2B FILTERS: RIGHT BUTTON FLEX



<SYNC_MASTER89>

45

45

B2B FF SPECIFIC



<SYNC_MASTER90>

<SYNC_DATE71> <SYNC_DATE72> <SYNC_DATE73> <SYNC_DATE74>

<SYNC_DATE78>

B

<SYNC_DATE79> <SYNC_DATE80> <SYNC_DATE81> <SYNC_DATE82> <SYNC_DATE83> <SYNC_DATE84> <SYNC_DATE85> <SYNC_DATE86> <SYNC_DATE87> <SYNC_DATE88> <SYNC_DATE89> <SYNC_DATE90>

TABLE OF CONTENTS

A

SYNC_MASTER=david-copy

TABLE OF CONTENTS

SYNC_DATE=03/01/2016

DRAWING TITLE

SCH,MLB,D11 DRAWING NUMBER

Schematic & PCB Callouts TABLE_5_HEAD

PART#

051-00482

QTY

1

DESCRIPTION

SCH,MLB,D11-12

REFERENCE DESIGNATOR(S)

SCH

CRITICAL

CRITICAL

BOM OPTION

? TABLE_5_ITEM

820-00229

1

PCBF,MLB,D11-12

PCB

CRITICAL

?

System Block Diagram:

SCH 051-00482 BRD 820-00229 MCO 056-01585

Apple Inc.

051-00482 REVISION

8.0.0

R



NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

1 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

1 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

NAND BOM Options

5

4

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

PART NUMBER

BOM OPTION

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

1

U1701

NAND,H,32GB,16nm,MLC

CRITICAL

U1701

NAND,H,128GB,16nm,TLC

CRITICAL

BOM OPTION

REF DES

COMMENTS:

371S00087

371S00064

ALTERNATE

D2700

DIODE,SHOTTKY,30V,200MA,0201

152S00558

152S00557

ALTERNATE

L2700

IND,MLD,0.47UH,2.5A,80Mohm,1608

376S00166

376S00164

ALTERNATE

Q2700,Q2701

PFET,12V,CSP4

TABLE_ALT_ITEM

NAND_32G

TABLE_ALT_ITEM

376S00106 1

ALTERNATE FOR PART NUMBER

COMMENTS:

376S00047

ALTERNATE

Q2101

DIODES INC. ACT DIODE

TABLE_ALT_ITEM

TABLE_5_ITEM

335S00182

1 TABLE_ALT_HEAD

PART NUMBER TABLE_ALT_HEAD

TABLE_5_ITEM

335S00169

2

Acc Buck Alternates

Active Diode Alternate TABLE_5_HEAD

PART#

3

NAND_128G TABLE_ALT_ITEM

TABLE_5_ITEM

335S00183

1

U1701

NAND,T,256GB,3Dv3,TLC

CRITICAL

DDR PLL Alternate

NAND_256G TABLE_5_ITEM

138S0867

5

CAP,X5R,10UF,20%,6.3V,0.65MM,HRZTL,0402

C1748,C1713,C1716,C1721,C1733

CRITICAL

NAND_32G

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

155S00095

155S00068

ALTERNATE

FL1501

FERR BD,100OHM,25%,100MA,2OHM,01005

TABLE_5_ITEM

138S00003

5

CAP,X5R,15UF,20%,,6.3V,0.65MM,HRZTL,0402

C1748,C1713,C1716,C1721,C1733

CRITICAL

NAND_128G

D

TABLE_ALT_ITEM

D

TABLE_5_ITEM

138S00003

5

CAP,X5R,15UF,20%,,6.3V,0.65MM,HRZTL,0402

C1748,C1713,C1716,C1721,C1733

CRITICAL

Load Switch OMIT TABLE

NAND_256G

TABLE_5_HEAD

Power Inductor Alternates

TABLE_ALT_HEAD

PART NUMBER

335S00201

ALTERNATE FOR PART NUMBER

BOM OPTION

335S00169

ALTERNATE

REF DES

U1701

PART#

COMMENTS:

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION TABLE_5_ITEM

353S01007

1

U2710,NFCSW_RF

ONSEMI,IC,LOAD,SWITCH,WLCSP4

CRITICAL

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

152S00118

152S00075

ALTERNATE

ALL

IND,PWR,SHLD,1.2 UH,3.0A,0.080 OHM,2016

152S00077

152S00397

ALTERNATE

ALL

IND,PWR,SHLD,1.0 UH,2.25A,0.150 OHM,2016

T,15nm,MLC,32GB

TABLE_ALT_ITEM

TABLE_ALT_ITEM

335S00209

335S00169

ALTERNATE

U1701

S,16nm,MLC,32GB

TABLE_ALT_ITEM

updated 11/12

TABLE_ALT_ITEM

335S00195

335S00182

ALTERNATE

U1701

SS,1Ynm,TLC,128GB

335S00180

335S00182

ALTERNATE

U1701

T,15nm,TLC,128GB

TABLE_ALT_ITEM

152S00121

152S00081

ALTERNATE

ALL

IND,PWR,SHLD,0.47 UH,3.8A,0.048 OHM,2012

152S00123

152S1936

ALTERNATE

ALL

IND,PWR,SHLD,15 UH,0.72A,0.900 OHM,3225

152S00402

152S00366

ALTERNATE

ALL

IND,MULT,1UH,1.2A,0.320 OHM,0603

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

335S00179

335S00182

ALTERNATE

U1701

SD,15nm,TLC,128GB

TABLE_ALT_ITEM

updated 11/12

TABLE_ALT_ITEM

335S00148

335S00183

ALTERNATE

U1701

SD,3Dv2,TLC,256GB

335S00190

335S00183

ALTERNATE

U1701

SS,3Dv3,TLC,256GB

TABLE_ALT_ITEM

152S00297

152S1843

ALTERNATE

ALL

reverted 11/13

CYNTEC 2012 1UH

TABLE_ALT_ITEM

TABLE_ALT_ITEM

152S00365

152S00297

ALTERNATE

ALL

CYNTEC 2012 1UH

152S00398

152S00204

ALTERNATE

ALL

IND,PWR,0.22UH,20%,6.7a,23MOHM,2012

#22686038:See Radar

TABLE_ALT_ITEM

For Chestnut inductor; so it doesn't interfere with PMU inducotr Buck 7 alts TABLE_ALT_ITEM

152S00120

152S00077

ALTERNATE

ALL

For Chestnut inductor only

152S00117

152S00074

ALTERNATE

L1806,L1810,L1814,L1816,L1817

IND,PWR,SHLD,1.0 UH,3.0A,0.060 OHM,2016

Except BUCK5 LX (BUCK5 LX is Taiyo only) TABLE_ALT_ITEM

N&V 15uF Cap Alternates Global R/C Alternates C

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

C

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_ITEM

MUR+KYO 15UF

138S00005

138S00003

ALTERNATE

(C1818, C1825, C1831)

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

CPU

TABLE_ALT_ITEM

118S0764

118S0717

ALTERNATE

ALL

TABLE_ALT_ITEM

RES, 3.92K, 0.1%, 0201

138S00005

138S00003

ALTERNATE

(C1837, C1842, C1844)

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

138S00005

138S00003

ALTERNATE

(C1819, C1826, C1832)

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

138S00005

138S00003

ALTERNATE

(C1838, C1843, C1845)

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

138S00005

138S00003

ALTERNATE

(C1401, C1408, C1434)

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

138S00005

138S00003

ALTERNATE

(C1813, C1820, C1827)

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

TABLE_ALT_ITEM

TABLE_ALT_ITEM

138S0702

138S0657

ALTERNATE

ALL

CAP, X5R, 4.3UF, 4V, 0610

138S00006

138S0835

ALTERNATE

ALL

CAP, 3-TERM, 4.3UF, 4V, 0402

138S0648

138S0652

ALTERNATE

ALL

CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO

132S0400

132S0436

ALTERNATE

ALL

CAP,X5R,0.22UF,6.3V,01005,TDK

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

GPU + GPU_SRAM

TABLE_ALT_ITEM

138S00024

138S0986

ALTERNATE

ALL

TABLE_ALT_ITEM

CAP,CER,3-TERM,7.5UF,20%,4V,0402,TAIYO/TDK

138S00005

138S00003

ALTERNATE

(C1833, C1839, C1865)

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

138S00005

138S00003

ALTERNATE

(C1814, C1821, C1828)

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

138S00005

138S00003

ALTERNATE

(C1834, C1866, C1414)

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

138S00005

138S00003

ALTERNATE

(C1806, C1810)

CAP,X5R,15UF,6.3V,0.65MM,0402,TY

138S00048

138S00003

ALTERNATE

TABLE_ALT_ITEM

138S0706

138S0739

ALTERNATE

ALL

CAP,CER,1UF,20%,10V,X5R,0201,MURATA

138S0945

138S0739

ALTERNATE

ALL

CAP,CER,1UF,20%,10V,X5R,0201,KYOCERA

132S0436

132S0400

ALTERNATE

ALL

CAP,CER,X5R,0.22UF,20%,6.3V,20%

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Magnesium Alternates

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

338S00203

ALTERNATE

REF DES

COMMENTS:

TABLE_ALT_ITEM

ALL

CAP,X5R,15UF,6.3V,0.65MM,0402,KYOCERA

TABLE_ALT_ITEM

338S00173

U2402

Larger Wafer (-29 flow) Magnesium

Global Ferrite Alternates

B

B

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

155S00067

155S0581

ALTERNATE

ALL

FERR, 240OHM, 0.38OHM DCR, 0201

155S0581

155S00067

ALTERNATE

ALL

FERR, 240OHM, 0.38OHM DCR, 0201

155S00012

155S00168

ALTERNATE

ALL

FLTR, 65 OHMS, 0605

155S00194

155S0610

ALTERNATE

ALL

FERR BD, 150OHM, TDK

155S00200

155S0610

ALTERNATE

ALL

FERR BD, 150OHM, TY

152S00489

152S00456

ALTERNATE

ALL

FERR BD, 0.47UH, TY

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

UT LDO Alternates

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

353S00889

353S00015

ALTERNATE

U2501

ST, LDO REG, 2.925V, CSP 0.65x0.65

TABLE_ALT_ITEM

Mamba LDO Alternates

Global Varistor Alternates

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS: TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

377S0168

377S0140

ALTERNATE

ALL

VARISTOR, 6.8V, 100PF, 01005

TABLE_ALT_ITEM

353S00932

353S00576

ALTERNATE

U3801

ST, LDO REG, 2.75V TABLE_ALT_ITEM

I2C5 Alternate TABLE_ALT_HEAD

A

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS: SYNC_MASTER=Sync

335S00234

335S00233

ALTERNATE

U1101

SYNC_DATE=06/29/2016

PAGE TITLE

TABLE_ALT_ITEM

I2C5 ALTERNATE

SYSTEM:BOM TABLES DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

2 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

2 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D11 EEEE CALLOUTS TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION TABLE_5_ITEM

825-6838

1

EEEE CODE FOR 639-01812

EEEE_GY2T

CRITICAL

EEEE_D11_BEST_JP

825-6838

1

EEEE CODE FOR 639-01813

EEEE_GY2V

CRITICAL

EEEE_D11_SUPREME_JP

825-6838

1

EEEE CODE FOR 639-01814

EEEE_GY2W

CRITICAL

EEEE_D11_EXTREME_JP

825-6838

1

EEEE CODE FOR 639-02138

EEEE_H3RN

CRITICAL

EEEE_D11_BEST_ROW

TABLE_5_ITEM

TABLE_5_ITEM

D

TABLE_5_ITEM

D

TABLE_5_ITEM

825-6838

1

EEEE CODE FOR 639-02139

EEEE_H3RP

CRITICAL

EEEE_D11_SUPREME_ROW

825-6838

1

EEEE CODE FOR 639-02140

EEEE_H3RQ

CRITICAL

EEEE_D11_EXTREME_ROW

825-6838

1

EEEE CODE FOR 639-02460

EEEE_H8C1

CRITICAL

EEEE_D11_BEST_CH

825-6838

1

EEEE CODE FOR 639-02465

EEEE_H8CK

CRITICAL

EEEE_D11_SUPREME_CH

825-6838

1

EEEE CODE FOR 639-02462

EEEE_H8C3

CRITICAL

EEEE_D11_EXTREME_CH

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CAYMAN DDR Alternates TABLE_ALT_ITEM

339S00258

339S00257

ALTERNATE

ALL

DDR-S, 3G, B1

CAYMAN OMIT TABLE TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION TABLE_5_ITEM

339S00257

1

U0700

CAYMAN, DDR-H, 3G, B1

CRITICAL

C

C

2.2uF CAP Alts TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

138S00049

138S00032

ALTERNATE

ALL

CAP,CER,X5R,2,2UF,20%6.3V,20%, KYOCERA

138S0831

138S00032

ALTERNATE

ALL

CAP,CER,X5R,2,2UF,20%,6.3V,20%,MURATA

TABLE_ALT_ITEM

TABLE_ALT_ITEM

SIP Alternates TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

339M00009

339M00003

ALTERNATE

ALL

TRINITY BLUE,STATS

339M00008

339M00002

ALTERNATE

ALL

NEO,STATS

TABLE_ALT_ITEM

TABLE_ALT_ITEM

B

B

A

SYNC_MASTER=david-copy

SYNC_DATE=03/01/2016

PAGE TITLE

SYSTEM:EEEE CALLOUTS DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

3 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

3 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

Current as of D11 MCO 056-01585 rev. 63 O O

TESTPOINTS #25046211

Contained in radio_mlb pages

2.70R1.80-NSP 1

1

C0413 220PF

5% 2 10V C0G-CERM 01005

NEO Stiffener

UP_RFFE

POWER

NORTH_SCREW_EXPOSED

O

BS0415

D

LCM

1

C0414 56PF

5% 2 25V NP0-C0G-CERM 01005

1

C0415 18PF

2% 2 16V CERM 01005

1

TP0420 1 A

C0416

TP-P55

BS0401

2.70R1.80-NSP 1

CHASSIS_GND_BS401

STDOFF-2.9OD0.888H-SM

STDOFF-2.9OD0.81H-SM

1

4 44

CHASSIS_GND_BS402

1

4

+/-0.1PF 2 16V NP0-C0G 01005

41 40 21

22 21

CHASSIS_GND_BS403

POWER GROUND

TP0421 1

PP5V0_USB

A

TP0415 1

PP_BATT_VCC

A

TP-P55

VBUS 45 39

5% 2 10V C0G-CERM 01005

TP0411 1

PP_LCM_BL_ANODE_CONN

C0402

53 28 27 26 25 23 21 19 18 10 9 46 41 40 39 37 35 34 33 31 30

A

VBATT

220PF

5% 2 10V C0G-CERM 01005

C0403 100PF

5% 2 16V NP0-C0G 01005

C0404

1

56PF

5% 2 25V NP0-C0G-CERM 01005

1

C0405 18PF

2% 2 16V CERM 01005

1

LCM BACKLIGHT SOURCE

ROOM=TEST

46 45

TP0417 1 LCM BACKLIGHT SINK3 A

PP_LCM_BL34_CAT1_CONN

TP-P55 ROOM=TEST

TP0408 1

PP_VDD_MAIN

A

TP-P55

46 45

TP0419 1

PP_LCM_BL34_CAT2_CONN

A

VDD_MAIN

TP-P55

C0406

FD0408

4PF

FID

+/-0.1PF 2 16V NP0-C0G 01005

LCM BACKLIGHT SINK4

ROOM=TEST

ROOM=TEST

1

D

TP-P55

TP-P55

1

LCM BACKLIGHT SINK2

ROOM=TEST

ROOM=TEST

CHASSIS_GND_BS401

220PF

A

ROOM=TEST

4

PTH per Rev63 for 1.8mm Drill

C0401

TP0410 1

PP_LCM_BL_CAT2_CONN

TP-P55

A

1

LCM BACKLIGHT SINK1

ROOM=TEST

45 39

TP0422 1

44 4

A

TP-P55

4PF

TP-P55

BS0403

TP0409 1

PP_LCM_BL_CAT1_CONN

ROOM=TEST

ROOM=TEST

BS0402

45 39

46 45

PP_LCM_BL34_ANODE_CONN

0P5SM1P0SQ-NSP 1 Note: Fiducial used as test point

TP0418 1 LCM BACKLIGHT SOURCE (3/4) A TP-P55 ROOM=TEST

ROOM=TEST

4

CHASSIS_GND_BS402 1

C0407 220PF

5% 2 10V C0G-CERM 01005

1

C0408 220PF

5% 2 10V C0G-CERM 01005

1

C0409 100PF

5% 2 16V NP0-C0G 01005

C0410

1

56PF

5% 2 25V NP0-C0G-CERM 01005

1

C0411 18PF

2% 2 16V CERM 01005

1

FIDUCIALS

C0412 4PF

+/-0.1PF 2 16V NP0-C0G 01005

DFU

C

C0417 220PF

5% 2 10V C0G-CERM 01005

1

C0418 220PF

5% 2 10V C0G-CERM 01005

TP-P55

C0419 100PF

5% 2 16V NP0-C0G 01005

C0420

1

56PF

5% 2 25V NP0-C0G-CERM 01005

1

C0421 18PF

2% 2 16V CERM 01005

1

ROOM=ASSEMBLY

FORCE DFU

ROOM=TEST

1

0P5SM1P0SQ-NSP 1

A

CHASSIS_GND_BS403 1

FID

TP0414 1

PMU_TO_AP_FORCE_DFU

20 12 4

FD0410

C

FD0409

C0422

FID

4PF

+/-0.1PF 16V 2 NP0-C0G 01005

0P5SM1P0SQ-NSP 1

E75 41 40

Front Shields

ROOM=ASSEMBLY

FD0405 FID

TP0402 1

90_TRISTAR_DP1_CONN_P

0P5SM1P0SQ-NSP 1

A

TP-P55

ROOM=ASSEMBLY

ROOM=TEST

41 40

FD0406

TP0403 1

90_TRISTAR_DP1_CONN_N

FID

0P5SQ-SMP3SQ-NSP 1

A

1

TP-P55

ROOM=ASSEMBLY

ROOM=TEST

SH0401 SM 41 40

90_TRISTAR_DP2_CONN_P

TP0404 1

FD0404

TP-P55

0P5SQ-SMP3SQ-NSP 1

FID

A

SHLD-UP-FRT-D11

ROOM=TEST 41 40

90_TRISTAR_DP2_CONN_N

ROOM=ASSEMBLY

TP0405 1

FD0403

TP-P55

0P5SQ-SMP3SQ-NSP 1

A

FID

ROOM=TEST

1

ROOM=ASSEMBLY

SH0403

41 40

TP0406 1

PP_TRISTAR_ACC1

TP-P55

SHLD-LOWER-FRT-D11

41 40

FID

0P5SQ-SMP3SQ-NSP 1

ACCESSORY ID AND POWER

ROOM=TEST

BS0404

FD0402

A

SM

ROOM=ASSEMBLY

TP0407 1

PP_TRISTAR_ACC2

FD0401

A

2.70R1.80-NSP

FID

TP-P55

1

0P5SQ-SMP3SQ-NSP 1

ROOM=TEST

B

TP0416 1 A

TP-P55 ROOM=TEST

Back Shields

FD0400

TP IS TO HELP WITH USB SI IN THE FACTORY FIXTURE.

FID

0P5SQ-SMP3SQ-NSP 1

ROOM=ASSEMBLY

41 40

TP0412 1

TRISTAR_CON_DETECT_L

A

TP-P55

FOR DIAGS

ROOM=TEST

1

FD0407

AMUX

SH0400

FID

0P5SM1P0SQ-NSP 1

SM

TP0413 1

PMU_AMUX_AY

20

A

SHLD-SOFT-UP-BK-D11

TP-P55

#25244799 100k to 200k 1

20

SH0402

TP0423 1

PMU_AMUX_BY

A

ROOM=TEST

FD0411

R0413

FID

200K

1% 1/32W MF 2 01005 ROOM=SOC

0P5SQ-SMP3SQ-NSP 1

ANALOG MUX B OUTPUT Note: Fiducial used as test point

ROOM=TEST

STDOFF-2.9OD0.888H-SM SHLD-SOFT-LOWER-BK-D11

ANALOG MUX A OUTPUT

ROOM=TEST

1

TP-P55

BS0405

SM

B

ROOM=ASSEMBLY

MOJAVE

1

BS0406

STDOFF-2.9OD1.9ID-0.85H-SM 38 37

MESA_TO_BOOST_EN

1

TP0400 1 A

TP-P55 ROOM=TEST

A

38 37

PP16V0_MESA

TP0401 1 A

SYNC_MASTER=sync

PAGE TITLE

TP-P55

CL0401 SM

SYSTEM:MECHANICAL COMPONENTS

ROOM=TEST

CLIP-COAX-RETENTION-D11

SYNC_DATE=05/17/2016

DRAWING NUMBER

1

Apple Inc.

051-00482 REVISION

8.0.0

R

TOP SIDE 8

7

6

5

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

4 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

4 OF 81

IV ALL RIGHTS RESERVED

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D

BOOTSTRAPPING:BOARD REV BOARD ID BOOT CONFIG NOSTUFF 12

BOARD_REV3

R0509 1ROOM=SOC 01005

MF

NOSTUFF

BOARD_REV2

R0505 1

BOARD_REV1

R0508 1

2

1/32W

5%

ROOM=SOC

12

01005

MF

2

01005

MF

MAKE_BASE=TRUE

PP1V8

7 8 9 11 12 13 16 17 18 25 29 30 39 46 47 48 52

1.00K

BOARD_REV[3:0]

1/32W

5%

ROOM=SOC

12

1.00K

2

FLOAT=LOW, PULLUP=HIGH

1.00K 1/32W

5%

NOSTUFF 12

BOARD_REV0

R0504 01005

ROOM=SOC

1 MF

2 1.00K 1/32W

5%

C

SELECTED -->

BOARD_ID4=No connect

11

BOARD_ID3

R0502 1ROOM=SOC 01005

MF

2

5%

11

BOARD_ID2 0=EUREKA, 1=KAROO

11

BOARD_ID1

R0503 01005

R0501

01005 0=FORM FACTOR A, 1=FORM FACTOR B

1 MF

1/32W

ROOM=SOC

1 MF

2 1.00K 1/32W

5%

C

BOARD_ID[4:0]

2 1.00K 1/32W

5%

Pre-Proto w/D520 (non enclosure) PROTO1 PROTO2 PROTO2.5 EVT SPARE CARRIER SPARE DVT SPARE PVT

1.00K

NOSTUFF ROOM=SOC

1111 1110 1101 1100 1011 xxxx 1000 xxxx 0010 xxxx 0000

SELECTED -->

BOARD_ID0=No connect

FLOAT=LOW, PULLUP=HIGH 01000 D10 MLB 01001 D10 DEV 01010 D11 MLB 01011 D11 DEV 01100 D101 MLB 01101 D101 DEV 01110 D111 MLB 01111 D111 DEV 0=MLB, 1=DEV 0=FORM FACTOR A, 1=FORM FACTOR B 0=EUREKA, 1=KAROO

12

MAKE_BASE=TRUE

PP1V8

BOOT_CONFIG1=No connect

BOOT_CONFIG0=No connect

BOOT_CONFIG[2:0]

B

SELECTED -->

B

FLOAT=LOW, PULLUP=HIGH 000 SPI0 001 SPI0 TEST MODE 010 NVME0_X2 011 NVME0 X2 TEST 100 NVME0 X1 101 NVME0 X1 TEST 110 SLOW SPI0 TEST 111 FAST SPI0 TEST

A

SYNC_MASTER=david-copy

SYNC_DATE=03/01/2016

PAGE TITLE

SYSTEM: BOARDID DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

5 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

5 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

spare DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

6 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

6 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

SOC - USB, JTAG, XTAL

2

1

VDD18_USB: 1.71-1.89V @20mA MAX

PP1V8 1

5 7 8 9 11 12 13 16 17 18 25 29 30 39 46 47 48 52

C0700 0.1UF

20% 2 6.3V X5R-CERM 01005

ROOM=SOC

D

D

VDD11_XTAL:1.06-1.17V @TBD mA

FL0700

MAX

240-OHM-25%-0.20A-0.9DCR PP1V1_XTAL

1 1

PP1V1

2 01005

C0704

1

ROOM=SOC

0.1UF

20% 2 6.3V X5R-CERM 0201-1

ROOM=SOC

ROOM=SOC

MAX

PP3V3_USB 25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 30 29

C0705 2.2UF

20% 2 6.3V X5R-CERM 01005

VDD18_AMUX: 1.62-1.98V @1mA

15 18

PP1V8

1

C0701

19 30

3.14-3.46V @20mA MAX

0.1UF

20% 6.3V 2 X5R-CERM 01005

ROOM=SOC

CKPLUS_WAIVE=PWRTERM2GND

VDD33_USB CG26

VDD_FIXED_USB CC25

U0700

VDD11_XTAL CG50

VDD18_USB CE25

C

VDD18_AMUX AJ60

VDD12_UH1_HSIC0 CL20

PP0V9_SOC_FIXED

8 9 10 15 18

tbd - tbd V @5mA MAX

C

CAYMAN-2GB-20NM-DDR-M CSP SYM 1 OF 16

ANALOGMUX_OUT N64

CM22 UH1_HSIC0_DATA NC CM20 UH1_HSIC0_STB NC

Dev ONLY

USB_DP CM26 USB_DM CL26

CL31 JTAG_SEL

40 40

20 13

40 37 20 13

PP0701 P2MM-NSM

B

SM

PP

20

CL29 NC CG37 NC CJ35 NC CK33 CH37

SWD_DOCK_BI_AP_SWDIO SWD_DOCK_TO_AP_SWCLK PMU_TO_SYSTEM_COLD_RESET_L

AP_TO_PMU_AMUX_OUT

90_USB_AP_DATA_P 90_USB_AP_DATA_N

20

40 40

OMIT_TABLE

JTAG_TRST* JTAG_TDO JTAG_TDI JTAG_TMS JTAG_TCK

USB_VBUS CH26

USB_VBUS_DETECT

21

USB_ID CJ26NC

CM14 COLD_RESET*

PMU_TO_AOP_TRISTAR_ACTIVE_READY

BJ3 CFSB

AP_TO_PMU_TEST_CLKOUT

BJ2 TST_CLKOUT

USB_REXT CK26

AP_USB_REXT 1

1% 1/32W MF 2 01005

BL65 S3E_RESET*

AP_TO_NAND_RESET_L

B

200

1 17

R0700 ROOM=SOC

WDOG CK35

BJ4 HOLD_RESET

AP_TO_PMU_WDOG_RESET

20

XTAL_AP_24M_IN XTAL_AP_24M_OUT

1

BL3 TESTMODE XI0 CM42 XO0 CL42

R0701

CRITICAL ROOM=SOC

511K

1% 1/32W MF 2 01005

ROOM=SOC

Y0700

1.60X1.20MM-SM

R0702 1

0.00 0% 1/32W MF 01005 ROOM=SOC

24.000MHZ-30PPM-9.5PF-60OHM

2

SOC_24M_O 1

C0702 12PF

5% 16V 2 CERM 01005

ROOM=SOC

1 2

3 4 1

C0703 12PF

2

5% 16V CERM 01005 ROOM=SOC

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SOC:JTAG,USB,XTAL DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

7 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

7 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

SOC - PCIE INTERFACES R0804 1

0.00

2

0% 1/32W MF 01005 ROOM=SOC

VDD12_PCIE_REFBUF:1.08-1.26V @40mA

MAX

PP1V2_SOC_PCIE_REFBUF 1

C0802 0.1UF

20% 2 6.3V X5R-CERM 01005

VDD_FIXED_PCIE_xxx:0.855-0.990V @225mA MAX

ROOM=SOC

PP0V9_SOC_FIXED

D

R0803

5 7 9 11 12 13 16 17 18 25 29 30 39 46 47 48 52

17 17

BW55 CC47

CC53 CC62 CE55 CE60

20% 2 6.3V X5R-CERM 01005

0% 1/32W MF 01005

C0804 0.1UF

20% 2 6.3V X5R-CERM 01005

VDD_FIXED_PCIE_REFBUF

0.1UF

2

C0800

1

1.0UF

2.2UF

20% 2 6.3V X5R 0201-1

ROOM=SOC

D

C0806

2

20% 6.3V X5R-CERM 0201-1 ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

CAYMAN-2GB-20NM-DDR-M CSP

5% 1/32W MF 2 01005

ROOM=SOC

PCIE_NAND_BI_AP_CLKREQ_L

0.00

1

U0700

R0805 100K

17

1

1

C0803

90_PCIE_AP_TO_NAND_REFCLK_P 90_PCIE_AP_TO_NAND_REFCLK_N

SYM 2 OF 16

BC64

PCIE_CLKREQ0*

CJ48 CK48

PCIE_REF_CLK0_P PCIE_REF_CLK0_N

PCIE_CLKREQ3*

BE66

PCIE_WLAN_BI_AP_CLKREQ_L

PCIE_REF_CLK3_P PCIE_REF_CLK3_N

CL64 CM64

90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N

52

52 52

PCIE LINK 3

1

ROOM=SOC

VDD_FIXED_PCIE_ANA

20% 6.3V 2 X5R-CERM 01005

ROOM=SOC

PP1V8

C0801

0.1UF

20% 6.3V X5R-CERM 0201-1

VDD_FIXED_PCIE_CLK

C0805 2.2UF

CA55 CA60

2

1

CC49 CE49

1

VDD12_PCIE_REFBUF

VDD12_PCIE: 1.14-1.26V @10mA MAX

PP1V2_SOC

VDD12_PCIE CE58

19 16 10

PP0V9_SOC_FIXED_PCIE_REFBUF

1

7 9 10 15 18

#24557655:replace with 20% caps. SI no negative impact

C

C0807 20%1

ROOM=SOC

PCIE LINK 0

17

90_PCIE_NAND_TO_AP_RXD_P 90_PCIE_NAND_TO_AP_RXD_N

X5R 1 ROOM=SOC 20% X5R D10 NAND is now Gen3 (was Gen2). Caps 1 ROOM=SOC 20% X5R 1 20% ROOM=SOC X5R

C0808 C0809

17

90_PCIE_AP_TO_NAND_TXD_P 90_PCIE_AP_TO_NAND_TXD_N

17

PCIE_AP_TO_NAND_RESET_L

17

1

C0810

CM46 CL46

PCIE_RX0_P PCIE_RX0_N

PCIE_RX3_P PCIE_RX3_N

CM61 CL61

90_AP_PCIE3_RXD_C_P 90_AP_PCIE3_RXD_C_N

CK44 CJ44

PCIE_TX0_P PCIE_TX0_N

PCIE_TX3_P PCIE_TX3_N

CK63 CJ63

90_AP_PCIE3_TXD_C_P 90_AP_PCIE3_TXD_C_N

BJ65

PCIE_PERST0*

PCIE_PERST3*

BJ66

52 52

52 52

PCIE_AP_TO_WLAN_RESET_L 52 1

R0802 LINK0

100K BG66 NC CL54 NC CM54 NC

PCIE_CLKREQ1* PCIE_REF_CLK1_P PCIE_REF_CLK1_N

R0806 100K

LINK3

5% 1/32W MF 2 01005 ROOM=SOC

5% 1/32W MF 2 01005

ROOM=SOC

PCIE_CLKREQ2*

BE65

PCIE_BB_BI_AP_CLKREQ_L

PCIE_REF_CLK2_P PCIE_REF_CLK2_N

CK59 CJ59

90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N

52

52 52

B

PCIE LINK 1

WLAN RX PP's are now managed on Page 52 CK52 NC CJ52 NC

PCIE_RX1_P PCIE_RX1_N

CM50 NC CL50 NC BG64 NC

PCIE_TX1_P PCIE_TX1_N

PCIE_RX2_P PCIE_RX2_N

CK56 CJ56

90_AP_PCIE2_RXD_C_P 90_AP_PCIE2_RXD_C_N

52 52

LINK 1 USED ON AP_DEV ONLY

PCIE_PERST1* LINK1

CH57 CG57

C

PCIE LINK 2

17

2 GND_VOID=TRUE 0.22UF 6.3V 01005 90_PCIE_NAND_TO_AP_RXD_C_P 2 GND_VOID=TRUE 0.22UF 90_PCIE_NAND_TO_AP_RXD_C_N 6.3V 01005 intentionally 0.22uF 2 GND_VOID=TRUE 0.22UF 6.3V 01005 90_PCIE_AP_TO_NAND_TXD_C_P 2 GND_VOID=TRUE 0.22UF 90_PCIE_AP_TO_NAND_TXD_C_N 6.3V 01005

PCIE_TX2_P PCIE_TX2_N

CM57 CL57

PCIE_PERST2*

BE64

90_AP_PCIE2_TXD_C_P 90_AP_PCIE2_TXD_C_N

52 52

PCIE_AP_TO_BB_RESET_L52

LINK2

1

PCIE_EXT_REF_CLK_P PCIE_EXT_REF_CLK_N

2

PCIE_REXT

CG63

B

R0801 100K 5% 1/32W MF 01005

ROOM=SOC

AP_PCIE_RCAL 1

2

R0800 3.01K 1% 1/32W MF 01005

ROOM=SOC

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SOC:PCIE DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

8 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

8 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

SOC - MIPI & ISP INTERFACES D

0.825-0.94V @25mA MAX

PP1V8

PP0V9_SOC_FIXED 0.1UF

20% 2 6.3V X5R-CERM 01005

C0900

1

2.2UF

C0901 2.2UF

20% 2 6.3V X5R-CERM 0201-1

20% 2 6.3V X5R-CERM 0201-1

ROOM=SOC

1

C0903 0.1UF

20% 2 6.3V X5R-CERM 01005

ROOM=SOC

VDD_FIXED_MIPI

ROOM=SOC

1

5 7 8 11 12 13 16 17 18 25 29 30 39 46 47 48 52

ROOM=SOC

VDD18_MIPI

C0902

G10 G15 G19 G21

1

G13 G17 G6

18 15 10 8 7

D

1.62-1.98V @7mA MAX

U0700 CAYMAN-2GB-20NM-DDR-M CSP 45 45

45 45

ISP_I2C0_SCL N65 ISP_I2C0_SDA N66

I2C_ISP_UT_SCL I2C_ISP_UT_SDA

MIPI0C_DPDATA1 MIPI0C_DNDATA1

ISP_I2C1_SCL U64 ISP_I2C1_SDA R65

I2C_ISP_NV_SCL I2C_ISP_NV_SDA

C24 NC B24 NC

MIPI0C_DPDATA2 MIPI0C_DNDATA2

ISP_I2C2_SCL U65 ISP_I2C2_SDA U66

I2C_ISP_NH_SCL I2C_ISP_NH_SDA

A26 NC B26 NC

MIPI0C_DPDATA3 MIPI0C_DNDATA3

ISP_I2C3_SCL W64 NC ISP_I2C3_SDA W66 NC

90_MIPI_NH_TO_AP_DATA0_P 90_MIPI_NH_TO_AP_DATA0_N

A18 B18

MIPI0C_DPDATA0 MIPI0C_DNDATA0

90_MIPI_NH_TO_AP_DATA1_P 90_MIPI_NH_TO_AP_DATA1_N

B20 C20

C

SYM 3 OF 16

48 48

30 46 30 46

48 48

1 45 45

B22 A22

90_MIPI_NH_TO_AP_CLK_P 90_MIPI_NH_TO_AP_CLK_N MIPI0C_REXT

E24

MIPI0C_DPCLK MIPI0C_DNCLK

33.2

2

NOSTUFF

1% 1/32W MF 01005

SENSOR_INT AA64NC

MIPI0C_REXT

C

R0906

Dev ONLY

1

25

AP_TO_NH_CLK

29

C0906 100PF

5% 2 35V NP0-C0G 01005

ROOM=SOC

Spare

AP_TO_UT_CLK

R0900 1 4.02K

1% 1/32W MF 01005 2 ROOM=SOC

39 39

39 39

B4 A4

90_MIPI_AP_TO_LCM_DATA0_P 90_MIPI_AP_TO_LCM_DATA0_N

B5 C5

90_MIPI_AP_TO_LCM_DATA1_P 90_MIPI_AP_TO_LCM_DATA1_N

SENSOR0_CLK B50 SENSOR1_CLK A48 SENSOR2_CLK C48

MIPID_DPDATA0 MIPID_DNDATA0

AP_TO_UT_CLK_R AP_TO_NV_CLK_R AP_TO_NH_CLK_R

R0907

D11/111 ONLY

30

1

MIPID_DPDATA1 MIPID_DNDATA1

33.2 1% 1/32W MF 01005

ROOM=SOC 46 46

C9 B9

90_MIPI_AP_TO_LCM_DATA2_P 90_MIPI_AP_TO_LCM_DATA2_N

SENSOR0_RST SENSOR1_RST SENSOR2_RST SENSOR3_RST SENSOR4_RST

MIPID_DPDATA2 MIPID_DNDATA2

D11/111 ONLY 46 46

39 39

B

26 36

A11 B11

90_MIPI_AP_TO_LCM_DATA3_P 90_MIPI_AP_TO_LCM_DATA3_N

B7 A7

90_MIPI_AP_TO_LCM_CLK_P 90_MIPI_AP_TO_LCM_CLK_N AP_TO_STROBE_DRIVER_HWEN SPI_AP_TO_MAGGIE_CS_L NC

MIPID_REXT

MIPID_DPDATA3 MIPID_DNDATA3

A50 E50 AA65 AE64 AC65 NC

SENSOR0_ISTRB E52 SENSOR1_ISTRB D50 NC

MIPID_DPCLK MIPID_DNCLK

BN4 BR2

DISP_TOUCH_BSYNC0 DISP_TOUCH_BSYNC1

BR4

DISP_TOUCH_EB

E11

MIPID_REXT

SENSOR0_XSHUTDOWN C50 NC SENSOR1_XSHUTDOWN B48

AP_TO_UT_SHUTDOWN_L AP_TO_NV_SHUTDOWN_L AP_TO_NH_SHUTDOWN_L TP_SENSOR3_RST

25

2

NOSTUFF 1

C0907 100PF

5% 2 35V NP0-C0G 01005

D11/111 ONLY

30 29

1

PP

SM

PP0902 P2MM-NSM

Radar 20511449 <--- Needed for Cayman debug; this pin cannot be input

ROOM=SOC

NC_SENSOR0_ISTRB

B

AP_TO_MUON_BL_STROBE_EN

37 46

MIPI1C_REXT E16 MIPI1C_DPDATA0 B12 MIPI1C_DNDATA0 C12

R0901 1 4.02K

MIPI1C_DPDATA1 B16 MIPI1C_DNDATA1 C16

1% 1/32W MF 01005 2 ROOM=SOC

Dev only

MIPI1C_DPCLK B14 MIPI1C_DNCLK A14

Per Radar 21221938

A

53 28 27 26 25 23 21 19 18 10 4 46 41 40 39 37 35 34 33 31 30

PP_VDD_MAIN

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

1

C0904

1

220PF

C0905 220PF

5% 2 10V C0G-CERM 01005

5% 2 10V C0G-CERM 01005

1

C0908 220PF

5% 10V 2 C0G-CERM 01005

1

C0909 220PF

5% 2 10V C0G-CERM 01005

1

SOC:MIPI AND ISP

C0910 220PF

DRAWING NUMBER

5% 2 10V C0G-CERM 01005

Apple Inc.

ROOM=SOC ROOM=SOC

ROOM=SOC

ROOM=SOC

051-00482 REVISION

8.0.0

R

ROOM=SOC

AC return path for LCM MIPI which is referenced to GND and VDD_MAIN Radar 21203307

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

9 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

9 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D 1

C1013 2.2UF

20% 2 6.3V X5R-CERM 0201-1

1

C1001 2.2UF

20% 2 6.3V X5R-CERM 0201-1 ROOM=SOC

C1004

1

0.1UF

C1005

1

0.01UF

20% 2 6.3V X5R-CERM 01005

CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND

15PF

10% 2 6.3V X5R 01005

ROOM=SOC

C1002

5% 2 16V NP0-C0G-CERM 01005

ROOM=SOC

ROOM=SOC Desense for Wifi frequencies

VDD12_LPDP_RX

VDD12_LPDP_TX

ROOM=SOC

1

VDD12_PLL_LPDP G23

PP1V2_SOC

G25 G28 G30 G55 G58 G60 G62

19 16 8

VDD12_PLL_LPDP:1.14-1.26V @3mA MAX VDD12_LPDP:1.14-1.26V @60mA MAX

U0700 CAYMAN-2GB-20NM-DDR-M CSP 30 30

30 30

LPDP_TX0P B27 NC LPDP_TX0N C27 NC

90_LPDP_NV_TO_AP_D0_P 90_LPDP_NV_TO_AP_D0_N

A54 LPDPRX_RX_D0_P B54 LPDPRX_RX_D0_N

90_LPDP_NV_TO_AP_D1_P 90_LPDP_NV_TO_AP_D1_N

B56 LPDPRX_RX_D1_P C56 LPDPRX_RX_D1_N

LPDP_TX1P A29 NC LPDP_TX1N B29 NC

90_LPDP_UT_TO_AP_D2_P 90_LPDP_UT_TO_AP_D2_N

A61 LPDPRX_RX_D2_P B61 LPDPRX_RX_D2_N

LPDP_TX2P B31 NC LPDP_TX2N C31 NC

90_LPDP_UT_TO_AP_D3_P 90_LPDP_UT_TO_AP_D3_N

B63 LPDPRX_RX_D3_P C63 LPDPRX_RX_D3_N

LPDP_TX3P A33 NC LPDP_TX3N B33

C

SYM 4 OF 16

Dev ONLY

C

LPDP Lanes swapped between D10 and D11 25 25

D11/111 ONLY 25 25

A64 LPDPRX_RX_D4_P B64 LPDPRX_RX_D4_N

GND ON MLB; other on Dev

D11/111 ONLY

30

LPDP_NV_BI_AP_AUX

25

LPDP_UT_BI_AP_AUX

D54 E56 NC D61 E63 NC D64 NC

LPDP_AUX_P D33 NC LPDP_AUX_N E33 NC

LPDPRX_AUX_D0_P LPDPRX_AUX_D1_P LPDPRX_AUX_D2_P LPDPRX_AUX_D3_P LPDPRX_AUX_D4_P

LPDP_CAL_DRV_OUT E35 NC LPDP_CAL_VSS_EXT E31 NC EDP_HPD BN3 NC DP_WAKEUP AP2 NC

B59 LPDPRX_BYP_CLK_P C59 LPDPRX_BYP_CLK_N

GND ON MLB; other on Dev

B 18 15 9 8 7

PP0V9_SOC_FIXED

A57 LPDPRX_RCAL_P

AP_LPDPRX_RCAL_NEG

B57 LPDPRX_RCAL_N

Reserved for PanelID[1:0] on ap_dev board Reserved for PanelID[1:0] on ap_dev board

B

R1001 1 300

1% 1/32W MF 01005-1 2 ROOM=SOC

C1006

1

100PF

NC

5% 16V NP0-C0G 2 01005 ROOM=SOC

A

D57 LPDPRX_EXT_C

#24401637:Unconnect LPDPRX_EXT_C

53 28 27 26 25 23 21 19 18 9 4 46 41 40 39 37 35 34 33 31 30

PP_VDD_MAIN SYNC_MASTER=Sync

1

C1010 33PF

1

SYNC_DATE=06/06/2016

PAGE TITLE

C1011

SOC:LPDP

33PF

5% 2 16V NP0-C0G-CERM 01005

5% 2 16V NP0-C0G-CERM 01005

ROOM=SOC

ROOM=SOC

DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

AC return path for LCM LPDP which is referenced to GND and VDD_MAIN

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

10 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

10 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

SOC - SERIAL INTERFACES D

D R1103 32

I2S_AP_TO_CODEC_MCLK

33.2

1

2

1% 1/32W MF 01005

32

ROOM=SOC

32

32

32

BV65 BY66 BU64 BR64 BU65

I2S_AP_TO_CODEC_MCLK_R I2S_AP_TO_CODEC_MSP_BCLK I2S_AP_TO_CODEC_MSP_LRCLK I2S_CODEC_TO_AP_MSP_DIN I2S_AP_TO_CODEC_MSP_DOUT I2S1/2/3 MCLK NC #24559456

53 53 53 53

36 35 34 33 32 36 35 34 33 32 36 36

C

53 53 53 53

I2S0_MCK I2S0_BCLK I2S0_LRCK I2S0_DIN I2S0_DOUT

I2S_AP_TO_BT_BCLK I2S_AP_TO_BT_LRCLK I2S_BT_TO_AP_DIN I2S_AP_TO_BT_DOUT

D48 NC E48 A46 C46 E46

I2S1_MCK I2S1_BCLK I2S1_LRCK I2S1_DIN I2S1_DOUT

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK I2S_MAGGIE_TO_AP_DIN I2S_AP_TO_MAGGIE_DOUT

BU66 NC BR66 BN64 BN65 BJ64

I2S2_MCK I2S2_BCLK I2S2_LRCK I2S2_DIN I2S2_DOUT

I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_LRCLK I2S_BB_TO_AP_DIN I2S_AP_TO_BB_DOUT

CH11 NC CM7 CK9 CG18 CJ9

I2S3_MCK I2S3_BCLK I2S3_LRCK I2S3_DIN I2S3_DOUT

U0700

I2C0_SCL CK7 I2C0_SDA CG12

I2C0_AP_SCL I2C0_AP_SDA

I2C1_SCL AG64 I2C1_SDA AG66

I2C1_AP_SCL I2C1_AP_SDA

I2C2_SCL U3 I2C2_SDA U4

I2C2_AP_SCL I2C2_AP_SDA

I2C3_SCL AE66 I2C3_SDA AE65

I2C3_AP_SCL I2C3_AP_SDA

5

BOARD_ID2 BOARD_ID1 BOARD_ID0

5

R1116 36 32

SPI_AP_TO_CODEC_MAGGIE_SCLK

1

Route as daisy-chain. No T's allowed.

0.00

36 32 36 32

2

0% 1/32W MF 01005

32

BOARD_ID3

CB2 BY4 BY3 NC CB4

N2 N3 N4 R3

SPI_CODEC_MAGGIE_TO_AP_MISO SPI_AP_TO_CODEC_MAGGIE_MOSI SPI_AP_TO_CODEC_MAGGIE_SCLK_R SPI_AP_TO_CODEC_CS_L

CSP SYM 6 OF 16

39

SPI_AP_TO_TOUCH_SCLK

1

0.00 0% 1/32W MF 01005

39 39

2 39

SPI_TOUCH_TO_AP_MISO SPI_AP_TO_TOUCH_MOSI SPI_AP_TO_TOUCH_SCLK_R SPI_AP_TO_TOUCH_CS_L

C44 B44 A44 D44

47

47 47

47 47

C I2C5_SCL I2C5_SDA

11 47 11 47

GPIO_42 CH20NC GPIO_43 CH22NC

SPI0_MISO SPI0_MOSI SPI0_SCLK SPI0_SSIN

PP1V8 1

R1113 10K 5% 1/32W MF 01005

2 ROOM=SOC

SPI1_MISO SPI1_MOSI SPI1_SCLK SPI1_SSIN

PMU_SCLK AH65 PMU_MISO AH66 PMU_MOSI AK64 DWI_CLK AK65 DWI_DO AM64

SPI2_MISO SPI2_MOSI SPI2_SCLK SPI2_SSIN

SPI_PMGR_TO_PMU_SCLK SPI_PMU_TO_PMGR_MISO SPI_PMGR_TO_PMU_MOSI

38 38 38 38

SPI_MESA_TO_AP_MISO SPI_AP_TO_MESA_MOSI SPI_AP_TO_MESA_SCLK MESA_TO_AP_INT

SPI3_MISO SPI3_MOSI SPI3_SCLK SPI3_SSIN

R1114 10K 5% 1/32W MF 01005

2 ROOM=SOC

20 20

DWI_PMGR_TO_BACKLIGHT_CLK DWI_PMGR_TO_BACKLIGHT_DATA

37 46 37 46

PMU_TO_AP_PRE_UVLO_L PMU_TO_AP_THROTTLE_GPU_L

SOCHOT AG4 B42 A42 E44 C42

1

5 7 8 9 11 12 13 16 17 18 25 29 30 39 46 47 48 52

20

DROOP AE3 GPU_TRIGGER BY2

ROOM=SOC

B

47

SPI4_SCLK CJ12NC SPI4_MISO CG22NC SPI4_MOSI CM9 NC

ROOM=SOC

R1101

47

CAYMAN-2GB-20NM-DDR-M

I2C5_SCL CH16 I2C5_SDA CJ14

5

47

20 20

AP_TO_PMU_SOCHOT_L

CLK32K_OUT AM66

AP_TO_CUMULUS_CLK32K

NAND_SYS_CLK BN66

AP_TO_NAND_SYS_CLK_R

20

B

39

1

0.00

R1118

2

AP_TO_NAND_SYS_CLK

17

0% 1/32W MF 01005 ROOM=SOC

I2C5 See Radar#25316444 for Details PP1V8 1

A1

25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 30 29

C1101 1.0UF

20% 6.3V 2 X5R 0201-1

VCC

U1101

ROOM=SOC

B1

A

SCL

WLCSP

SDA

A2

I2C5_SDA I2C5_SCL

11 47 11 47

To Cayman

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SOC:SERIAL

B2

VSS ROOM=SOC CRITICAL

DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

11 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

11 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

.

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D

SOC - GPIO INTERFACES

27 36

#24557547:Delete R1204

44 20

AP_TO_ACC_BUCK_VSEL

AP_TO_MAGGIE_CRESETB_L BUTTON_VOL_UP_L DEV ONLY

53

AP_TO_BB_RESET_L

MAGGIE_TO_AP_CDONE

36

RESERVERD FOR SSHB ID ON DEV BOARD D101/D111 ONLY D101/D111 ONLY

C

53

D101/D111 ONLY

NC_AP_TO_BB_IPC_GPIO2 NC_AP_TO_GNSS_WAKE AP_TO_BB_TIME_MARK NC_AP_TO_GNSS_TIME_MARK

BB_TO_AP_RESET_DETECT_L 33 AP_TO_SPKAMP2_RESET_L 29 ALS_TO_AP_INT_L 53

29 25 18 17 16 13 11 9 8 7 5 52 48 47 46 39 30

PP1V8

NOSTUFF 1 Nostuff per #24511702

R1210 10K

53

5% 1/32W MF 01005

17 39

AP_TO_NFC_FW_DWLD_REQ

AP_TO_NAND_FW_STRAP TOUCH_TO_AP_INT_L

2 ROOM=SOC 20

BOOT_CONFIG0

PMU_TO_AP_THROTTLE_CPU_L #24608280 53

D10/D11 ONLY

53 39 36

AP_TO_BBPMU_RADIO_ON_L AP_TO_ICEFALL_FW_DWLD_REQ AP_TO_LCM_RESET_L AP_BI_HOMER_BOOTLOADER_ALIVE BOOT_CONFIG1

20 4

Dev only 5

PMU_TO_AP_FORCE_DFU NC_DFU_STATUS PP1V8 BOARD_ID4

53

53 53

AP_TO_BB_IPC_GPIO1

53 53 5 5

B

AP_TO_NFC_DEV_WAKE

PMU_TO_AP_BUF_RINGER_A AP_TO_BT_WAKE AP_TO_WLAN_DEVICE_WAKE BOARD_REV3 BOARD_REV2 BOARD_REV1 BOARD_REV0 AP_TO_TOUCH_MAMBA_RESET_L AP_TO_BB_MESA_ON AP_TO_BB_COREDUMP

20

5 5 39 53

20 20

BB64 NC BC65 BB66 AY65 AY66 NC AV65 AV67 AT67 AT66 AT64 AP66 AP65 AH64 AE4 AC3 AE2 BB2 BB4 BC3 NC BC4 BE2 NC BE4 BE3 BG2 CJ11 CL9 NC CH14 CK11 CG20 AA2 NC AA3 D42 E42 A41 C41 E41 A39 AT4 AT2 AV3 AY2 AY3 BU2 BU3

PMU_TO_AP_BUF_POWER_KEY_L PMU_TO_AP_BUF_VOL_DOWN_L

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 GPIO_32 GPIO_33 GPIO_34 GPIO_35 GPIO_36 GPIO_37 GPIO_38 GPIO_39 GPIO_40 GPIO_41

U0700 CAYMAN-2GB-20NM-DDR-M CSP SYM 5 OF 16

TMR32_PWM0 AG2 NC PROX_BI_AP_AOP_INT_PWM_L TMR32_PWM1 AH4 AH3 TMR32_PWM2 NC_BB_TO_AP_RESET_ACT_L UART0_RXD CL5 UART0_TXD CJ7

UART_AP_DEBUG_RXD UART_AP_DEBUG_TXD

UART1_CTS* UART1_RTS* UART1_RXD UART1_TXD

E39 D39 C39 B39

UART_BT_TO_AP_CTS_L UART_AP_TO_BT_RTS_L UART_BT_TO_AP_RXD UART_AP_TO_BT_TXD

UART2_CTS* UART2_RTS* UART2_RXD UART2_TXD

AM4 AK3 AK4 AH2

NC_AP_UART2_CTS_L NC_AP_UART2_RTS_L NC_AP_UART2_RXD NC_AP_UART2_TXD

UART3_CTS* UART3_RTS* UART3_RXD UART3_TXD

AA4 W2 W4 U2

UART_NFC_TO_AP_CTS_L UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_RXD UART_AP_TO_NFC_TXD

UART4_CTS* UART4_RTS* UART4_RXD UART4_TXD

D37 C37 B37 A37

UART_WLAN_TO_AP_CTS_L UART_AP_TO_WLAN_RTS_L UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_TXD

UART5_RTXD BG4

SWI_AP_BI_TIGRIS

13 29

D101/D111 ONLY

C

40 40

53 53 53 53

D101/D111 ONLY; for GNSS

53 53 53 53

53 53 53 53

21

B UART6_RXD CG16 UART6_TXD CG14

UART_ACCESSORY_TO_AP_RXD UART_AP_TO_ACCESSORY_TXD

UART7_RXD AP3 UART7_TXD AM2

UART_HOMER_TO_AP_RXD UART_AP_TO_HOMER_TXD

40 40

36 36

REQUEST_DFU1 REQUEST_DFU2

#25120460:REQUEST_DFU Assignment

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SOC:GPIO & UART DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

12 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

12 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

SOC - AOP D

D

PP1V8 5 7 8 9 11 12 16 17 18 25 29 30 39 46 47 48 52

1

U0700 CAYMAN-2GB-20NM-DDR-M

2

CSP CM16 CM29

AOP_DDR_REQ AOP_DDR_RESET*

SPI_AOP_TO_COMPASS_CS_L COMPASS_TO_AOP_INT PROX_BI_AP_AOP_INT_PWM_L ACCEL_GYRO_TO_AOP_DATARDY SPI_AOP_TO_ACCEL_GYRO_CS_L ACCEL_GYRO_TO_AOP_INT SPI_AOP_TO_PHOSPHORUS_CS_L LCM_TO_MANY_BSYNC TRISTAR_TO_AOP_INT AOP_TO_MAGGIE_EN

AUDIO_TO_AOP_INT_L AOP_TO_MESA_I2C_ISO_EN PMU_TO_AOP_IRQ_L

CK12 CK16 CK18 CJ29 CG31 CH31 CK20 CJ31 CK27 CK24 CK29 CK22 CM12 CK31 CG33 CJ33

AOP_FUNC_0 AOP_FUNC_1 AOP_FUNC_2 AOP_FUNC_3 AOP_FUNC_4 AOP_FUNC_5 AOP_FUNC_6 AOP_FUNC_7 AOP_FUNC_8 AOP_FUNC_9 AOP_FUNC_10 AOP_FUNC_11 AOP_FUNC_12 AOP_FUNC_13 AOP_FUNC_14 AOP_FUNC_15

I2C_AOP_SCL I2C_AOP_SDA

CM11 CJ24

AOP_I2C0_SCL AOP_I2C0_SDA

CJ18 CJ27 CJ16

AOP_SPI_MISO AOP_SPI_MOSI AOP_SPI_SCLK

UART_BB_TO_AOP_RXD UART_AOP_TO_BB_TXD

CK14 CJ20

AOP_UART0_RXD AOP_UART0_TXD

MAGGIE_TO_AOP_INT UART_AOP_TO_MAGGIE_TXD

CJ22 CL11

AOP_UART1_RXD AOP_UART1_TXD

UART_TOUCH_TO_AOP_RXD UART_AOP_TO_TOUCH_TXD

CG29 CH29

AOP_UART2_RXD AOP_UART2_TXD

32

I2S_CODEC_XSP_TO_AOP_BCLK I2S_CODEC_XSP_TO_AOP_DIN I2S_AOP_TO_MAGGIE_L26_MCLK_R I2S_CODEC_XSP_TO_AOP_LRCLK

CL35 CJ39 CM35 CK37

AOP_I2S_BCLK AOP_I2S_DIN AOP_I2S_MCK AOP_I2S_LRCK

DOCK_ATTENTION CG41

32

I2S_AOP_TO_CODEC_XSP_DOUT

CG39

AOP_I2S_DOUT

DOCK_CONNECT CL37

20 15

#24512059: Remove R1300 PU

24 24

Use internal pullup in SOC (AOP side).

29 12 24 24 24

C

24 53 39 23 20 40 36 24 24 24 35 34 33 32 48

Plan to use internal pullup in AOP.

Radar 21210869

20

48 48

#25756894:North Carbon R1

24

SPI_AOP_TO_IMU_SCLK_R1

24

49.9 2

1

1% 1/32W MF 01005

#25756894:South Carbon R2

24

SPI_AOP_TO_IMU_SCLK_R2

53

ROOM=SOC

53

R1306

36

49.9 2

1

PHOSPHORUS_TO_AOP_INT_L SPI_AOP_TO_BOT_ACCEL_GYRO_CS_L BOT_ACCEL_GYRO_TO_AOP_DATARDY

SPI_IMU_TO_AOP_MISO SPI_AOP_TO_IMU_MOSI 24 SPI_AOP_TO_IMU_SCLK

R1305

36

1% 1/32W MF 01005

SYM 7 OF 16

AOP_TO_PMU_SLEEP1_REQUEST PMU_TO_AOP_SLEEP1_READY

20

39 39

CFSB_AOP CH35 AWAKE_REQ CM31 AWAKE_RESET* CJ37 AOP_PDM_CLK0 CM37 AOP_PDM_DATA0 CH41 AOP_PDM_DATA1 CK39 RT_CLK32768 CM33 AOP_SWD_TCK_OUT CL14 AOP_SWD_TMS0 AOP_SWD_TMS1 SWD_TMS2 SWD_TMS3

CL16 CG35 BU4 BV3

NOSTUFF

R1304 1.00K 5% 1/32W MF 01005

ROOM=SOC

PMU_TO_SYSTEM_COLD_RESET_L

7 20

AOP_TO_PMU_ACTIVE_REQUEST PMU_TO_AOP_TRISTAR_ACTIVE_READY

20 7 20 37 40

AOP_TO_MESA_BLANKING_EN AOP_TO_WLAN_CONTEXT_B AOP_TO_WLAN_CONTEXT_A

38 53 53

PMU_TO_AOP_CLK32K

20

SWD_AP_TO_MANY_SWCLK

17 36 53

HOMER_TO_AOP_WAKE_INT SWD_AOP_BI_BB_SWDIO SWD_AP_BI_NAND_SWDIO SWD_AP_BI_HOMER_SWDIO

C

36 53

BB_SWDIO has pullup in Radio_MLB pages

17 36

ROOM=SOC

B

R1303 36 35 34 33

I2S_AOP_TO_MAGGIE_L26_MCLK

1

33.2 1% 1/32W MF 01005

32 32

2

B

ROOM=SOC

AOP_TO_SPKAMP1_ARC_RESET_L MESA_TO_AOP_FDINT

34 35

38

DOCK_CONNECT can be GPIO, but input only. Radar 21680759

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SOC:AOP DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

13 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

13 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

SOC - CPU, GPU & SOC RAILS PP_CPU_VAR 14 18

PP1401

SM

P2MM-NSM

PP

PP_GPU_VAR

1

14 18

PP_SOC_VAR

ROOM=SOC

1.06V @17.4A MAX 0.9V @tbd A MAX 0.625V @tbd A MAX

PP1402 P2MM-NSM

SM

1

PP

PP_CPU_VAR

1

14 18

ROOM=SOC

C1401

1

1

15UF

D

C1408

20% 2 6.3V X5R 0402-1

C1434

1

15UF

1

15UF

20% 2 6.3V X5R 0402-1

20% 2 6.3V X5R 0402-1

2

C1449 2.2UF

2

ROOM=SOC

ROOM=SOC

C1404

C1411

C1417

C1422

C1427

C1430

1

3

1

2 4

3

1

2 4

4.3UF

3

1

2 4

20% 4V CERM 0402

4.3UF 3

20% 4V CERM 0402

1

2 4

4.3UF

3

1

2 4

20% 4V CERM 0402

3

2 4

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

C1405

C1412

C1418

C1423

C1428

C1431

4.3UF

4.3UF

1UF

1UF

1

20% 4V CERM 0402

3

1

20% 4V CERM 0402

2 4

3

1

2 4

20% 4V CERM 0402

1UF

20% 4V CERM 0402 1

3

2 4

3

20% 4V CERM 0402

1

2 4

1UF

20% 4V CERM 0402 1

3

2 4

3

2 4

C ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

C1406

C1413

C1419

C1424

C1460

0.47UF

0.47UF

0.47UF

0.47UF

7.5UF

1

20% 6.3V CERM 0402

3

1

20% 6.3V CERM 0402

2 4

3

1

2 4

20% 6.3V CERM 0402

3

1

2 4

20% 6.3V CERM 0402

3

1

20% 4V CERM 0402

2 4

2 4

ROOM=SOC

C1461 7.5UF

3

20% 4V CERM 0402 1

3

2 4

AD10 AD15 AD19 AD23 AF13 AF17 AJ23 AL21 AL8 AN10 AN19 AN23 AR13 AR17 AR21 AU10 AU15 AW13 AW17 AW21 BA10 BA23 BD21 BD8 BF10 BF23 BH13 BH17 BH21 BK10 BK15 AJ10

U0700 CAYMAN-2GB-20NM-DDR-M CSP SYM 8 OF 16

VDD_CPU

VDD_GPU

OMIT

XW1402

18

BUCK0_PP_CPU_FB

1.06V @1.0A MAX 0.80V @TBDA MAX

ROOM=SOC

ROOM=SOC

ROOM=SOC

AF8 AN15 AR8 AU19 AW8 BA15 BA19 BH8

C1435

C1433

7.5UF

7.5UF

7.5UF

1

B

ROOM=SOC

C1407 20% 4V CERM 0402

20% 4V CER 0402

3 2

1

4

3 2

1

20% 4V CERM 0402

3

C1458

1

10UF

20% 2 6.3V CERM-X5R 0402-9 ROOM=SOC

4

PP_GPU_SRAM_VAR ROOM=SOC

ROOM=SOC

C1439

C1437 7.5UF

7.5UF 20% 4V CER 0402

1

3 2 4

AB13 AB17 AB21 AB25 AB43 AB47 AB51 AB55 AD40 AD45 AD49 AD53 AF55 AJ40 AJ49 AJ53 J25 J30 J38 J43 J47 J51 L15 L19 L23 L28 L32 L36 L40 L45 L49 L53 P13 T15 T36 T40 T53 V13 V25 V34 V38 V51 V55 Y28

1

OMIT

BUCK1_PP_GPU_FB

2

1.03V 0.92V 0.80V 0.67V

18

ROOM=SOC

NO_XNET_CONNECTION

@12.9A @10.7A @TBD A @TBD A

1

20% 4V CERM 0402

3

1

C1459 10UF

20% 2 6.3V CERM-X5R 0402-9 ROOM=SOC

ROOM=SOC

20% 2 6.3V CERM-X5R 0402-9

XW1403

SHORT-20L-0.05MM-SM 1 2

BUCK2_PP_SOC_FB

18

D

ROOM=SOC

MAX MAX MAX MAX

PP_GPU_VAR 1

1

C1414 15UF

20% 2 6.3V X5R 0402-1 ROOM=SOC

2

4.3UF 1

20% 4V CERM 0402

3

20% 6.3V X5R-CERM 0201-1

C1448 2.2UF

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

C1409

C1452

C1454

C1416

C1421

C1426

4.3UF

4.3UF

7.5UF

7.5UF

7.5UF

4.3UF

2 4

3

AF43 AF47 AF51 P17 P21 P25 P30 P34 P38 P43 P47 P51 Y15 Y19 Y23 Y40 Y45 Y49 Y53

1

2 4

20% 4V CERM 0402

3

1

2 4

20% 4V CERM 0402

3

2 4

1

20% 4V CERM 0402

3

1

2 4

20% 4V CERM 0402

3

1

2 4

20% 4V CERM 0402

3

1

2 4

20% 4V CERM 0402

2 4

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

ROOM=SOC

C1420

C1425

C1429

C1456

C1457

0.47UF

0.47UF

0.47UF

0.47UF

20% 4V CERM 0402

1UF 3

1

2 4

20% 4V CERM 0402

2 4

1UF

3

20% 4V CERM 0402 1

3

2 4

1

20% 6.3V CERM 0402

3

1

2 4

AD28 AD32 AF60 AJ28 AJ32 AJ36 AL6 AN28 AN32 AN36 AN40 AN45 AN49 AN53 AN58 AR25 AR30 AR34 AR38 AR43 AR47 AR51 AR55 AW30 AW34 AW38 AW43 AW47 AW51 AW55 AW60 BD25 BD30 BD34 BD38 BD43 BD47 BD51 BD55 BD6 BD60 BF28 BF32 BF36 BF45 BF49 BF53 BF58 BK28 BK32 BK36 BK40

3

C1415

1

20% 6.3V CERM 0402

2 4

AP_VDD_CPU_SENSE 1

3

1

20% 6.3V CERM 0402

2 4

3

1

20% 6.3V CERM 0402

3

2 4

PP

SM

PP1403 P2MM-NSM

1

SM PP

20

PP1408 P2MM-NSM ROOM=SOC

ROOM=SOC

VDD_GPU_SENSE AJ45

VDD_GPU_SRAM

AP_VDD_GPU_SENSE 1

TP_VDD_SOC_SENSE

PP SM

PP1410 P2MM-NSM

1

SM PP

20

PP1409 P2MM-NSM ROOM=SOC

ROOM=SOC

VSS_SENSE AJ47

1

TP_VSS_SENSE

C1440

C1442

1UF

7.5UF

0.47UF

20% 4V CERM 0402

3

1

20% 4V CERM 0402

3

1

2 4

20% 4V CERM 0402

3

1

2 4

20% 6.3V CERM 0402

3

2 4

C1432

ROOM=SOC

VDD_CPU_SENSE BK23

VDD_SOC_SENSE AL47

C1438

4.3UF

7.5UF

C1410 1UF

TP_AP_VSS_CPU_SENSE

C1465

ROOM=SOC

VDD_CPU_SRAM

VSS_CPU_SENSE BK21

ROOM=SOC

ROOM=SOC

ROOM=SOC

1

ROOM=SOC

2 4

ROOM=SOC

20% 4V CERM 0402

ROOM=SOC

1

20% 6.3V X5R-CERM 0201-1

2

ROOM=SOC

ROOM=SOC

C1402

1

C1466 2.2UF

ROOM=SOC

14 18

2 4

1.03V @1.44A MAX 0.92V @1.50A MAX 0.80V @TBD A MAX 18

SHORT-20L-0.05MM-SM 2 1 NO_XNET_CONNECTION

PP_CPU_SRAM_VAR

18

20% 6.3V CERM-X5R 0402-9

OMIT

10UF

XW1401

ROOM=SOC

20% 4V CERM 0402

2

C1403

ROOM=SOC

ROOM=SOC

7.5UF

10UF

1

NO_XNET_CONNECTION

ROOM=SOC

20% 4V CERM 0402

C1444

0.80V @4.1A MAX 0.67V @TBDA MAX

20% 6.3V X5R-CERM 0201-1

ROOM=SOC

7.5UF

20% 6.3V CERM-X5R 0402-9 ROOM=SOC

ROOM=SOC

20% 4V CERM 0402

1

10UF

SHORT-20L-0.05MM-SM

7.5UF

C1436

18

PP

SM

PP1411 P2MM-NSM ROOM=SOC

U0700 CAYMAN-2GB-20NM-DDR-M CSP SYM 9 OF 16

VDD_SOC

VDD_SOC

BK45 BK49 BK53 BM55 BP15 BP19 BP23 BP28 BP32 BP36 BP40 BP45 BP49 BP53 BP58 BT13 BT17 BT21 BT25 BT30 BT34 BT38 BT43 BT47 BT51 BT55 BW10 CA13 CA17 CA21 CA25 CA30 CA34 CA38 CA43 CA47 CE13 CE17 CE45 J13 J21 J34 P55 T10 T60 V30 Y10 Y36 Y60 BF40 J60

C

B

AW25

2 4

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SOC:POWER (1/3) DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

14 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

14 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

SOC - POWER SUPPLIES DDR IMPEDANCE CONTROL 18 15 7

1.06-1.17V @0.85A MAX 18 15 7

PP1V1

D

1 1

1

C1506 10UF

C1528 10UF

20% 6.3V 2 CERM-X5R 0402-9

20% 6.3V 2 CERM-X5R 0402-9 ROOM=SOC

ROOM=SOC

1

2

C1518 2.2UF 20% 6.3V X5R-CERM 0201-1 ROOM=SOC

PP0V9_SOC_FIXED ROOM=SOC

ROOM=SOC

ROOM=SOC

C1502

C1527

C1503

4.3UF

1UF

1

20% 4V CERM 0402

3

2 4

20% 4V CERM 0402 1

7.5UF 20% 4V CERM 0402 1

3

2 4

1

C1501

2

20% 6.3V CERM-X5R 0402-9

3

2 4

10UF

ROOM=SOC

C

B

0.797-0.945V @9 mA MAX

AB30 AB34 AB38 AD58 AF25 AF30 AF34 AF38 AF62 AJ58 AL25 AL30 AL34 AL38 AL43 AL51 AL55 AL60 AR60 AU28 AU32 AU36 AU40 AU45 AU49 AU53 AU58 AU6 BA28 BA32 BA36 BA40 BA45 BA49 BA53 BA58 BH25 BH30 BH34 BH38 BH43 BH47 BH51 BH55 BK58

AW23

U0700 CAYMAN-2GB-20NM-DDR-M CSP SYM 10 OF 16

VDD_FIXED

VDD_FIXED

BK6 BM13 BM17 BM21 BM25 BM30 BM34 BM38 BM43 BM47 BM51 BP10 BP60 BW15 BW19 BW23 BW28 BW32 BW36 BW40 BW45 BW49 BW53 BW58 BW8 CC10 CC15 CC19 CC23 CC28 CC32 CC45 G32 G36 J17 J23 J55 J62 L10 L58 L60 T32 T58 T8 Y58 Y8

PP0V8_AOP 1

C1504 2.2UF

CC36 CE30 CE40

2

C1519 2.2UF 20% 6.3V X5R-CERM 0201-1

1

C1514 2.2UF

20% 6.3V 2 X5R-CERM 0201-1 ROOM=SOC

1

2

240

C1522 2.2UF

1% 1/32W MF 2 01005

20% 6.3V X5R-CERM 0201-1

ROOM=SOC

R1501 ROOM=SOC

BE1 BJ1 BL1 BM8 BP6 BT8 BW6 CA8 CC6 CD1 CH1

U0700 CAYMAN-2GB-20NM-DDR-M CSP VDDIO11_DDR0

SYM 11 OF 16

DDR0_RREF DDR1_RREF DDR2_RREF DDR3_RREF

CD3 BY64 K3 K65

DDR0_RREF DDR1_RREF DDR2_RREF DDR3_RREF

DDR0_ZQ DDR3_ZQ

BN2 AA66

DDR0_ZQ DDR3_ZQ

DDR0_RET* DDR1_RET* DDR2_RET* DDR3_RET*

CF3 CB65 K4 K64

PMU_TO_AOP_SLEEP1_READY

1

R1502 240

1

BE67 BH60 BJ67 BK62 BL67 BM60 BP62 BT60 BW62 CD67 CH67

AB8 AC1 AE1 AH1 E1 K1 L6 P8 T6 V8 Y6

AB60 AC67 AD62 AE67 AH67 E67 K67 P60 T62 V60 Y62

VDD_FIXED_CPU

VDD_LOW

VDDIO11_PLL_DDR0 VDDIO11_PLL_DDR1 VDDIO11_PLL_DDR2 VDDIO11_PLL_DDR3

CE8 BW60 J8 P58

1

R1503 240

1% 1/32W MF 2 01005 ROOM=SOC

R1504

1

240

1% 1/32W MF 2 01005

1% 1/32W MF 2 01005

ROOM=SOC

R1505

1

240

240

2 ROOM=SOC

2 ROOM=SOC

1% 1/32W MF 01005

ROOM=SOC

R1506

D

1% 1/32W MF 01005

13 20

FL1501 100OHM-25%-0.12A

1.06 - 1.17V @4mA MAX

0.765-0.840V @60mA MAX 19

1

ROOM=SOC

TBD-TBDV @1.9A MAX 18 10 9 8 7

PP1V1

PP1V1_DDR_PLL

1

2

PP1V1

7 15 18

01005 1

C1508

1

0.22UF 2

20% 6.3V X5R 01005-1

C1509

1

C1523

0.22UF 2

ROOM=SOC

20% 6.3V X5R 01005-1

1

C1510

0.22UF 2

ROOM=SOC

20% 6.3V X5R 01005-1

ROOM=SOC

0.22UF 20% 6.3V X5R 01005-1

2

ROOM=SOC

ROOM=SOC

VDDIO11_DDR1

C

(CURRENT INCLUDED IN VDD2) VDDIO11_RET_DDR0 VDDIO11_RET_DDR1 VDDIO11_RET_DDR2 VDDIO11_RET_DDR3

CG3 CD65 H4 H64

PP1V1_SDRAM

DDR0_SYS_ALIVE DDR1_SYS_ALIVE DDR2_SYS_ALIVE DDR3_SYS_ALIVE

CF4 CB64 H3 H65

SYSTEM_ALIVE

VDDIO11_DDR2

VDD2

VDDIO11_DDR3

AM3 AM65 BB3 BB65 BR1 BR67 BV1 BV67 BY1 BY67 C2 C66 CJ2 CJ66 CK2 CK66 D2 D66 N1 N67 R1 R67 W1 W67

15 18 19

17 20 21

1.06 - 1.17V @1.74A MAX

PP1V1_SDRAM 1

C1512

1

10UF 2

20% 6.3V CERM-X5R 0402-9 ROOM=SOC

C1513

1

10UF

2

20% 6.3V CERM-X5R 0402-9 ROOM=SOC

C1507

1

2.2UF 2

20% 6.3V X5R-CERM 0201-1 ROOM=SOC

C1529

1

2.2UF 2

C1511 2.2UF

1

15 18 19

B

C1515 2.2UF

20% 6.3V X5R-CERM 0201-1

20% 2 6.3V X5R-CERM 0201-1

20% 2 6.3V X5R-CERM 0201-1

ROOM=SOC

ROOM=SOC

ROOM=SOC

20% 6.3V 2 X5R-CERM 0201-1 ROOM=SOC

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SOC:POWER (2/3) DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

15 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

15 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

SOC - POWER SUPPLIES 1.70-1.95V @134mA

D

C

B

A12 A16 A2 A20 A24 A27 A31 A35 A5 A52 A56 A59 A63 A66 A9 AA1 AA67 AB10 AB15 AB19 AB23 AB28 AB32 AB36 AB40 AB45 AB49 AB53 AB58 AB6 AB62 AC2 AC4 AC64 AC66 AD13 AD17 AD21 AD25 AD30 AD34 AD43 AD47 AD51 AD55 AD60 AD8 AF10 AF15 AF19 AF23 AF28 AF32 AF36 AF40 AF45 AF49 AF53 AF58 AF6 AG1 AG3 AG65 AG67 AJ21 AJ25 AJ30 AJ34 AJ38 AJ43 AL10 AJ51 AJ55 AJ8 AK1 AK2 AK66 AK67

U0700 CAYMAN-2GB-20NM-DDR-M CSP SYM 13 OF 16

VSS

VSS

AL23 AL28 AL32 AL36 AL40 AL45 AL53 AL58 AL62 AN13 AN17 AN21 AN25 AN30 AN34 AN38 AN43 AN47 AN51 AN55 AN60 AN8 AP1 AP4 AP64 AP67 AR10 AR15 AR19 AR28 AR32 AR36 AR40 AR45 AR49 AR53 AR58 AR6 AR62 AT1 AT3 AT65 AU13 AU17 AU21 AU25 AU30 AU34 AU38 AU43 AU47 AU51 AU55 AU60 AU8 AV1 AV2 AV4 AV64 AV66 AW10 AW15 AW19 CH50 AW28 AW32 AW36 AW40 AW45 AW49 AW53 AW58 AW6 AW62 AY1 AY4 AY64 AY67

B1 B3 B35 B41 B46 B52 B65 B67 BA13 BA17 BA21 BA30 BA34 BA38 BA43 BA47 BA51 BA55 BA60 BA8 BC1 BC2 BC66 BC67 BD10 BD23 BD28 BD32 BD36 BD40 BD45 BD49 BD53 BD58 BD62 BF21 BF25 BF30 BF34 BF43 BF47 BF51 BF55 BF8 BG1 BG3 BG65 BG67 BH10 BH15 BH19 BH23 BH28 BH32 BH36 BH40 BH45 BH49 BH53 BH58 BH6 BH62 BK13 BK17 AL49 BK25 BK30 BK34 BK38 BK43 BK47 BK51 BK55 BK60 BK8 BL2 BL4 BL64

U0700 CAYMAN-2GB-20NM-DDR-M CSP SYM 14 OF 16

VSS

VSS

BL66 BM10 BM15 BM19 BM23 BM28 BM32 BM36 BM40 BM45 BM49 BM53 BM58 BM6 BM62 BN1 BN67 BP13 BP17 BP21 BP25 BP30 BP34 BP38 BP43 BP47 BP51 BP55 BP8 BR3 BR65 BT10 BT15 BT19 BT23 BT28 BT32 BT36 BT40 BT45 BT49 BT53 BT58 BT6 BT62 BU1 BU67 BV2 BV4 BV64 BV66 BW13 BW17 BW21 BW25 BW30 BW34 BW38 BW43 BW47 BW51 CE51 BY65 C11 C14 C18 C22 C26 C29 C33 C35 C4 C52 C54 C57 C61 C64 C7 CA10

CA15 CA19 CA23 CA28 CA32 CA36 CA40 CA45 CA49 CA53 CA58 CA6 CA62 CB1 CB3 CB66 CB67 CC13 CC17 CC21 CC30 CC34 CC38 CC43 CL22 T30 CC8 CD2 CD4 CD64 CD66 CE10 CE15 CE47 CE53 CE6 CE62 CF1 CF2 CF64 CF65 CF66 CF67 CG1 CG11 CG2 CG24 CG27 CG4 CG42 CG44 CG46 CG48 CG5 CG52 CG54 CG56 CG59 CG61 CG64 CG65 CG66 CG67 CH12 CH18 CH2 CH24 CH27 CH3 CH33 CH39 CH4 CH42 CH44 CH46 CH48

U0700 CAYMAN-2GB-20NM-DDR-M CSP SYM 15 OF 16

VSS

VSS

CH5 CH52 CH54 CH56 CH59 CH61 CH63 CH64 CH65 CH66 CH7 CH9 CJ1 CJ3 CJ4 CJ41 CJ42 CJ46 CJ5 CJ50 CJ54 CJ57 CJ61 CJ64 CJ65 CJ67 CK4 CK41 CK42 CK46 CK5 CK50 CK54 CK57 CK61 CK64 CL1 CL12 CL18 CL24 CL27 CL3 CL33 CL39 CL4 CL41 CL44 CL48 CL52 CL56 CL59 CL63 CL65 CL67 CL7 CM18 CM2 CM24 CM27 CM39 CM4 CM41 CM44 CM48 CM5 CM52 CM56 CM59 CM63 CM66 D1 D11 D12 D14 D16 D18

D20 D22 D24 D26 D27 D29 D3 D31 D35 D4 D41 D46 D5 D52 D56 D59 D63 D65 D67 D7 D9 E12 E14 E18 E2 E20 E22 E26 E27 E29 E3 E37 E4 E5 E54 E57 E59 E61 E64 E65 E66 E7 E9 F1 F2 F3 F4 F64 F65 F66 F67 G38 G43 G47 G51 G8 H1 H2 H66 H67 J10 J15 J19 J28 J32 J40 J45 J49 J53 J6 K2 K66 L13 L17 L21 L25 L30 L34

U0700 CAYMAN-2GB-20NM-DDR-M CSP SYM 16 OF 16

VSS

VSS

L38 L43 L47 L51 L55 L62 L8 M1 M2 M3 M4 M64 M65 M66 M67 P10 P15 P19 P23 P28 P32 P36 P40 P45 P49 P53 P6 P62 R2 R4 R64 R66 T13 T25 T34 T38 T51 T55 U1 U67 V10 V15 V28 V32 V36 V40 V53 V58 V6 V62 W3 W65 Y13 Y17 Y21 Y25 Y30 Y43 Y47 Y51 Y55 BF38 J58

46 41 40 37 36 32 21 20 18 16 53 52 48 47

MAX

PP1V8_SDRAM 1

2

1

C1615 2.2UF 20% 6.3V X5R-CERM 0201-1

2

ROOM=SOC

C1605 2.2UF 20% 6.3V X5R-CERM 0201-1

1

2

ROOM=SOC

1

C1608 2.2UF 20% 6.3V X5R-CERM 0201-1

2

ROOM=SOC

C1612 2.2UF 20% 6.3V X5R-CERM 0201-1 ROOM=SOC

AM1 AM67 BB1 BB67 C3 C65 CK3 CK65

U0700 CAYMAN-2GB-20NM-DDR-M CSP VDD1

D

SYM 12 OF 16

CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND

1.62-1.98V @43mA MAX 29 25 18 17 13 12 11 9 8 7 5 52 48 47 46 39 30

PP1V8 1

1

C1602 10UF

20% 6.3V 2 CERM-X5R 0402-9

2

ROOM=SOC

C1607 2.2UF 20% 6.3V X5R-CERM 0201-1

1

2

ROOM=SOC

1

C1610 2.2UF 20% 6.3V X5R-CERM 0201-1

2

ROOM=SOC

C1614 2.2UF 20% 6.3V X5R-CERM 0201-1

AJ62 AN62 AU62 BA62 BF62

AD6 AJ6 AN6 BA6 BF6 CE19 CE23

1.62-1.98V @10mA

PP1V8_SDRAM 1

C1603 2.2UF 20% 6.3V X5R-CERM 0201-1

2

ROOM=SOC

19

1

2

MAX

CE28 CE32 CE34 CE36 CE43 CE38

C1601 0.1UF 20% 6.3V X5R-CERM 01005 ROOM=SOC

PP1V2_REF 1

VDDIO18_GRP2

VDDIO18_GRP3

VDDIO18_GRP4

C VDDIO18_GRP10

1.62-1.98V @2mA MAX

AR23 BK19 AF21 J36 CE21 BF60

1.62-1.98V @1mA MAX

CG9

VDD18_FMON

1.62-1.98V @1mA MAX

CC40

VDD18_LPOSC

TBD-TBDV @30mA MAX

AU23 T28 Y38

VDD12_CPU_UVD VDD12_GPU_UVD VDD12_SOC_UVD

BA25

VDD12_PLL_CPU

C1611 2.2UF

2

VDDIO18_GRP1

ROOM=SOC

G40 G45 G49 G53

46 41 40 37 36 32 21 20 18 16 53 52 48 47

VDD18_EFUSE1 CG7 VDD18_EFUSE2 G34

20% 6.3V X5R-CERM 0201-1

VDD18_TSADC0 VDD18_TSADC1 VDD18_TSADC2 VDD18_TSADC3 VDD18_TSADC4 VDD18_TSADC5

ROOM=SOC

R1602 19 10 8

PP1V2_SOC

1

0.00

2

VDD12_PLL_CPU:1.14-1.26V @13mA

Y32 AD36 AD38 Y34

MAX

PP1V2_PLL_CPU

0% 1/32W MF 01005

1

VDD12_PLL_SOC

B

C1606 0.1UF

ROOM=SOC

20% 2 6.3V X5R-CERM 01005 ROOM=SOC

R1601 1

C1604 2.2UF 20% 6.3V X5R-CERM 0201-1

1

0.00

2

VDD12_PLL_SOC:1.14-1.26V @31mA

MAX

PP1V2_PLL_SOC

0% 1/32W MF 01005

1

C1609 0.1UF

ROOM=SOC

20% 2 6.3V X5R-CERM 01005

2

ROOM=SOC

ROOM=SOC

A

1

C1613 0.1UF

20% 2 6.3V X5R-CERM 01005 ROOM=SOC

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SOC:POWER (3/3) DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

16 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

16 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7 315mA 25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 30 29

6

MAX

R1703 24.9

PP1V8

1

5

1

C1726 2.2UF

ROOM=NAND

20% 6.3V X5R-CERM 0201-1

2 17

1

2

3

2

1

PP1V8_NAND_AVDD

2

1% 1/32W MF 01005

D

4

1

20% 6.3V X5R 0402-1

ROOM=NAND

20% 6.3V X5R-CERM 01005

2

ROOM=NAND

PROBE POINTS 1

C1707 15UF 20% 6.3V X5R 0402-1

2

C1710 0.1UF

ROOM=NAND

NAND_AGND

C1701 15UF

1

2

ROOM=NAND

C1729 15UF 20% 6.3V X5R 0402-1

1

2

ROOM=NAND

C1730 15UF

17 8

20% 6.3V X5R 0402-1

D

90_PCIE_AP_TO_NAND_REFCLK_P

SM

1

PP

PP1701 P2MM-NSM ROOM=NAND

17 8

ROOM=NAND

90_PCIE_AP_TO_NAND_REFCLK_N

SM

1

PP

PP1702 P2MM-NSM ROOM=NAND

1

C1739

C1741

1

1.0UF

1.0UF

20% 2 6.3V X5R 0201-1

20% 2 6.3V X5R 0201-1

ROOM=NAND

1

1

C1708

2

C1745 1.0UF

20% 2 6.3V X5R 0201-1

20% 2 6.3V X5R 0201-1

ROOM=NAND

1

1

5% 16V CERM 01005 ROOM=NAND

5% 2 16V NP0-C0G 01005 ROOM=NAND

1

C1717 68PF

C1723

20% 2 6.3V X5R 0201-1

ROOM=NAND

1

39PF

2

C1747 1.0UF

ROOM=NAND

C1711 22PF

5% 2 10V C0G-CERM 01005 ROOM=NAND

1

1.0UF

ROOM=NAND

220PF

19

C1743

1

5% 16V NP0-C0G 01005 ROOM=NAND

2

C1722

1

C1712 100PF 5% 16V NP0-C0G 01005

ROOM=NAND

PP0V9_NAND 1007mA

MAX 1

2

C

1

C1704 15UF 20% 6.3V X5R 0402-1

C1702 15UF 20% 6.3V X5R 0402-1

2

ROOM=NAND

1

2

ROOM=NAND

1

C1705 15UF

15UF

20% 6.3V X5R 0402-1

2

ROOM=NAND

20% 6.3V X5R 0402-1

C1727 15UF

20% 6.3V 0402-1

2 X5R

ROOM=NAND

#24543147:10uF for 32GB #26326159:10uF for C1719

ROOM=NAND

1230mA

C

MAX (1us peak power)

PP3V0_NAND OMIT

1

C1737

1

1.0UF

1

1.0UF

20% 2 6.3V X5R 0201-1

C1740 1.0UF

20% 2 6.3V X5R 0201-1

ROOM=NAND

1

C1738

20% 2 6.3V X5R 0201-1

ROOM=NAND

C1703

1

220PF

C1706

1

5% 16V NP0-C0G 01005

2

ROOM=NAND

ROOM=NAND

1

20% 2 6.3V X5R 0201-1

ROOM=NAND

1

1

C1714

1

C1720 100PF

5% 10V C0G-CERM 01005

2

ROOM=NAND

5% 16V NP0-C0G 01005

1

C1746

20% 6.3V 2 X5R 0402-1

20% 2 6.3V X5R 0201-1

1

1

C1728

1.0UF

68PF

20% 2 6.3V X5R 0201-1

5% 2 16V NP0-C0G 01005

ROOM=NAND

C1715

5% 2 10V C0G-CERM 01005

C1724 0.01UF 10% 6.3V X5R 01005

1

C1750 1.0UF

20% 2 6.3V X5R 0201-1

20% 2 6.3V X5R 0402-1

C1719

1

OMIT

C1721

1

10UF

15UF

20% 2 6.3V CERM-X5R 0402-9

ROOM=NAND

1

20% 2 6.3V X5R 0402-1

ROOM=NAND

C1751

1

C1733 15UF

20% 2 6.3V X5R 0402-1

ROOM=NAND

C1752

1

1.0UF

1.0UF

20% 2 6.3V X5R 0201-1

ROOM=NAND

1

ROOM=NAND

ROOM=NAND

C1753 1.0UF

20% 2 6.3V X5R 0201-1

20% 2 6.3V X5R 0201-1

ROOM=NAND

1

ROOM=NAND

1

C1754 1.0UF

20% 2 6.3V X5R 0201-1

ROOM=NAND

ROOM=NAND

5% 2 16V CERM 01005

1

C1731 68PF

5% 2 16V NP0-C0G 01005

1

39PF

100PF

5% 2 16V NP0-C0G 01005

5% 2 16V NP0-C0G 01005

ROOM=NAND

C1734

ROOM=NAND

ROOM=NAND

1

C1735 220PF

5% 10V 2 C0G-CERM 01005 ROOM=NAND

1

C1736 100PF

5% 2 16V NP0-C0G 01005

ROOM=NAND

OA0 OA10 OD0 OD10 OG0 OG10

ROOM=NAND

C1732

1

VCC VCC VCC VCC VCC VCC

A5 OB0 OB10 OF0 OF10 R5 VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO

A3 A7 F2 J1 J9 R3 R7 VDD VDD VDD VDD VDD VDD VDD

E5 VREF

C3 AVDD1

J7

K4 K6 PCI_VDD1 PCI_VDD2

10% 6.3V X5R 01005

PCI_AVDD_H

M4 J5

C1725

C1718 22PF

ROOM=NAND

NAND_VREF

0.01UF 2

C1716 15UF

ROOM=NAND

ROOM=NAND

PCI_AVDD_CLK1 PCI_AVDD_CLK2

1

20% 2 6.3V X5R 0402-1

1

OMIT

ROOM=NAND

ROOM=NAND

B

C1749

220PF

2

C1713 15UF

ROOM=NAND

PP1V8 1

1

OMIT

ROOM=NAND

1 25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 30 29

C1748 15UF

1.0UF

ROOM=NAND

220PF

2

C1744 1.0UF

20% 2 6.3V X5R 0201-1

100PF

5% 2 16V CERM 01005

ROOM=NAND

C1709

C1742 1.0UF

ROOM=NAND

22PF

5% 2 10V C0G-CERM 01005

1

OMIT

B

U1701 THGBX6T1T82LFXF VLGA

11

17 8 17 8

8

1

R1704 3.01K 1% 1/32W MF 01005

8 8

AP_TO_NAND_SYS_CLK

D2

CLK_IN

90_PCIE_AP_TO_NAND_REFCLK_P 90_PCIE_AP_TO_NAND_REFCLK_N

H8 H6

PCIE_REFCLK_P PCIE_REFCLK_M

PCIE_NAND_BI_AP_CLKREQ_L

G9

PCIE_CLKREQ*

PCIE_NAND_RESREF

M6

PCI_RESREF

90_PCIE_AP_TO_NAND_TXD_P 90_PCIE_AP_TO_NAND_TXD_N

M8 K8

PCIE_RX0_P PCIE_RX0_M

NC NC

2 ROOM=NAND 8 8

90_PCIE_NAND_TO_AP_RXD_P 90_PCIE_NAND_TO_AP_RXD_N NC NC

7

AP_TO_NAND_RESET_L

A

NC

N5 N3

PCIE_RX1_P PCIE_RX1_M

P8 N7

PCIE_TX0_P PCIE_TX0_M

M2 K2

VER-1 ROOM=NAND BOMOPTION=OMIT_TABLE

CRITICAL

PCIE_TX1_P PCIE_TX1_M

F8

RESET*

D8

TRST*

EXT_D0 EXT_D1 EXT_D2 EXT_D3 EXT_D4 EXT_D5 EXT_D6 EXT_D7

G3 J3 H2 E3 E7 F6 C7 B8

EXT_NCE

G1

EXT_NRE

F4

EXT_NWE

C5

EXT_RNB

G5

EXT_CLE

H4

EXT_ALE

D4

PMU_TO_NAND_LOW_BATT_BOOT_L AP_TO_NAND_FW_STRAP

20 12

NC NC NC NC NC

SYSTEM_ALIVE

15 20 21

PCIE_AP_TO_NAND_RESET_L

8

SWD_AP_BI_NAND_SWDIO_R

ROOM=NAND

SWD_AP_NAND_SWCLK_R

ROOM=NAND

1/32W 1/32W

1 0% 1 0%

0.00 R1702 2 01005 MF 0.00 R1707 2

01005

MF

SWD_AP_BI_NAND_SWDIO

13

SWD_AP_TO_MANY_SWCLK

13 36 53

NC NC

SYNC_MASTER=Sync

0.5% 1/32W MF 01005

17

2 ROOM=NAND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NAND DRAWING NUMBER

B4 B6 OE10 G7 L3 L5 L7 P2 P4 P6 OC0 OC10 OE0

R1701 34.8

PAGE TITLE

B2

1

ZQ

VSSA

D6

NAND_ZQ

SYNC_DATE=06/06/2016

Apple Inc.

051-00482 REVISION

8.0.0

R

NAND_AGND

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

17 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

17 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

L1806

10UF

D 1

C1875 2.2UF

20% 2 6.3V X5R-CERM 0201-1

C1876 2.2UF

20% 2 6.3V X5R-CERM 0201-1 ROOM=PMU

1

10UF

C1853

1

10UF

C1857

20% 2 6.3V CERM-X5R 0402-9

20% 2 6.3V CERM-X5R 0402-9

20% 2 6.3V CERM-X5R 0402-9

ROOM=PMU

ROOM=PMU

ROOM=PMU

ROOM=PMU

1

C1847

1

2.2UF

2.2UF

ROOM=PMU

1

2.2UF

1

2.2UF

20% 2 6.3V X5R-CERM 0201-1 ROOM=PMU

1

C1855

1

1

2.2UF

C1849

1

H1 H2 H3

C1856

20% 2 6.3V X5R-CERM 0201-1

ROOM=PMU

ROOM=PMU

C

ROOM=PMU

BUCK0_LX2 VDD_BUCK0_23

0.22UH-20%-6.7A-0.023OHM

BUCK0_LX3 VDD_BUCK1_01

BUCK0_FB VDD_BUCK1_23

BUCK1_LX0

VDD_BUCK2

VDD_BUCK3

M1 M2 M3

VDD_BUCK4

B1 C1 D1

VDD_BUCK5

K18 K19

VDD_BUCK6

U6 V6

VDD_BUCK7

F18 F19

VDD_BUCK8

BUCK1_LX1

BUCK5

3.2A MAX

1

C1867 220PF

5% 2 10V C0G-CERM 01005

1

C1840 15UF

20% 2 6.3V X5R 0402-1 ROOM=PMU

1

C1801 15UF

20% 2 6.3V X5R 0402-1 ROOM=PMU

1

C1803 15UF

20% 2 6.3V X5R 0402-1 ROOM=PMU

1

C1807

ROOM=PMU NO_XNET_CONNECTION=1

15UF

20% 2 6.3V X5R 0402-1 ROOM=PMU

BUCK1_LX2

BUCK1_LX3

BUCK1_FB

ROOM=SOC

C1811

1

220PF

C1804 15UF

5% 2 10V C0G-CERM 01005

20% 2 6.3V X5R 0402-1

ROOM=PMU

1

C1808

ROOM=PMU

A10 B10 C10 D10

ROOM=PMU

NO_XNET_CONNECTION=1

14

BUCK2_LX1

F5 BUCK5_FB

BUCK2_FB

1.5A MAX

220PF

C1805 15UF

20% 2 6.3V X5R 0402-1

5% 2 10V C0G-CERM 01005 ROOM=PMU

1

C1809

ROOM=PMU

VBUCK3_SW

B18 C18 D18 A18

BUCK1_LX0

A16 B16 C16 D16

BUCK1_LX1

1

U7 V7

BUCK7_LX0 BUCK4_LX0

L1801

CRITICAL

R8 BUCK7_FB

NO_XNET_CONNECTION=1

BUCK4_LX1

1UH-20%-2.1A-0.12OHM 2

PP_GPU_SRAM_VAR

1

BUCK8_LX0

1.5A MAX

BUCK8

PIQA20121T-SM

0.80V - 0.92V

1

C1869

1

220PF

C1806 15UF

20% 2 6.3V X5R 0402-1

5% 2 10V C0G-CERM 01005 ROOM=PMU

1

C1810

A14 B14 C14 D14

A12 B12 C12 D12

ROOM=SOC

0.75A MAX

BUCK9

BUCK8_FB

L1802

1.0UH-20%-1.5A-0.161OHM 1 2 BUCK9_LX0

C1870

1

220PF

C1862 15UF

20% 2 6.3V X5R 0402-1

5% 2 10V C0G-CERM 01005 ROOM=PMU

ROOM=PMU

1

C1863 15UF

20% 2 6.3V X5R 0402-1

1

L1811

15UF

0.22UH-20%-6.7A-0.023OHM 1

2 PINA20121T-SM

NO_XNET_CONNECTION=1

C1813

20% 2 6.3V X5R 0402-1

1

15UF

20% 2 6.3V X5R 0402-1

ROOM=PMU

CRITICAL

C1820

1

C1827 15UF

20% 2 6.3V X5R 0402-1

ROOM=PMU

1

C1833

1

15UF

1

15UF

20% 2 6.3V X5R 0402-1

ROOM=PMU

C1839

ROOM=PMU

0.67V - 0.92V 1.03V for overdrive only

C1865 15UF

20% 2 6.3V X5R 0402-1

14

20% 2 6.3V X5R 0402-1

ROOM=PMU

ROOM=PMU

ROOM=PMU

L1812

2

BUCK1_LX2

1 PINA20121T-SM

NO_XNET_CONNECTION=1

CRITICAL

ROOM=PMU

1

C1814 15UF

20% 2 6.3V X5R 0402-1

1

C1821 15UF

20% 2 6.3V X5R 0402-1

ROOM=PMU

1

C1828 15UF

20% 2 6.3V X5R 0402-1

ROOM=PMU

1

C1834

1

15UF

1

15UF

20% 2 6.3V X5R 0402-1

ROOM=PMU

C1866

C

220PF

5% 2 10V C0G-CERM 01005

20% 2 6.3V X5R 0402-1

ROOM=PMU

C1873

ROOM=PMU

ROOM=PMU

L1813

1

BUCK1_LX3

2 PINA20121T-SM

NO_XNET_CONNECTION=1

CRITICAL

ROOM=PMU

14

L1814

G1 G2 G3

1

BUCK2_LX0

2 PIQA20161T-SM

PP_SOC_VAR CRITICAL

0.67V/0.80V

ROOM=PMU

1

L1815

J1 J2 J3

BUCK2_LX1

J5

BUCK2_PP_SOC_FB

2

C1822 15UF

20% 2 6.3V X5R 0402-1

1 PIQA20121T-SM

NO_XNET_CONNECTION=1

14

CRITICAL

1

C1829 15UF

20% 2 6.3V X5R 0402-1

ROOM=PMU

1

C1835 15UF

20% 2 6.3V X5R 0402-1

ROOM=PMU

1

C1841 15UF

20% 2 6.3V X5R 0402-1

ROOM=PMU

1

C1864 15UF

20% 2 6.3V X5R 0402-1

ROOM=PMU

1

C1871 220PF

5% 2 10V C0G-CERM 01005

ROOM=PMU

ROOM=PMU

ROOM=PMU

14

L1816

ROOM=PMU

R2 R3 R1 R7

1

BUCK3_LX0

2 PIQA20161T-SM

NO_XNET_CONNECTION=1

PP1V8_SDRAM CRITICAL

1

OMIT

15UF

XW1804

20% 2 6.3V X5R 0402-1

SHORT-20L-0.05MM-SM 1 2

U2 V2

C1816

1

C1823 15UF

20% 2 6.3V X5R 0402-1

ROOM=PMU

1

16 20 21 32 36 37 40 41 46 47 48 52 53

C1860 220PF

5% 2 10V C0G-CERM 01005

ROOM=PMU

ROOM=PMU

L1817

N1 N2 N3

1

BUCK4_LX0

2 PIQA20161T-SM

NO_XNET_CONNECTION=1

PP1V1_SDRAM CRITICAL

1

ROOM=PMU

L1 L2 L3

L1818

K5

2

BUCK4_LX1

20% 2 6.3V X5R 0402-1

1 PIQA20121T-SM

NO_XNET_CONNECTION=1

C1830 15UF

ROOM=PMU

1

C1836 15UF

20% 2 6.3V X5R 0402-1 ROOM=PMU

1

C1802 15UF

20% 2 6.3V X5R 0402-1 ROOM=PMU

1

C1874 15UF

20% 2 6.3V X5R 0402-1 ROOM=PMU

1

15 19

C1861 220PF

5% 2 10V C0G-CERM 01005 ROOM=PMU

CRITICAL

ROOM=PMU OMIT

XW1805

SHORT-20L-0.05MM-SM 1 2

BUCK4_FB

ROOM=SOC

VBUCK4_SW

U5 V5

BUCK3_SW1

T1 U1

PP1V8

U3 V3

PP1V8_TOUCH PP1V8_MAGGIE_IMU

H15 BUCK8_FB

M18 M19

BUCK9_LX0

OMIT

XW1806

SHORT-20L-0.05MM-SM 2 1

BUCK9_FB

P16 BUCK9_FB

ROOM=PMU ROOM=SOC

NO_XNET_CONNECTION=1

5 7 8 9 11 12 13 16 17 25 29 30 39 46 47 48 52

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SYSTEM POWER:PMU (1/3) DRAWING NUMBER

BUCK3_SW2 BUCK3_SW3

38 39 46 47

Apple Inc.

24 36

051-00482 REVISION

8.0.0

R

BUCK4_SW1

PP1V1

U4 V4

7 15

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

18 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

18 OF 81

IV ALL RIGHTS RESERVED

8

7

B

NO_XNET_CONNECTION=1

0603 1

BUCK4_FB

BUCK8_LX0

XW1801

ROOM=PMU

PP2V8_UT_AF_VAR

CRITICAL

ROOM=PMU

NO_XNET_CONNECTION=1

SHORT-20L-0.05MM-SM 2 1

CRITICAL 30 25

PP_GPU_VAR

OMIT

20% 2 6.3V X5R 0402-1

A

PIQA20161T-SM

F12BUCK1_PP_GPU_FB

ROOM=PMU

15UF

ROOM=PMU

G18 G19

SWITCH OUTPUTS

14

2

0.47UH-20%-3.8A-0.048OHM

BUCK7_FB

ROOM=PMU ROOM=SOC

1

NO_XNET_CONNECTION=1

XW1803 SHORT-20L-0.05MM-SM 2

L1810

1.0UH-20%-3.6A-0.060OHM

OMIT

20% 2 6.3V X5R 0402-1

ROOM=PMU

14

ROOM=SOC

H16 BUCK6_FB

ROOM=PMU

15UF

ROOM=PMU

BUCK4

1

BUCK3_LX0

BUCK6_LX0

NO_XNET_CONNECTION=1

1.0UH-20%-2.25A-0.086OHM 2 1 BUCK7_LX0

C1868

ROOM=PMU

220PF

5% 2 10V C0G-CERM 01005

20% 2 6.3V X5R 0402-1

4.7A MAX

1

ROOM=PMU

D

C1872

CRITICAL

NO_XNET_CONNECTION=1

BUCK6_FB

MCFE2016T-SM

0.80V - 1.06V

J18 J19

ROOM=PMU

PP_CPU_SRAM_VAR

ROOM=PMU

15UF

20% 2 6.3V X5R 0402-1

1

ROOM=PMU

BUCK3_FB

L1805

ROOM=PMU

15UF

20% 2 6.3V X5R 0402-1

C1845

1

2 PINA20121T-SM

F10BUCK0_PP_CPU_FB

XW1807

CRITICAL

1

BUCK0_LX3

BUCK5_LX0

BUCK3_FB

ROOM=SOC

BUCK7

BUCK6_LX0

SHORT-20L-0.05MM-SM 2 1

15UF

20% 2 6.3V X5R 0402-1

C1843

1

L1809

0.47UH-20%-3.8A-0.048OHM

OMIT

20% 2 6.3V X5R 0402-1

CRITICAL

15UF

20% 2 6.3V X5R 0402-1

C1838

1

1.0UH-20%-3.6A-0.060OHM

ROOM=PMU

15UF

15UF

20% 2 6.3V X5R 0402-1

C1832

1

1.0UH-20%-3.6A-0.060OHM

PIQA20121T-SM 1

15UF

ROOM=PMU

C1826

1

BUCK3

1.5A MAX

1

ROOM=PMU

1.7A MAX

BUCK6

2

PP1V25_BUCK

ROOM=PMU

(pending vendor qual)

19

C1819

1

1 PINA20121T-SM

NO_XNET_CONNECTION=1

1UH-20%-2.1A-0.12OHM

B

2

BUCK0_LX2

A8 B8 C8 D8

NO_XNET_CONNECTION=1

L1804

CRITICAL

BUCK5_FB

ROOM=PMU

CRITICAL

L1808

VDD_BUCK9

XW1802

SHORT-20L-0.05MM-SM 2 1

20% 2 6.3V X5R 0402-1

0.22UH-20%-6.7A-0.023OHM

OMIT

ROOM=PMU

ROOM=PMU

15UF

20% 6.3V 2 X5R 0402-1

BUCK2

MEKK2016T-SM

B2 C2 D2 A2

ROOM=PMU

15UF

20% 2 6.3V X5R 0402-1

0.625V - 1.06V

C1844

1

ROOM=PMU

0.22UH-20%-6.7A-0.023OHM

BUCK2_LX0

BUCK5_LX0

15UF

20% 2 6.3V X5R 0402-1

C1842

1

4.7A MAX

1

15UF

20% 2 6.3V X5R 0402-1

C1837

1

1.0UH-20%-3.6A-0.060OHM

L1803

2

PP0V9_SOC_FIXED

PINA20121T-SM

NO_XNET_CONNECTION=1

15UF

ROOM=PMU

2

C1831

1

14

0.22UH-20%-6.7A-0.023OHM

1.0UH-3.6A-0.06OHM

15 10 9 8 7

1

BUCK0_LX1

A6 B6 C6 D6

C1825

1

20% 2 6.3V X5R 0402-1

L1807

D10/D101:#24681501,TY ONLY, D11/D11: Both Vendor

CRITICAL

C1818

1

15UF

VDD_BUCK0_01

T2 T3

L18 L19

PP_CPU_VAR CRITICAL

0.22UH-20%-6.7A-0.023OHM

2.2UF

20% 2 6.3V X5R-CERM 0201-1

ROOM=PMU

A13 B13 C13 D13

ROOM=PMU

2.2UF

20% 2 6.3V X5R-CERM 0201-1

C1859

20% 2 6.3V X5R-CERM 0201-1

ROOM=PMU

C1877

A17 B17 C17 D17

2.2UF

20% 2 6.3V X5R-CERM 0201-1

ROOM=PMU

C1858 ROOM=PMU

2.2UF

20% 2 6.3V X5R-CERM 0201-1

A9 B9 C9 D9

20% 2 6.3V X5R-CERM 0201-1

ROOM=PMU

C1852

A5 B5 C5 D5

2.2UF

20% 2 6.3V X5R-CERM 0201-1

ROOM=PMU

C1848

C1854

1

2.2UF

20% 2 6.3V X5R-CERM 0201-1

20% 2 6.3V X5R-CERM 0201-1

1

C1851

1

BUCK0_LX1

10UF

20% 2 6.3V CERM-X5R 0402-9

ROOM=PMU

1

C1850

BAT/USB

1

BUCK INPUT

C1846

BUCK0_LX0

NO_XNET_CONNECTION=1

BUCK1

1

SYM 2 OF 4 ROOM=PMU

B4 C4 D4 A4

BUCK0

PP_VDD_MAIN

VDD_MAIN_SNS VDD_MAIN VDD_MAIN_E VDD_MAIN_N VDD_MAIN_SW VDD_MAIN_W VDD_MAIN_W

2 PIQA20161T-SM

13.4A MAX

M8 N7 H6 F11 R13 H14 H13

WLCSP

13.4A MAX

53 28 27 26 25 23 21 19 10 9 4 46 41 40 39 37 35 34 33 31 30

VDD_MAIN_SNS

1

BUCK0_LX0

D2333A1 19

Voltages per Cayman Power Spec, Sec. 2.2, rev 0.9.2, #24557869

1.0UH-20%-3.6A-0.060OHM

U1801

1

6

5

4

3

2

1

SIZE

D

A

8

7

53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

5

4

1

SHORT-20L-0.05MM-SM 2 1

VDD_MAIN_SNS

2

C1901 15UF 20% 6.3V X5R 0402-1

1

C1910 10UF

20% 6.3V 2 CERM-X5R 0402-9

ROOM=PMU

ROOM=PMU NO_XNET_CONNECTION

1

C1914 10UF

20% 6.3V 2 CERM-X5R 0402-9

ROOM=PMU

ROOM=PMU

1

1

C1911 10UF

20% 6.3V 2 CERM-X5R 0402-9

C1907 10UF

ROOM=PMU

ADJ.RANGE, HI

ACCURACY

MAX.CURRENT

LDO1 (Ca)

1.2-2.475V

2.4-3.675V

+/-1.4%

50mA

LDO2 (Ca)

1.2-2.475V

2.4-3.675V

+/-2.5%

50mA

LDO3 (Ca)

1.2-2.475V

2.4-3.675V

+/-2.5%

50mA

LDO4 (D)

0.7-1.2V

+/-2.5%

60mA

LDO5 (F)

2.5-3.6V(tbc)

+/-75mV

1000mA

LDO# LDO11 (Cb)

ROOM=PMU

XW1902

SHORT-20L-0.05MM-SM 2

ADJ.RANGE, LOW

LDO#

20% 6.3V 2 CERM-X5R 0402-9

OMIT

PMU_PRE_UVLO_DET

2

1

ADELYN LDO SPECS

XW1901

20

3

PP_VDD_MAIN OMIT

18

6

1

ROOM=PMU

D

53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

53 38 37 32 30 25 23

PP_VDD_MAIN

PP_VDD_BOOST 1

C1915 15UF

20% 2 6.3V X5R 0402-1 ROOM=PMU

1

2.4-3.675V

1.2-2.475V

LDO6 (Cb)

ADJ.RANGE, HI

1.2-2.475V

2.4-3.675V

MAX.CURRENT

ACCURACY +/-30mV

250mA

+/-5%

10mA

+/-30mV

250mA

+/-3.0%

400mA

LDO12 (E)

1.8V

LDO13 (Cb)

1.2-2.475V

LDO14 (Gb)

0.7-1.4V

LDO15 (Ca)

1.2-2.475V

2.4-3.675V

+/-2.5%

50mA

LDO16 (Cb)

1.2-2.475V

2.4-3.675V

+/-30mV

250mA

LDO17 (Ca)

1.2-2.475V

2.4-3.675V

+/-2.5%

50mA

LDO18 (Gb)

0.7-1.4V

+/-3.0%

400mA

LDO19 (Gb)

0.7-1.4V

+/-3.0%

400mA

LDO_RTC

2.5V

+/-2.0%

10mA

BUF_1V2

1.2V

+/-5.0%

10mA

2.4-3.675V

D

250mA

+/-2.5%

(500/100mA in bypass)

LDO7 (Cb)

1.2-2.475V

2.4-3.675V

+/-30mV

250mA

LDO8 (Cb)

1.2-2.475V

2.4-3.675V

+/-30mV

250mA

LDO9 (Cb)

1.2-2.475V

2.4-3.675V

+/-25mV

250mA

LDO10 (Ga)

0.7-1.2V

+/-4.5%

1150mA

C1912 15UF

20% 6.3V 2 X5R 0402-1 ROOM=PMU

ADJ.RANGE, LOW

U1801 D2333A1 WLCSP

SYM 1 OF 4

C1908 2.2UF

20% 2 6.3V X5R-CERM 0201-1

C

1

2.2UF

20% 2 6.3V X5R-CERM 0201-1

ROOM=PMU

18

C1913 ROOM=PMU

PP1V25_BUCK

VDD_LDO5 VDD_LDO6_BYP VDD_LDO7_8 VDD_LDO9 VDD_LDO10 VDD_LDO11_13 VDD_LDO14 VDD_LDO16 VDD_LDO18 VDD_LDO19 VDD_LDO19

T12 U11 T10 T16 U9 U10 T14

VBYPASS

R15

VLDO7 VLDO8 VLDO9

T17 P18 R18

VLDO9_FB

P17

VLDO10 VLDO11 VLDO12 VLDO13 VLDO14 VLDO15 VLDO16 VLDO17 VLDO18 VLDO19

G15 VPP_OTP

U1801 D2333A1 WLCSP

PP3V3_USB PP1V8_VA PP3V0_ALS_APS_CONVOY PP0V8_AOP PP3V0_NAND

LDO1 LDO2 LDO3 LDO4 LDO5

7 30 32 33 34 35 25 29 30 15 17

PP_ACC_VAR

T9 U13NC P7 U14 U16 U12 T18NC T11 U17 U18

LDO6

27 40

PP3V0_TRISTAR_ANT_PROX PP2V9_NH_AVDD PP1V8_HAWKING

29

PP0V9_NAND

17

PP1V8_ALWAYS PP3V0_MESA PP1V2_SOC PP1V8_MESA

LDO7 LDO8 LDO9

29 40 41 53

44

29 30

LDO10 LDO11 LDO12 LDO13 LDO14 LDO15 LDO16 LDO17 LDO18 LDO19

16

VBUF_1V2

20 21 38 8 10 16 38 48

#24989262

PP_LDO17 PP1V2_UT_DVDD PP1V2_NH_NV_DVDD

1/20W R1901 MF NOSTUFF 0201 1% 0.00 2 1 25

SYM 4 OF 4

B

A

A1 A11 A15 H8 A19 P13 A3 P14 A7 B11 B15 B19 B3 B7 C11 C15 C19 C3 C7 D11 D15 D19 D3 D7 E1 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E2 E3 E4 E5 E6 E7 E8 E9 F1 F17 F2 F3 F4

VSS

VSS

G17 G4 H17 H18 H19 H4 J17 J4 J8 K1 K17 K2 K3 K4 K8 L17 L4 L8 M17 M4 N17 N18 N19 N4 P1 P2 P3 P4 P15 R17 R4 T5 T15 T4 T6 T7 T8 U15 T13 U8 V1 V12 V19 V8

NC

J6 TP_DET

VBUF_1V2

P8

VPUMP

R5

PP1V2_REF

1

C1918

1

2.2UF

1

2.2UF

20% 2 6.3V X5R-CERM 0201-1

C1902 47NF

2

C1916

20% 6.3V X5R-CERM 01005

ROOM=PMU

C1921 2.2UF

20% 2 6.3V X5R-CERM 0201-1 ROOM=PMU

1

C1922 2.2UF

20% 2 6.3V X5R-CERM 0201-1 ROOM=PMU

1

20% 2 6.3V X5R 0201-1

ROOM=PMU

1

C1925 1.0UF

20% 2 6.3V X5R 0201-1

ROOM=PMU

C1935 1.0UF

20% 2 6.3V X5R-CERM 0201-1

ROOM=PMU

1

C1926 2.2UF

20% 2 6.3V X5R-CERM 0201-1

ROOM=PMU

1

C1923 2.2UF

20% 2 6.3V X5R 0201-1

ROOM=PMU

1

1

1.0UF

20% 2 6.3V X5R-CERM 0201-1

PMU_VPUMP

C1933

ROOM=PMU

1

1

C1930

1

2.2UF

20% 2 6.3V X5R 01005-1 ROOM=PMU

1

2.2UF

C1932 0.22UF

20% 2 6.3V X5R-CERM 0201-1 ROOM=PMU

C1927

1

C1904

ROOM=PMU

ROOM=PMU

ROOM=PMU

B

20% 2 6.3V X5R-CERM 0201-1

20% 2 6.3V X5R-CERM 0201-1

ROOM=PMU

C1919 2.2UF

2.2UF

20% 2 6.3V X5R-CERM 0201-1

#24989262:OTP-AO LDO17 default off,50mA Iout_max

VPUMP: 10nF min. @4.6V

53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

PP_VDD_MAIN 1

C1905 33PF

5% 2 16V NP0-C0G-CERM 01005 ROOM=PMU

1

C1909 220PF

5% 2 10V C0G-CERM 01005 ROOM=PMU

PMU_VSS_RTC 20 SYNC_MASTER=Sync

U15 = PMU XTAL GND

SYNC_DATE=06/06/2016

PAGE TITLE

SYSTEM POWER:PMU (2/3) DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

19 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

19 OF 81

IV ALL RIGHTS RESERVED

8

C

New for ADELYN

1

LDO

PP1V1_SDRAM

VDD_LDO1 VDD_LDO2_15 VDD_LDO3_17 VDD_LDO4 LDO INPUT

18 15

R12 V11 R10 R16 V9 V10 R14 P19 R19 R9 V13 V16 T19 V17 V18 U19

VLDO1 VLDO2 VLDO3 VLDO4 VLDO5_0 VLDO5_1 VLDO6

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

BUTTON PULL-UP RESISTORS 1

PP

SM

PP2001 P2MM-NSM ROOM=SOC

1

PP SM

PP1V8_SDRAM

PP2002 P2MM-NSM

NOSTUFF 1

R2008 100K

ROOM=SOC

1 46 41 40 37 36 32 21 20 18 16 53 52 48 47

PP1V8_ALWAYS

PP1V8_SDRAM

PP

SM

PP2003 P2MM-NSM ROOM=PMU

19 20 21

2

WLCSP

NO_XNET_CONNECTION 11 13 7

C2001

P9 P10 P11 M5 NC P12

15 13

40 37 13 7

AOP_TO_PMU_SLEEP1_REQUEST PMU_TO_AOP_SLEEP1_READY AOP_TO_PMU_ACTIVE_REQUEST PMU_TO_AOP_TRISTAR_ACTIVE_READY

R11 L11 L12 J12

PMU_TO_AOP_CLK32K

13

M9 NC M10

D101/D111 ONLY: TCXO_RF Supplies 32K 21 17 15 53 39 23 13

SYSTEM_ALIVE LCM_TO_MANY_BSYNC

R2020

47

2

5% 1/32W MF 01005

#24825674: Add R2020 to meet timing spec #26169957: R2020 to 100ohm

PMU_TO_AOP_IRQ_L

SYS_ALIVE FORCE_SYNC CRASH* IRQ*

I2C1_AP_SCL I2C_PMU_SDA_R

N13 M13

SCL SDA

N6 N5 P5

SCLK MOSI MISO

HIGH=FORCE PWM MODE

SPI_PMGR_TO_PMU_SCLK SPI_PMGR_TO_PMU_MOSI SPI_PMU_TO_PMGR_MISO

11 11

C

11

7 20

BUTTON_VOL_UP_L

44 12

NC

1 39 37

R2001

100PF

5% 16V 2 NP0-C0G 01005 ROOM=PMU

10KOHM-1%

2

01005 ROOM=PMU

40 20 36

FOREHEAD_NTC_RETURN

4

1

C2013

10% 2 10V X5R 01005

1

5% 16V NP0-C0G 2 01005 ROOM=PMU

RCAM_NTC_RETURN

01005 ROOM=PMU

XW2002 SHORT-20L-0.05MM-SM

B

1

2 OMIT

ROOM=SOC

2

01005 ROOM=PMU

1

PA_NTC_RETURN

PMU_XTAL1 PMU_XTAL2

1

2

01005 ROOM=PMU

V14 V15

1

N9

AMUX_A0 AMUX_A1 AMUX_A2 AMUX_A3 AMUX_A4 AMUX_A5 AMUX_A6 AMUX_A7 AMUX_AY AMUX_B0 AMUX_B1 AMUX_B2 AMUX_B3 AMUX_B4 AMUX_B5 AMUX_B6 AMUX_B7 AMUX_BY TDEV1 TDEV2 TDEV3 TDEV4 TDEV5 TCAL XTAL1 XTAL2

VDD_RTC

C2002

20% 2 6.3V X5R 0201 ROOM=PMU

2

C2011 100PF

5% 16V 2 NP0-C0G 01005 ROOM=PMU

1

1

R2010 3.92K

0.1% 1/20W MF 0201 2 ROOM=PMU

VDROOP0* G6 VDROOP1* G7

1

C2006 0.22UF

R2011 200K

PRE_UVLO_DET N8

PMU_PRE_UVLO_DET

1 11

16 18 20 21 32 36 37 40 41 46 47 48 52 53

NOSTUFF

R2015 220K 5% 1/32W MF 01005

12

2 ROOM=PMU

BUTTON_VOL_DOWN_L

11

20 44

14

NOTE:VDROOP_DET filtering is now inside Adelyn

14

19

IBAT VBAT BRICK_ID ADC_IN

L7 NC M7 NC H7 TRISTAR_TO_PMU_USB_BRICK_ID PMU_ADC_IN K7

BUTTON1 BUTTON2 BUTTON3 BUTTON4

M12 BUTTON_VOL_DOWN_L N12 BUTTON_POWER_KEY_L M11 BUTTON_RINGER_A N11 NC Reserved for MENU key on dev board

F16 F15 G14 F14 F13 G13 G12 H12 G11 G10 F9 G9 F8 G8 H9 H10 J9 J10 K9 K10 L9

PP1V8_SDRAM

2 ROOM=PMU

PMU_TO_AP_THROTTLE_CPU_L PMU_TO_AP_THROTTLE_GPU_L AP_VDD_CPU_SENSE AP_VDD_GPU_SENSE

GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21

R2007 220K

2 ROOM=PMU

BUTTON_POWER_KEY_L

44 20

1% 1/20W MF 201

PMU_TO_AP_PRE_UVLO_L

VDROOP0_DET F6 VDROOP1_DET F7

BUTTONO1 H11 BUTTONO2 J11 BUTTONO3 K11

NOSTUFF

PMU_TO_AP_BUF_VOL_DOWN_L PMU_TO_AP_BUF_POWER_KEY_L PMU_TO_AP_BUF_RINGER_A TIGRIS_TO_PMU_INT_L BB_TO_PMU_PCIE_HOST_WAKE_L PMU_TO_BBPMU_RESET_R_L WLAN_TO_PMU_HOST_WAKE NFC_TO_PMU_HOST_WAKE PMU_TO_NAND_LOW_BATT_BOOT_L

C 20 40 20

20 44 20 44 20 44

12

Button for two-finger reset: 20711463 and 21196187

12 12

21

R2000 1.00K

53

1

2

PMU_TO_BBPMU_RESET_L

53

5% 1/32W MF 01005 ROOM=PMU

53 53 17

NC_PMU_TO_GNSS_EN

PMUGPIO_TO_WLAN_CLK32K PMU_TO_BT_REG_ON

20 53 53

NC_GNSS_TO_PMU_HOST_WAKE

PMU_TO_WLAN_REG_ON BT_TO_PMU_HOST_WAKE PMU_TO_CODEC_DIGLDO_PULLDN PMU_TO_ACC_BUCK_SW_EN PMU_TO_BB_USB_VBUS_DETECT PMU_TO_NFC_EN PMU_TO_AP_FORCE_DFU_R PMU_TO_BOOST_EN PMU_TO_LCM_PANICB PMU_TO_HOMER_RESET_L

53 53 32

B

27 53

#24511807: Stuff for Carrier

R2009 0.00

53

1 23

RS

39

RS

PMU_TO_AP_FORCE_DFU

2

4 12

0% 1/32W MF 01005

36

I2C0_AP_SCL

37 47

GPIO21 = I2C SCL is for Chestnut dark current mitigation

RS

Sequencer controllable RS = requires sequencer

CRITICAL

Y2001

32.768KHZ-20PPM-12.5PF 1

1 C2003 22PF

2

1.60X1.00-SM ROOM=PMU

5% 16V CERM 2 01005

AP_NTC_RETURN

PMU_VREF

PRE_UVLO* N10

0.22UF

R2004 10KOHM-1%

R6 M6 P6 L5 L6 G16

PMU_VDD_RTC

2

SHORT-20L-0.05MM-SM ROOM=SOC

1

5% 16V 2 NP0-C0G 01005 ROOM=PMU

NC

XW2005

AP NTC

100PF

PMU_AMUX_BY

2

1

C2010 1

BBPMU_TO_PMU_AMUX3

OMIT

R2003 10KOHM-1%

AP_TO_PMU_TEST_CLKOUT

XW2004 SHORT-20L-0.05MM-SM

1

5% 16V NP0-C0G 2 01005 ROOM=PMU

1

4

CHESTNUT_TO_PMU_ADCMUX

OMIT

RADIO PA NTC

C2009 100PF

37

PMU_TCAL

XW2003 SHORT-20L-0.05MM-SM ROOM=SOC

PMUGPIO_TO_WLAN_CLK32K

53 20

J14 J15 J16 K16 K15 K14 J13 K13 K12

L14 L15 NC L16 M16 M15 M14 N16 N15 N14

FOREHEAD_NTC REAR_CAMERA_NTC RADIO_PA_NTC AP_NTC

OMIT ROOM=SOC

1

ACC_BUCK_TO_PMU_AMUX

53

R2002 2

27

7

ROOM=PMU PLACE_NEAR=U1801:2mm

10KOHM-1%

BBPMU_TO_PMU_AMUX1 BBPMU_TO_PMU_AMUX2

1000PF

REAR CAMERA NTC

LCM_TO_CHESTNUT_PWR_EN TRISTAR_TO_PMU_USB_BRICK_ID PP1V2_MAGGIE PMU_AMUX_AY

53

53

TBD

1 C2008 100PF

AP_TO_PMU_AMUX_OUT PMU_ADC_IN NC

FOREHEAD NTC

C2007 1

VREF J7

D 19 20 21

5% 1/32W MF 01005

ROOM=PMU

SLEEP_32K OUT_32K

H5 L13 L10 G5

NC 13

SLEEP1_REQ SLEEP1_RDY ACTIVE_REQ ACTIVE_RDY

COMPARATOR

13

13

I2C1_AP_SDA

PMU_IREF

20% 6.3V 2 X5R 0201

ADC

10% 2 10V X5R 01005 ROOM=PMU

100

IREF K6

Active high with int 200k PD

1000PF

1

RESET_IN1 RESET_IN2 RESET_IN3 RESET* SHDN

BUTTONS

1

AP_TO_PMU_WDOG_RESET TRISTAR_TO_PMU_HOST_RESET AP_TO_PMU_SOCHOT_L PMU_TO_SYSTEM_COLD_RESET_L

REFS

7

2 ROOM=PMU

40

47

1

SYM 3 OF 4

GPIO

2 ROOM=PMU

ROOM=PMU

PP1V8_ALWAYS

D2333A1

5% 1/32W MF 01005

RESETS

2 ROOM=PMU

U1801

R2012 10K

PMGR

5% 1/32W MF 01005

1

AMUX

5% 1/32W MF 01005

R2005 100K

NTC

1

R2006 100K

XTAL

1

5% 1/32W MF 01005

BUTTON_RINGER_A

44 20

D

16 18 20 21 32 36 37 40 41 46 47 48 52 53

ROOM=PMU 19

1

C2004 22PF

5% 16V 2 CERM 01005

PMU_VSS_RTC

ROOM=PMU

XW2001

SHORT-20L-0.05MM-SM

1

2

ROOM=PMU

A

OMIT

NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SYSTEM POWER:PMU (3/3) DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

20 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

20 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

TIGRIS CHARGER D

D

PP_VDD_MAIN 1

C2113 10UF

20% 2 6.3V CERM-X5R 0402-9

1

C2114 10UF

20% 2 6.3V CERM-X5R 0402-9

ROOM=CHARGER

4.2UF

10% 2 16V X5R-CERM 0402-1 ROOM=CHARGER

1

C2111 4.2UF

10% 2 16V X5R-CERM 0402-1 ROOM=CHARGER

1

C2112 100PF

5% 2 35V NP0-C0G 01005 ROOM=CHARGER

1

220PF

C

C2115 2.2UF

5% 2 10V C0G-CERM 01005

20% 2 6.3V X5R-CERM 0201-1

ROOM=CHARGER

28

TO TRINITY

C2101

1

4.2UF

20 19

PP1V8_ALWAYS 1

R2101

10% 2 16V X5R-CERM 0402-1 ROOM=CHARGER

1

330PF

10% 2 16V CER-X7R 01005 ROOM=CHARGER 47

100K

5% 1/32W MF 2 01005 ROOM=CHARGER

47

20 17 15

R2103 20

TIGRIS_TO_PMU_INT_L

C2110

1

100

5% 1/32W MF 01005

#24558610: Change to 100ohm

40

G3 E4

I2C1_AP_SDA I2C1_AP_SCL

E3

SYSTEM_ALIVE TRISTAR_TO_TIGRIS_VBUS_OFF

F4: 100 kOhm pullup to VLDO (regulated output voltage)

2

TIGRIS_TO_PMU_INT_R_L

ROOM=CHARGER

TIGRIS_VBUS_DETECT

F3

1

30.1K 2 1% 1/32W MF 01005

WCSP

ROOM=CHARGER

CRITICAL

SDA SCL SYS_ALIVE VBUS_OVP_OFF INT VBUS_DET TEST

LDO BOOT

G5

A4 BUCK_SW B4 BUCK_SW D4 BUCK_SW C4 BUCK_SW A1 BAT B1 BAT D1 BAT C1 BAT E1 BAT_SNS E2 ACT_DIODE G1 HDQ_HOST F2 HDQ_GAUGE

C2106

0.047UF 1

TIGRIS_BOOT ROOM=CHARGER

ROOM=CHARGER

C2102

1

330PF

2

BGA

10% 16V X5R 0201

ROOM=CHARGER

1

D

220PF

5% 10V 2 C0G-CERM 01005 ROOM=CHARGER

10% 16V CER-X7R 2 01005 ROOM=CHARGER

TIGRIS_BUCK_LX

PP_BATT_VCC VBATT_SENSE

22

1

SWI_AP_BI_TIGRIS TIGRIS_TO_BATTERY_SWI_1V8

C2108

1

330PF

TIGRIS_ACTIVE_DIODE 12

R2102 1 47 46 41 40 37 36 32 20 18 16 53 52 48

4 22

1

C2118 2.2UF

20% 2 6.3V X5R-CERM 0201-1

ROOM=CHARGER

ROOM=CHARGER

5% 1/32W MF 01005 ROOM=CHARGER 2

PP1V8_SDRAM

1

20% 2 6.3V X5R-CERM 0201-1

ROOM=CHARGER

100K

C2117 2.2UF

10% 2 16V CER-X7R 01005

NOSTUFF

A3 B3 D3 C3

B

USB_VBUS_DETECT

G2 F1

R2104 7

F4

VBUS VBUS VBUS VBUS VBUS

U2101 SN2400AB0

R2105

B

Q2102

40.2K

RV3C002UN DFN

D

S

2

G

1

1% 1/32W MF 2 01005

3

PP5V0_USB

PMID

PGND PGND PGND PGND

41 40 4

A5 B5 D5 C5 E5

CSD68827W G

#25112685,Remove Snub

C2105

G4

Q2101

A1

NO_XNET_CONNECTION

F5

CRITICAL

S

ROOM=CHARGER

C1 C2 C3

5% 2 35V NP0-C0G 01005 ROOM=CHARGER

C2109

A2 B2 D2 C2

100PF

1

VDD_MAIN VDD_MAIN VDD_MAIN VDD_MAIN

C2103

C2104

A2 A3 B1 B2 B3

1 1

ROOM=CHARGER

TIGRIS_LDO

TIGRIS_PMID

C

4 9 10 18 19 23 25 26 27 28 30 31 33 34 35 37 39 40 41 46 53

TIGRIS_TO_BATTERY_SWI

22

SYM_VER_1

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SYSTEM POWER:CHARGER DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

21 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

21 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D

BATTERY CONNECTOR THIS ONE ON MLB

--->

516S00172 (matches d10 mlb MCO rev 27)

C

C XW2201

SHORT-20L-0.05MM-SM 1 2

VBATT_SENSE

21

ROOM=BATTERY_B2B

J2201 RCPT-BATT-SHORT F-ST-SM

21

TIGRIS_TO_BATTERY_SWI

1

100

5% 1/32W MF 01005 ROOM=BATTERY_B2B

1 3 4

TIGRIS_BATTERY_SWI_CONN

2 1

C2201 56PF

9

5% 2 25V NP0-C0G-CERM 01005 ROOM=BATTERY_B2B

NO_XNET_CONNECTION=1

11 8

7

R2201

PLACE_NEAR=J2201:2mm

PP_BATT_VCC

5 2 6

1

C2202 56PF

5% 2 25V NP0-C0G-CERM 01005

10 12

ROOM=BATTERY_B2B

1

C2203 100PF

5% 2 16V NP0-C0G 01005

ROOM=BATTERY_B2B

1

4 21

C2204 220PF

5% 2 10V C0G-CERM 01005 ROOM=BATTERY_B2B

ROOM=BATTERY_B2B

CRITICAL

ALLOW_APPLE_PREFIX

B

B

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SYSTEM POWER:BATTERY CONN DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

22 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

22 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D

BOOST C

C When VDD_MAIN < 3.4, boosts to 3.4 Otherwise tracks VDD_MAIN

PP_VDD_MAIN 1

C2309 10UF

20% 6.3V 2 CERM-X5R 0402-9

ROOM=BOOST

1

L2301 ROOM=BOOST

C2301

0.47UH-20%-4.2A-0.048OHM 1 2 SYS_BOOST_LX

4.7UF

20% 2 6.3V X5R-CERM1 402 ROOM=BOOST

PIUA20121T-SM 20

PMU_TO_BOOST_EN 1

A3 A4

VIN

C3 C4

SW SW

A1

EN

VIN

U2301

VOUT VOUT

SN61280D DSBGA ROOM=BOOST

B3 B4

PP_VDD_BOOST 1

C2302 15UF

20% 2 6.3V X5R 0402-1 ROOM=BOOST

R2301 511K

47

I2C0_AP_SCL

B2

47

I2C0_AP_SDA

C2

SDA

B1

VSEL

C1

BYP*

A2

GPIO

1% 1/32W MF 2 01005

53 39 20 13

LCM_TO_MANY_BSYNC HIGH=FORCE PWM MODE

SCL

D2 D3 D4

PGND

1

C2303 15UF

20% 2 6.3V X5R 0402-1 ROOM=BOOST

1

C2304 15UF

20% 2 6.3V X5R 0402-1 ROOM=BOOST

1

C2307 15UF

20% 2 6.3V X5R 0402-1 ROOM=BOOST

1

C2308 15UF

20% 2 6.3V X5R 0402-1 ROOM=BOOST

1

19 25 30 32 37 38 53

C2306 220PF

5% 2 10V C0G-CERM 01005 ROOM=BOOST

AGND D1

53 28 27 26 25 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 30

Control details from Radar 19634006

B

B

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

SYSTEM POWER:BOOST DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

23 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

23 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

MAGNESIUM - COMPASS

CARBON - ACCEL & GYRO INVENSENSE, MPU-6800: C2403=0.1UF

D 24

BOMOPTION=CARBON_1

C2418

1

1

2.2UF

C2402 0.1UF

20% 2 6.3V X5R-CERM 0201-1

20% 2 6.3V X5R-CERM 01005

ROOM=CARBON

PP1V8_MAGGIE_IMU

BOMOPTION=CARBON_1

1

C2415

1

BOMOPTION=CARBON_1

1

20% 2 6.3V X5R-CERM 0201-1

VDD

ROOM=MAGNESIUM

ROOM=MAGNESIUM

ROOM=CARBON

C2408 2.2UF

20% 2 6.3V X5R-CERM 01005

20% 2 6.3V X5R-CERM 01005

ROOM=CARBON

1

C2401 0.1UF

0.1UF

16

36 24 18

PP1V8_MAGGIE_IMU_FILT

PP1V8_MAGGIE_IMU

U2402

BOMOPTION: CARBON_1 #25765850:Update Carbon APN

1

36 24 18

C4

D

HSCDTD601A-19A

BOMOPTION=CARBON_1

R2401

VDD

100K

NC

VDDIO

U2401

5% 1/32W MF 2 01005

NC NC NC NC

MPU-6900-21 LGA

ROOM=SOC

SPI_AOP_TO_ACCEL_GYRO_CS_L

13

5 8 14

GYRO_CHARGE_PUMP

SPC 2 SDI 3 SDO 4

CS FSYNC REGOUT

SPI_AOP_TO_IMU_SCLK_R1 SPI_AOP_TO_IMU_MOSI SPI_IMU_TO_AOP_MISO

13 24 13 24

24

BOMOPTION=CARBON_1

1

13 24

C2419

B1 B3 D1 D2

RSV RSV RSV RSV

7

ACCEL_GYRO_TO_AOP_INT

INT

DRDY

6

ACCEL_GYRO_TO_AOP_DATARDY

C2403

13 24

SCL/SCK A3

SPI_AOP_TO_IMU_SCLK_R1

13 24

SPI_AOP_TO_COMPASS_CS_L

13

TRG/SE C3 NC

114K INT PD

DRDY A1

ROOM=MAGNESIUM

COMPASS_TO_AOP_INT

13

CRITICAL VSS

ROOM=CARBON

PP2404 1 SM PP

ROOM=MAGNESIUM

15 GND

13 GND

12 GND

ROOM=CARBON

11 GND

9 GND

10% 2 6.3V X6S 0201

C

SPI_AOP_TO_IMU_MOSI

P2MM-NSM

0.1UF

10 GND

1

SDA/SDI A4

CSB A2

1.09M INT PU

CRITICAL

BOMOPTION=CARBON_1

13 24

C1

ROOM=CARBON

SPI_IMU_TO_AOP_MISO

D4 RST*

PP1V8_MAGGIE_IMU_FILT

+/-0.1PF 2 16V NP0-C0G 01005

13

SDO B4

114K INT PU

5PF

13

LGA

C2 VPP

PP2401 1 SM

C

PP

P2MM-NSM ROOM=MAGNESIUM

PP2402 1

#25782019:Add 0ohm

PP

SM

P2MM-NSM

ROOM=MAGNESIUM

R2404 36 24 18

PP1V8_MAGGIE_IMU

1

0.00

2

24

0% 1/32W MF 01005 ROOM=BOT_CARBON

24

PP2403 1 SM

PP1V8_MAGGIE_IMU_R 1

C2448

1

2.2UF

C2442 0.1UF

20% 2 6.3V X5R-CERM 0201-1

20% 2 6.3V X5R-CERM 01005

ROOM=BOT_CARBON

PP1V8_MAGGIE_IMU_R

PP

1

P2MM-NSM

C2445

ROOM=MAGNESIUM

0.1UF

#25740540:PP for South Carbon MOSI

20% 2 6.3V X5R-CERM 01005

ROOM=BOT_CARBON

1

ROOM=BOT_CARBON

PP

SM

PP2440 P2MM-NSM

1

R2441 100K

1

16

ROOM=HOMER

VDD

VDDIO

U2404

5% 1/32W MF 2 01005

MPU-6900-21 LGA

ROOM=SOC

SPI_AOP_TO_BOT_ACCEL_GYRO_CS_L

13

5 8 14

BOT_GYRO_CHARGE_PUMP

SPC 2 SDI 3 SDO 4

CS FSYNC REGOUT

SPI_AOP_TO_IMU_SCLK_R2 SPI_AOP_TO_IMU_MOSI SPI_IMU_TO_AOP_MISO

13

NOSTUFF

13 24

1

13 24

XW2404 SHORT-20L-0.05MM-SM

6

BOT_ACCEL_GYRO_TO_AOP_DATARDY

13

+/-0.1PF 2 16V NP0-C0G 01005 ROOM=BOT_CARBON

ROOM=BOT_CARBON

ROOM=BOT_CARBON NO_XNET_CONNECTION=1

10% 2 6.3V X6S 0201

ROOM=BOT_CARBON

B 15 GND

XW2404 to balance Via/Cu at INT pin

13 GND

CRITICAL 12 GND

0.1UF

BOT_ACCEL_GYRO_TO_XW_INT

DRDY

10 GND

C2443

INT

9 GND

B

1

2

7

11 GND

1

NC

C2449 5PF

OMIT

PHOSPHORUS

#24593845 BOSCH (APN:338S00188): nostuff C2420/C2421/C2422/C2423 and R2403 PU ST (APN:338S00230): stuff C2420-C2423, C2420R2422 with 155S00017, stuff R2403 PU C2420=4pF(131S0253),C2405=3pF(131S0251) per #25691124

R2422 24

1

PP1V8_MAGGIE_IMU_FILT NOSTUFF

1

C2413

1

0.1UF

1

0.1UF

20% 2 6.3V X5R-CERM 01005

C2420 4PF

20% 2 6.3V X5R-CERM 01005

ROOM=PHOSPHORUS

+/-0.1PF 2 16V NP0-C0G 01005

ROOM=PHOSPHORUS

ROOM=PHOSPHORUS

1

2

0% 1/32W MF 01005

C2421 20PF

5% 2 16V NP0-C0G-CERM 01005

0.00

ROOM=PHOSPHORUS

ROOM=PHOSPHORUS

PP1V8_MAGGIE_IMU NOSTUFF

1

C2422 20PF

5% 2 16V NP0-C0G-CERM 01005 ROOM=PHOSPHORUS

18 24 36

NOSTUFF

1

C2423 5.6PF

+/-0.1PF 2 16V NP0-C0G-CERM 01005 ROOM=PHOSPHORUS

1

C2414 2.2UF

20% 2 6.3V X5R-CERM 0201-1 ROOM=PHOSPHORUS

BOSCH: Internal PU

1

A 2

NOSTUFF

R2403 100K 5% 1/32W MF 01005

ROOM=SOC

6

PP1V8_MAGGIE_IMU_FILT 8

24

C2405

NOSTUFF

VDD

VDDIO

U2403

24 13 24 13

13

SPI_AOP_TO_IMU_MOSI SPI_AOP_TO_IMU_SCLK_R1 SPI_AOP_TO_PHOSPHORUS_CS_L

BMP284AA

3 SDI 4 SCK 2 CS*

LGA

SDO 5

SPI_IMU_TO_AOP_MISO

SYNC_MASTER=Sync

13 24

SYNC_DATE=06/06/2016

PAGE TITLE

IRQ 7

SENSORS

PHOSPHORUS_TO_AOP_INT_L 13

DRAWING NUMBER

1

GND

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

24 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

24 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

UTAH POWER

5

4

3

2

1

IO FILTERS

Scrub voltage selection

NOTE: OUTPUT IMPDEANCE MUST BE >0.005-OHM IN ORDER TO MEET CAP ESR REQUIREMENT PER LDO SPEC. VENDOR ALSO RECOMMENDS CIN = COUT FOR STABILITY

U2501

D PP_VDD_BOOST 1

C2527 2.2UF

A1

ROOM=RCAM_B2B

B1

20% 2 6.3V X5R-CERM 0201-1

PP2V9_UT_AVDD_CONN See Page46: D11x

VEN

D

150OHM-25%-200MA-0.7DCR 1

C2507 is 4UF

C2502 0.22UF

GND

10% 2 6.3V CER-X5R 01005

B2

53 38 37 32 30 23 19

FL2504

LP5907UVX2.925-S DSBGA VIN VOUT A2

ROOM=RCAM_B2B

1

45 46

9

1

AP_TO_UT_CLK

C2504

1

220PF

01005

C2512

1

ROOM=RCAM_B2B

100PF

ROOM=RCAM_B2B

AP_TO_UT_CLK_CONN

45

AP_TO_UT_SHUTDOWN_CONN_L

45

C2513 56PF

5% 2 25V NP0-C0G-CERM 01005

5% 2 16V NP0-C0G 01005

5% 2 10V C0G-CERM 01005

ROOM=RCAM_B2B

2

ROOM=RCAM_B2B

ROOM=RCAM_B2B

NOSTUFF

L2501

FL2501

33-OHM-25%-1500MA 30 18

1

PP2V8_UT_AF_VAR

150OHM-25%-200MA-0.7DCR

2

PP2V8_UT_AF_VAR_CONN

0201

1

ROOM=RCAM_B2B

C2505

1

2.2UF

45

9

1

AP_TO_UT_SHUTDOWN_L

C2501

ROOM=RCAM_B2B

ROOM=RCAM_B2B

L2502

FL2503

33-OHM-25%-1500MA 1

C2514 220PF

5% 10V 2 C0G-CERM 01005

5% 2 10V C0G-CERM 01005

ROOM=RCAM_B2B

PP3V0_ALS_APS_CONVOY

1

ROOM=RCAM_B2B

220PF

20% 2 6.3V X5R-CERM 0201-1

30 29 19

2 01005

150OHM-25%-200MA-0.7DCR

PP3V0_UT_SVDD_CONN

2 0201

1

ROOM=RCAM_B2B

C2519

1

2.2UF

26

1

UT_AND_NV_TO_STROBE_DRIVER_STROBE

UT_AND_NV_TO_LED_DRIVER_STROBE_EN_CONN

2 01005

C2518

1

ROOM=RCAM_B2B

30 45

C2515 220PF

220PF

20% 2 6.3V X5R-CERM 0201-1 ROOM=RCAM_B2B

C

45

5% 2 10V C0G-CERM 01005 ROOM=RCAM_B2B

5% 2 10V C0G-CERM 01005 ROOM=RCAM_B2B

C

L2503

33-OHM-25%-1500MA 19

PP1V2_UT_DVDD

1

PP1V2_UT_VDD_CONN

2 0201

1

ROOM=RCAM_B2B

C2506 2.2UF

20% 2 6.3V X5R-CERM 0201-1

1

C2508

1

2.2UF

2.2UF

20% 6.3V 2 X5R-CERM 0201-1

20% 2 6.3V X5R-CERM 0201-1

ROOM=RCAM_B2B

C2510

ROOM=RCAM_B2B

ROOM=RCAM_B2B

1

C2503 220PF

5% 2 10V C0G-CERM 01005 ROOM=RCAM_B2B

1

45

C2521 15PF

5% 2 16V NP0-C0G-CERM 01005 ROOM=RCAM_B2B Desense for Wifi frequencies

L2504

33-OHM-25%-1500MA 29 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 30

1

PP1V8

2

PP1V8_UT_CONN

0201

1

ROOM=RCAM_B2B

C2509 1.0UF

20% 2 6.3V X5R 0201-1

1

45

LPDP FILTERS

C2511 220PF

AC return path for LPDP

5% 2 10V C0G-CERM 01005 ROOM=RCAM_B2B

ROOM=RCAM_B2B

53 28 27 26 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 30

which is referenced to GND and VDD_MAIN

PP_VDD_MAIN 1

C2522 33PF

5% 2 16V NP0-C0G-CERM 01005

B

ROOM=RCAM_B2B

10

90_LPDP_UT_TO_AP_D2_P

90_LPDP_UT_TO_AP_D2_P MAKE_BASE=TRUE

10

90_LPDP_UT_TO_AP_D2_N

90_LPDP_UT_TO_AP_D2_N MAKE_BASE=TRUE

10

90_LPDP_UT_TO_AP_D3_P

90_LPDP_UT_TO_AP_D3_P MAKE_BASE=TRUE

10

90_LPDP_UT_TO_AP_D3_N

90_LPDP_UT_TO_AP_D3_N MAKE_BASE=TRUE

1

C2528

1

33PF

33PF

5% 2 16V NP0-C0G-CERM 01005

5% 2 16V NP0-C0G-CERM 01005

ROOM=RCAM_B2B

C2523

1 20% X5R-CERM 1 ROOM=RCAM_B2B 20% X5R-CERM ROOM=RCAM_B2B

C2524 C2525

1 20% X5R-CERM 1 ROOM=RCAM_B2B 20% X5R-CERM ROOM=RCAM_B2B

C2526

C2529

B

ROOM=RCAM_B2B

2 6.3V 01005 2 6.3V 01005

0.1UF 90_LPDP_UT_TO_AP_D2_CONN_P

45

0.1UF 90_LPDP_UT_TO_AP_D2_CONN_N

45

2 6.3V 01005 2 6.3V 01005

0.1UF 90_LPDP_UT_TO_AP_D3_CONN_P

45

0.1UF 90_LPDP_UT_TO_AP_D3_CONN_N

45

C2530 0.1UF 10

LPDP_UT_BI_AP_AUX

LPDP_UT_BI_AP_AUX

1

LPDP_UT_BI_AP_AUX_CONN

2

45

MAKE_BASE=TRUE

20% 6.3V X5R-CERM 01005

1

ROOM=RCAM_B2B

A

C2520 56PF

5% 2 25V NP0-C0G-CERM 01005 ROOM=RCAM_B2B

SYNC_MASTER=sync

SYNC_DATE=05/17/2016

PAGE TITLE

B2B FILTERS: UTAH DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

25 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

25 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

STROBE DRIVERS INSIDE NEO SIP MODULE D10/sip_neo

D

D

M2600 53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

PP_VDD_MAIN

C2609

NEO SIP

C2610

1

10UF

10UF

20% 6.3V CERM-X5R 2 0402-9

25

53 46 37

1

SYM 1 OF 3

220PF

B8 D2 D3

5% 10V C0G-CERM 2 01005

20% 6.3V CERM-X5R 2 0402-9

ROOM=STROBE

9

C2613

1

ROOM=STROBE

ROOM=STROBE

C9

AP_TO_STROBE_DRIVER_HWEN

C8

UT_AND_NV_TO_STROBE_DRIVER_STROBE

D8

BB_TO_STROBE_DRIVER_GSM_BURST_IND 48

I2C_ISP_UT_SDA

48

I2C_ISP_UT_SCL

B9 B10

ROOM=STROBE

VDD VDD VDD

CRITICAL

HWEN1

D9 LED1 D10 LED1

PP_STROBE_DRIVER1_COOL_LED

44 45

D6 LED2 D7 LED2

PP_STROBE_DRIVER1_WARM_LED

44 45

STB1 NTC

C10

STROBE_MODULE_NTC

44

GSM1 SDA1 SCL1

C

C M2600

PP_VDD_MAIN

20% 6.3V 2 CERM-X5R 0402-9 ROOM=STROBE2

C2612

1

10UF

20% 6.3V 2 CERM-X5R 0402-9 ROOM=STROBE2

C2614

SIP

1

SYM 2 OF 3

220PF

5% 10V 2 C0G-CERM 01005

B18 B19 D13

ROOM=STROBE

C12 C13

VDD VDD VDD

PP_STROBE_DRIVER2_COOL_LED

LED1 B11 LED1 B12

PP_STROBE_DRIVER2_WARM_LED

LED2 B14 LED2 B15

HWEN0

44 45

A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B2 B3 B4 B5 B6 B7 B16 B17 B20 C1 C2 C3 C4 C5 C6 C7

44 45

STB0 NTC C11

B13

GSM0

46

I2C_ISP_NV_SDA

D12

SDA2

46

I2C_ISP_NV_SCL

D11

SCL2

B

53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

PP_VDD_MAIN 1

C2617 220PF

5% 2 10V C0G-CERM 01005 ROOM=STROBE2

1

C2618 220PF

5% 2 10V C0G-CERM 01005 ROOM=STROBE2

NEO SIP

SYM 3 OF 3

A1 B1

AC return path for plane edge termination, which occurs near the Strobe modules.

M2600

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND2 GND2S

10UF

1

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

C14 C15 C16 C17 C18 C19 C20 D1 D4 D5 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19

B

E20 D20

C2611

NEO

GND1 GND1S

53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

CDS_LIB=apple

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

CAMERA:STROBE DRIVER DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

26 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

26 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

ACCESSORY BUCK #25761020:Add Bypass 0ohm NOSTUFF

R2711 1

D

0.00

2

D

1% 1/20W MF 0201

From PMU LDO6

ROOM=ACC_BUCK

OMIT_TABLE

1

U2710 53 28 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 30

PP_VDD_MAIN

C2704

1

2.2UF

FPF1204UCX WLCSP-COMBO A2 VIN VOUT A1

2.2UF

20% 2 6.3V X5R-CERM 0201-1

PP_VDD_MAIN_ACC_BUCK_VIN

20% 2 6.3V X5R-CERM 0201-1

ROOM=PMU

B2 ON

1 ROOM=ACC_BUCK

From PMU GPIO14

2.2UF

GND

100K

5% 1/32W MF 2 01005 ROOM=ACC_BUCK

1

PMEG3002ESF

ROOM=ACC_BUCK

R2710

D2700 SOD962-2

A ROOM=ACC_BUCK

100K

FET Changes per #25687842 4/12/2016

1% 1/32W MF 2 01005

A2

R2700

K

20% 2 6.3V X5R-CERM 0201-1

B1 1

C2700

Q2700

ROOM=ACC_BUCK

PMCM4401VPE

VIN

0.47UH-20%-2.52A-0.08OHM

C

A1 VSEL

AP_TO_ACC_BUCK_VSEL

From AP GPIO1

SW FB

B1

ACC_BUCK_SW

1

C1

ACC_BUCK_FB

27

2

46

PP_ACC_BUCK_VAR

B1

PIGA1608-SM

ROOM=ACC_BUCK

1

R2701 100K

5% 1/32W MF 2 01005 ROOM=ACC_BUCK

OMIT

GND 1

C2710 0.22UF

A2 B2

ROOM=ACC_BUCK

1

C2702 10UF

C2

12

EN

20% 2 6.3V CERM-X5R 0402-9

10% 2 6.3V CER-X5R 01005

R2705 10K

ROOM=ACC_BUCK

1

ROOM=ACC_BUCK

1

C2703

1

220PF

XW2700

0.1UF

5% 2 10V C0G-CERM 01005

20% 2 6.3V X5R-CERM 01005

ROOM=ACC_BUCK

27

SHORT-20L-0.05MM-SM 1 2

ACC_BUCK_FB

ROOM=TRISTAR

PP_ACC_VAR

Q2701

ROOM=ACC_BUCK NO_XNET_CONNECTION=1 PLACE_NEAR=Q2700:2mm

ROOM=ACC_BUCK

1

#25172498

1

0.1% 1/32W TF 2 01005

B1

19 27 40

C2708

20% 2 6.3V CER-X5R 0201

2 OMIT

R2702 200K

C

4UF

PMCM4401VPE WLCSP

5% 1/32W MF 01005 2 ROOM=ACC_BUCK

XW2707 SHORT-20L-0.05MM-SM

A2 B2

ROOM=TRISTAR

ROOM=TRISTAR

1 NO_XNET_CONNECTION=1

#25741319: Change to 4UF

ROOM=ACC_BUCK

ACC_BUCK_TO_PMU_AMUX

A1 G

20

C2701

To Tristar on Pg40

A1 G

WLCSP B2

L2700

#25370332: For EMC #25919133: C2707 on P46 D

FAN53612-1.5V-1.9V ACC_BUCK_EN

WLCSP

CRITICAL

D

U2700

S

PMU_TO_ACC_BUCK_SW_EN

ROOM=PMU

S

20

C2705

PMU_AMUX_B3 FOR NOW

ACT_DIODE_TO_COMP_SENSE ROOM=TRISTAR

1

R2704 200K

ACT_DIODE_TO_COMP_OUT

0.1% 1/32W TF 2 01005 ROOM=ACC_BUCK

ACT_DIODE_TO_COMP_POS 40 27 19

PP_ACC_VAR

C2706

1

5

0.22UF

10% 6.3V 2 CER-X5R 01005

VCC

U2701

ROOM=ACC_BUCK

SCY992200A 4 IN+

UDFN VOUT 6

B

ACT_DIODE_TO_COMP_NEG

1

3 IN-

R2706

NC 2

B NC

#25987909: To Resistor Divider

VEE 1

200K

1

ROOM=ACC_BUCK

0.1% 1/32W TF 2 01005

R2703 200K

0.1% 1/32W TF 2 01005

ROOM=ACC_BUCK

ROOM=ACC_BUCK

A

SYNC_MASTER=sync

SYNC_DATE=05/17/2016

PAGE TITLE

Accessory: Buck Circuit DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

27 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

27 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D

SIP 53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

C

L4 M4 N4

PP_VDD_MAIN

V2 V3

VDD_T VDD_T VDD_T

VDD_A VDD_A

SYM 1 OF 6

SIP TIG L6 TIG M6 TIG N6

TIGRIS_BUCK_LX

21

53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

PP_VDD_MAIN

D5 D6

VDD1_2 VDD1_2

F2 G2 H2 J2

VDDX_1 VDDX_1 VDDX_1 VDDX_1

SYM 4 OF 6

M2800

M2800

TRINITY_BLUE

TRINITY_BLUE

SIP

SIP

SYM 2 OF 6

SYM 5 OF 6

ARC X2 ARC X3

ARC1_LX

35

D2 D3

VDD2_2 VDD2_2

Q2 R2 S2 T2

VDDX_1 VDDX_1 VDDX_1 VDDX_1

F6 G6 H6 J6

BL_SW1_LX

BL1_2 B5 BL1_2 B6

BL_SW2_LX

37

Q6 R6 S6 T6

BL34_SW1_LX

46

BL2_2 B2 BL2_2 B3

BL34_SW2_LX

46

BL1_1 BL1_1 BL1_1 BL1_1

BL2_1 BL2_1 BL2_1 BL2_1

37

M2800 TRINITY_BLUE SIP V5 V6

B

VDD_S VDD_S

SYM 3 OF 6

SPK SPK

X5 X6

SPEAKERAMP1_LX

34

A

M2800 TRINITY_BLUE SIP SYM 6 OF 6

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

M5 M7 N1 N2 N3 N5 N7 P1 P2 P3 P4 P5 P6 P7 Q1 Q3 Q4 Q5 Q7 R1 R3 R4 R5 R7 S1 S3 S4 S5 S7 T1 T3 T4 T5 T7 U1 U2 U3 U4 U5 U6 U7 V1 V4 V7 W1 W2 W3 W4 W5 W6 W7 X1 X4 X7 Y1 Y2 Y3 Y4 Y5

C

B

Y7 GND2 Y6 GND2S

M2800 TRINITY_BLUE

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

A1 GND1 A2 GND1S

M2800 TRINITY_BLUE

A3 A4 A5 A6 A7 B1 B4 B7 C1 C2 C3 C4 C5 C6 C7 D1 D4 D7 E1 E2 E3 E4 E5 E6 E7 F1 F3 F4 F5 F7 G1 G3 G4 G5 G7 H1 H3 H4 H5 H7 J1 J3 J4 J5 J7 K1 K2 K3 K4 K5 K6 K7 L1 L2 L3 L5 L7 M1 M2 M3

SYNC_MASTER=sync

SYNC_DATE=05/17/2016

PAGE TITLE

TRINITY:FF SPECIFIC DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

28 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

28 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

NEW HAMPSHIRE POWER

FL2913

1

2 0201

1

C2914

1

0.1UF

1

PP3V0_ALS_APS_CONVOY

30 25 19

PP1V8_NH_IO_CONN

ROOM=FOREHEAD

2

45

PP3V0_ALS_CONVOY_CONN

01005

C2902

C2917

1

ROOM=FOREHEAD

45

C2926 220PF

20% 2 6.3V X5R-CERM 0201-1

5% 2 10V C0G-CERM 01005

5% 2 10V C0G-CERM 01005 ROOM=FOREHEAD

ROOM=FOREHEAD

ROOM=FOREHEAD

ROOM=FOREHEAD

1

2.2UF

220PF

20% 2 6.3V X5R-CERM 01005

D

1

150OHM-25%-200MA-0.7DCR

33-OHM-25%-1500MA

PP1V8

2

PROX, ALS, & CONVOY POWER

FL2901

17 16 13 12 11 9 8 7 5 52 48 47 46 39 30 25 18

3

D

FL2902

33-OHM-25%-1500MA 30 19

PP1V2_NH_NV_DVDD

1

PP1V2_NH_DVDD_CONN

2 0201

1

ROOM=FOREHEAD

C2916 2.2UF

20% 2 6.3V X5R-CERM 0201-1

1

C2915

1

0.1UF

C2903

FL2910

220PF

5% 2 10V C0G-CERM 01005

20% 2 6.3V X5R-CERM 01005 ROOM=FOREHEAD

ROOM=FOREHEAD

45

150OHM-25%-200MA-0.7DCR PP3V0_TRISTAR_ANT_PROX

53 41 40 19

ROOM=FOREHEAD

1

2

FL2903

C2927

1

2.2UF

1

PP2V9_NH_AVDD

1

ROOM=FOREHEAD

10-OHM-750MA 19

PP3V0_PROX_CONN

01005

2

PP2V9_NH_AVDD_CONN

220PF

20% 2 6.3V X5R-CERM 0201-1

#24511567: Remove C2918

45

5% 2 10V C0G-CERM 01005

ROOM=FOREHEAD

01005-1

1

ROOM=FOREHEAD

C2909 2.2UF

20% 2 6.3V X5R-CERM 0201-1 ROOM=FOREHEAD

1

C2901

1

0.1UF

220PF

20% 2 6.3V X5R-CERM 01005

5% 2 10V C0G-CERM 01005 ROOM=FOREHEAD

ROOM=FOREHEAD

NO_XNET_CONNECTION=1

1

SPEAKER2

FL2907

150OHM-25%-200MA-0.7DCR 1

AP_TO_NH_CLK

2

AP_TO_NH_CLK_CONN

01005

C

ROOM=FOREHEAD

C2904

NEW HAMPSHIRE I/O 9

1

ROOM=FOREHEAD

5% 2 10V C0G-CERM 01005 ROOM=FOREHEAD

45

C2910

SPEAKERAMP2_TO_SPEAKER_OUT_POS

46 45 33

1

C2935 220PF

5% 2 10V C0G-CERM 01005

ROOM=FOREHEAD

150OHM-25%-200MA-0.7DCR

AP_TO_NH_SHUTDOWN_L

1

ROOM=FOREHEAD

2

SPEAKERAMP2_TO_SPEAKER_OUT_NEG

AP_TO_NH_SHUTDOWN_CONN_L

01005

1

ROOM=FOREHEAD

C

NO_XNET_CONNECTION=1

5% 2 25V NP0-C0G-CERM 01005

FL2908

C2932 220PF

56PF

9

C2908

33 45 46

C2911

NO_XNET_CONNECTION=1

C2931

220PF

1

220PF

5% 2 10V C0G-CERM 01005

5% 10V 2 C0G-CERM 01005

ROOM=FOREHEAD

ROOM=FOREHEAD

R2903

CONVOY I/O

1

SPEAKER_TO_SPEAKERAMP2_VSENSE_P

33

PDM_ADARE_TO_CONVOY_CLK

100

PDM_ADARE_TO_CONVOY_CLK_CONN

2

1

100PF

5% 2 35V NP0-C0G 01005

R2904

45

C2905

SPEAKER_TO_SPEAKERAMP2_VSENSE_N

33

1

0.00

SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_N

2

5% 2 25V NP0-C0G-CERM 01005

1

01005

1

ROOM=FOREHEAD

C2934 100PF

ROOM=FOREHEAD

5% 2 35V NP0-C0G 01005

ROOM=FOREHEAD

150OHM-25%-200MA-0.7DCR 1 2 PDM_CONVOY_TO_ADARE_DATA_CONN

45

NO_XNET_CONNECTION=1

0% 1/32W MF 01005

56PF

FL2906

PDM_CONVOY_TO_ADARE_DATA

C2933 ROOM=FOREHEAD

ROOM=FOREHEAD

33

1

#25657495: Update FL2905 to 100ohm 1

45

NO_XNET_CONNECTION=1

ROOM=FOREHEAD

5% 1/32W MF 01005

B

SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_P

2

0% 1/32W MF 01005

R2905 33

0.00

B

ROOM=FOREHEAD 45

C2906 56PF

5% 2 25V NP0-C0G-CERM 01005

MIC3

ROOM=FOREHEAD

32

FL2914

150OHM-25%-200MA-0.7DCR 1

PP_CODEC_TO_FRONTMIC3_BIAS

2 01005

1

ROOM=FOREHEAD

PROX/ALS I/O

2

R2915 PROX_BI_AP_AOP_INT_PWM_L

1

240

2

1% 1/32W MF 01005

PROX_BI_AP_AOP_INT_PWM_L_CONN 1

C2921

31

FRONTMIC3_TO_CODEC_AIN4_N

1

2 ROOM=FOREHEAD

1

2

ROOM=FOREHEAD

FL2909

45

31

FRONTMIC3_TO_CODEC_AIN4_P

2

1 01005

ROOM=FOREHEAD

DZ2906

150OHM-25%-200MA-0.7DCR

01005 1

45

6.8V-100PF 01005

FL2911

ALS_TO_AP_INT_L

FRONTMIC3_TO_CODEC_AIN4_CONN_N

NO_XNET_CONNECTION=1

01005

5% 2 10V C0G-CERM 01005

150OHM-25%-200MA-0.7DCR 2 1 ALS_TO_AP_INT_CONN_L

ROOM=FOREHEAD

FL2904

ROOM=FOREHEAD

12

DZ2905

150OHM-25%-200MA-0.7DCR

45

220PF

ROOM=FOREHEAD

A

45

6.8V-100PF 01005

#25170697: R2915 to 240ohm/C2921 to 220pF

13 12

PP_CODEC_TO_FRONTMIC3_BIAS_CONN

C2924

ROOM=FOREHEAD

FRONTMIC3_TO_CODEC_AIN4_CONN_P NO_XNET_CONNECTION=1

1

DZ2907

45 SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

B2B:FOREHEAD

6.8V-100PF 01005

56PF

5% 2 25V NP0-C0G-CERM 01005 ROOM=FOREHEAD

2

ROOM=FOREHEAD

DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

29 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

29 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

THIS PAGE UNIQUE TO LARGE FORM FACTOR

NEVADA CONNECTOR

NEVADA POWER

THIS ONE --->

NOTE: OUTPUT IMPDEANCE MUST BE >0.005-OHM IN ORDER TO MEET CAP ESR REQUIREMENT PER LDO SPEC. VENDOR ALSO RECOMMENDS CIN = COUT FOR STABILITY

1 OTHER FORM FACTOR SPECIFIC PAGES: 4 - Mechanical 46 - FF Specific

516S00152 RCPT (USED ON MLB) 516S00151 PLUG ROOM=NEVADA

J3001 AA26D-S022VA1 F-ST-SM

U3001 PP_VDD_BOOST

53 38 37 32 25 23 19

A1

PP2V9_NV_AVDD_CONN

30 30

ROOM=NEVADA

PP2V8_UT_AF_VAR

30 25 18

B1 1

1

VEN GND

C3002 2.2UF

C3006

1

4UF

20% 2 6.3V X5R-CERM 0201-1

C3007

1

0.22UF

ROOM=NEVADA

C3009

30

220PF

10% 2 6.3V CER-X5R 01005

20% 2 6.3V CER-X5R 0201

B2

D

LP5907UVX2.925-S DSBGA VIN VOUT A2

45 30 25

5% 2 10V C0G-CERM 01005

ROOM=NEVADA

30 30

ROOM=NEVADA 30 30

I2C_NV_SDA_CONN I2C_NV_SCL_CONN UT_AND_NV_TO_LED_DRIVER_STROBE_EN_CONN AP_TO_NV_SHUTDOWN_CONN_L UT_TO_NV_SYNC_J3001_CONN PP1V8_NV_IO_CONN LPDP_NV_BI_AP_AUX_CONN

ROOM=NEVADA 30 30

PP3V3_NV_SVDD_CONN PP1V8_NV_AF_CONN

L3003

24

23

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

26

25

90_LPDP_NV_TO_AP_D0_CONN_N 90_LPDP_NV_TO_AP_D0_CONN_P

D

30 30

90_LPDP_NV_TO_AP_D1_CONN_N 90_LPDP_NV_TO_AP_D1_CONN_P

30 30

AP_TO_NV_CLK_CONN

30

PP2V9_NV_AVDD_CONN

30

33-OHM-25%-1500MA

PP1V2_NH_NV_DVDD

29 19

1

30

PP1V2_NV_VDD_CONN

2 0201

1

ROOM=NEVADA

C3016 2.2UF

20% 2 6.3V X5R-CERM 0201-1

1

C3019

1

2.2UF

1

2.2UF

20% 2 6.3V X5R-CERM 0201-1

ROOM=NEVADA

C3021

1

220PF

ROOM=NEVADA

C3028 15PF

5% 2 10V C0G-CERM 01005

20% 2 6.3V X5R-CERM 0201-1

ROOM=NEVADA

C3001

PP1V2_NV_VDD_CONN

30

5% 2 16V NP0-C0G-CERM 01005

ROOM=NEVADA

ROOM=NEVADA Desense for Wifi frequencies

GPIO FILTERS NOSTUFF

L3005

FL3002

33-OHM-25%-1500MA 30 25 18

1

PP2V8_UT_AF_VAR

D11: STUFF L3001, L3004. NOSTUFF L3005, L3006 D12: NOSTUFF L3001, L3004. STUFF L3005, L3006

2

C

150OHM-25%-200MA-0.7DCR 45

1

UT_TO_NV_SYNC_J2501_CONN

0201

01005

C3029

1

ROOM=NEVADA

2 1

ROOM=NEVADA

100PF

L3001

25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 29

PP1V8

1

PP1V8_NV_AF_CONN

C

C3027

5% 2 16V NP0-C0G 01005

ROOM=RCAM_B2B

2

30

100PF

5% 2 16V NP0-C0G 01005

33-OHM-25%-1500MA

UT_TO_NV_SYNC_J3001_CONN

ROOM=NEVADA

30

0201 ROOM=NEVADA

1

C3017

45 30 25

UT_AND_NV_TO_LED_DRIVER_STROBE_EN_CONN

220PF

1

5% 2 10V C0G-CERM 01005

100PF

5% 2 16V NP0-C0G 01005

ROOM=NEVADA

L3002

ROOM=NEVADA

33-OHM-25%-1500MA 1

C3011

FL3001

PP1V8_NV_IO_CONN

2

150OHM-25%-200MA-0.7DCR

30

0201 ROOM=NEVADA

1

C3020

1

1.0UF

C3026

9

AP_TO_NV_SHUTDOWN_L

1

AP_TO_NV_SHUTDOWN_L

01005

220PF

ROOM=NEVADA

AP_TO_NV_SHUTDOWN_CONN_L 1

ROOM=NEVADA

5% 2 10V C0G-CERM 01005

20% 2 6.3V X5R 0201-1

2

MAKE_BASE=TRUE

30

C3012 220PF

5% 10V 2 C0G-CERM 01005

ROOM=NEVADA

L3004

ROOM=NEVADA

33-OHM-25%-1500MA 19 7

PP3V3_USB

1

PP3V3_NV_SVDD_CONN

2

R3002

30

0201

46 9

ROOM=NEVADA

B

1

220PF

NOSTUFF

33-OHM-25%-1500MA 2 PP3V0_ALS_APS_CONVOY 1

C3030

1

MAKE_BASE=TRUE

20% 2 6.3V X5R-CERM 0201-1

ROOM=NEVADA

0.00

1

ROOM=NEVADA

I2C_ISP_NV_SDA

1

MAKE_BASE=TRUE

0.00 0% 1/32W MF 01005

LPDP FILTERS 5% 2 16V NP0-C0G-CERM 01005 ROOM=NEVADA

C3004

1

33PF

C3032 33PF

5% 2 16V NP0-C0G-CERM 01005

5% 2 16V NP0-C0G-CERM 01005

ROOM=NEVADA

ROOM=NEVADA

1

C3033 33PF

9

AP_TO_NV_CLK_R

AP_TO_NV_CLK_R MAKE_BASE=TRUE

5% 2 16V NP0-C0G-CERM 01005

1

33.2

56PF

5% 2 25V NP0-C0G-CERM 01005

1% 1/32W MF 01005 ROOM=SOC

ROOM=NEVADA

1

LPDP_NV_BI_AP_AUX

150OHM-25%-200MA-0.7DCR 1 2 AP_TO_NV_CLK_CONN AP_TO_NV_CLK

2

0.1UF

LPDP_NV_BI_AP_AUX

C3014

FL3004

R3003

C3031 10

1

30

ROOM=NEVADA

PP_VDD_MAIN 1

CKPLUS_WAIVE=I2C_PULLUP

I2C_NV_SDA_CONN

2

ROOM=NEVADA

33PF

B

5% 2 25V NP0-C0G-CERM 01005

R3001 46 9

C3003

C3013 ROOM=NEVADA

0201

1

30

56PF

ROOM=NEVADA

ROOM=NEVADA

53 46 41 26 25 23 21 19 18 10 9 4 40 39 37 35 34 33 31 28 27

CKPLUS_WAIVE=I2C_PULLUP

I2C_NV_SCL_CONN

2

0% 1/32W MF 01005

2.2UF

5% 2 10V C0G-CERM 01005

L3006

29 25 19

C3018

1

I2C_ISP_NV_SCL

1

C3005 100PF

5% 2 16V NP0-C0G 01005

ROOM=NEVADA

2

NOSTUFF

LPDP_NV_BI_AP_AUX_CONN

1

C3008

01005 ROOM=NEVADA

100PF

1

30

C3015 56PF

5% 2 25V NP0-C0G-CERM 01005

5% 2 16V NP0-C0G 01005

ROOM=NEVADA

ROOM=NEVADA

NOSTUFF

30

MAKE_BASE=TRUE

ROOM=NEVADA

1

20% 6.3V X5R-CERM 01005

C3010

NEAR SOC

56PF

NEAR B2B

5% 2 25V NP0-C0G-CERM 01005

A

ROOM=NEVADA SYNC_MASTER=sync

90_LPDP_NV_TO_AP_D0_P

10

90_LPDP_NV_TO_AP_D0_P MAKE_BASE=TRUE

90_LPDP_NV_TO_AP_D0_N

10

90_LPDP_NV_TO_AP_D0_N MAKE_BASE=TRUE

C3022

1 ROOM=NEVADA 20% X5R-CERM 1 ROOM=NEVADA 20% X5R-CERM

C3023

2 6.3V 01005 2 6.3V 01005

0.1UF

90_LPDP_NV_TO_AP_D0_CONN_P

30

90_LPDP_NV_TO_AP_D0_CONN_N

30

SYNC_DATE=05/17/2016

PAGE TITLE

B2B:NEVADA

GND_VOID=TRUE

0.1UF

DRAWING NUMBER

Apple Inc.

GND_VOID=TRUE

051-00482 REVISION

8.0.0

R

90_LPDP_NV_TO_AP_D1_P

10

90_LPDP_NV_TO_AP_D1_P MAKE_BASE=TRUE

90_LPDP_NV_TO_AP_D1_N

10

90_LPDP_NV_TO_AP_D1_N MAKE_BASE=TRUE

C3024 ROOM=NEVADA

1 20% X5R-CERM 1 20% ROOM=NEVADA X5R-CERM

C3025

2 6.3V 01005 2 6.3V 01005

0.1UF

90_LPDP_NV_TO_AP_D1_CONN_P

30

GND_VOID=TRUE

0.1UF

90_LPDP_NV_TO_AP_D1_CONN_N

30

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

30 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

GND_VOID=TRUE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

30 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

CALTRA AUDIO CODEC (ANALOG INPUTS & OUTPUTS)

D

D

CRITICAL ROOM=CODEC

U3101 41 41

41 41

44 44

For Borealis

29 29

LOWERMIC1_TO_CODEC_AIN1_P LOWERMIC1_TO_CODEC_AIN1_N

L2 AIN1+ L1 AIN1-

LOWERMIC4_TO_CODEC_AIN2_P LOWERMIC4_TO_CODEC_AIN2_N

K3 AIN2+ L3 AIN2-

REARMIC2_TO_CODEC_AIN3_P REARMIC2_TO_CODEC_AIN3_N

K2 AIN3+ K1 AIN3-

FRONTMIC3_TO_CODEC_AIN4_P FRONTMIC3_TO_CODEC_AIN4_N

J3 AIN4+ J4 AIN4-

C

WLCSP-1

SYM 1 OF 3

CS42L71

AOUT1+ AOUT1-

L9 NC M9 NC

AOUT2+ AOUT2-

L8 NC M8 NC

HPOUTA HPOUTB

K10NC K11NC

HS3

M5

HS4

M4

HS3_REF HS4_REF

HSIN+ HSIN-

L10 M10

D1 NC E1 NC

HPDETECT J9 NC NC

F1 AIN5+ G1 AIN5-

NC NC

F2 AIN6+ F3 AIN6-

WAS FOR RECEIVER; REPLACED BY SPEAKER IN D1xy

C

NC

ROOM=CODEC

C3107 100PF 1

44 44

B

33 33

53 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 30 28

A

HAWKING_TO_CODEC_AIN7_P HAWKING_TO_CODEC_AIN7_N

1

NC NC

A4 DMIC1_CLK B4 DMIC1_DATA

DP DN

J12 H12

MBUS_REF

G10

NC

C4 DMIC2_CLK C3 DMIC2_DATA

NC NC

A3 DMIC3_CLK B3 DMIC3_DATA

NC NC

A2 DMIC4_CLK B2 DMIC4_DATA

PDM_CODEC_TO_SPKAMP2_CLK PDM_CODEC_TO_SPKAMP2_DATA

5% 16V NP0-C0G 01005

R3104 20.0

G2 AIN7+ G3 AIN7-

90_MIKEYBUS_CALTRA_DATA_P 90_MIKEYBUS_CALTRA_DATA_N MIKEYBUS_REFERENCE 1

R3101 100

41

2

2

90_MIKEYBUS_DATA_P

40

90_MIKEYBUS_DATA_N

40

5% 1/32W MF 01005 ROOM=CODEC

R3103 20.0

1

2

5% 1/32W MF 01005 ROOM=CODEC

C3106 100PF 1

5% 1/32W MF 01005 2ROOM=CODEC

2

5% 16V NP0-C0G 01005

A9 PDM_CLK B9 PDM_DATA

B

ROOM=CODEC

PP_VDD_MAIN 1

C3112 220PF

5% 2 10V C0G-CERM 01005 ROOM=CODEC

1

C3113

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

220PF

AUDIO:CALTRA CODEC (1/2)

5% 2 10V C0G-CERM 01005

DRAWING NUMBER

ROOM=CODEC

Apple Inc.

AC return path for Mikeybus which is referenced to GND and VDD_MAIN

051-00482 REVISION

8.0.0

R

Radar 21203307

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

31 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

31 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

CALTRA AUDIO CODEC (POWER & I/O) 35 34 33 19

PP1V8_VA 1

C3209 2.2UF

D

20% 2 6.3V X5R-CERM 0201-1 ROOM=CODEC

D

CODEC_AGND

53 38 37 30 25 23 19

32

PP_VDD_BOOST 1

C3212

1

0.1UF

C3214

1

0.1UF

2.2UF

20% 2 6.3V X5R-CERM 01005

20% 2 6.3V X5R-CERM 01005 ROOM=CODEC

C3205

20% 2 6.3V X5R-CERM 0201-1

ROOM=CODEC

46 41 40 37 36 32 21 20 18 16 53 52 48 47

ROOM=CODEC

PP1V8_SDRAM 1

PP1V8_SDRAM 0.1UF

5% 1/32W MF 2 01005 ROOM=CODEC

C3215 0.1UF

20% 2 6.3V X5R-CERM 01005

20% 2 6.3V X5R-CERM 01005

R3202

PP1V2_VD_FILT 1.0UF

20% 2 6.3V X5R 0201-1

20% 2 6.3V X5R 0201-1

ROOM=CODEC

ROOM=CODEC

C C3203 41

1

LOWERMIC1_TO_CODEC_BIAS_FILT_RET

PP_CODEC_TO_LOWERMIC1_BIAS LOWERMIC1_BIAS_FILT_IN

41

2

M6 MIC1_BIAS K7 MIC1_BIAS_FILT

1

U3101 NC K8

ROOM=CODEC 35 34 33 13

11

36 11

36 11

K12NC

36 11

11

CS42L71 CRITICAL

PP_CODEC_TO_LOWERMIC4_BIAS LOWERMIC4_BIAS_FILT_IN

41

36 35 34 33 11 36 35 34 33 11

L6 MIC2_BIAS J7 MIC2_BIAS_FILT

FLYC

36 35 34 33

L12NC

36 35 34 33

20% 6.3V X5R-CERM1 402

13

ROOM=CODEC

13

C3201 45

1

REARMIC2_TO_CODEC_BIAS_FILT_RET

44

2

PP_CODEC_TO_REARMIC2_BIAS REARMIC2_BIAS_FILT_IN

13

K6 MIC3_BIAS L5 MIC3_BIAS_FILT

13

20% 6.3V X5R-CERM1 402

FLYN

1

29

PP_CODEC_TO_FRONTMIC3_BIAS FRONTMIC3_BIAS_FILT_IN 1

C3223

1

1.0UF

ROOM=CODEC

XW3203 SHORT-20L-0.05MM-SM

+VCP_FILT

J6 MIC4_BIAS K5 MIC4_BIAS_FILT

20% 6.3V X5R-CERM1 402

2

B

2

CS42L71

INT*

ROOM=CODEC

SPI_AP_TO_CODEC_MAGGIE_SCLK

C9 C8

CS* CCLK

SPI_AP_TO_CODEC_MAGGIE_MOSI SPI_CODEC_MAGGIE_TO_AP_MISO

B8 A8

MOSI MISO

C12

MCLK

CRITICAL

I2S_AP_TO_CODEC_MCLK

B11 C11 A11 A10

XSP_SCLK XSP_LRCK/FSYNC XSP_SDIN/DAC2B_MUTE XSP_SDOUT

11

20

PMU_TO_CODEC_DIGLDO_PULLDN

H5 J5

DIGLDO_PULLDN DIGLDO_PDN

C3224

20% 2 6.3V X5R 0201-1

ROOM=CODEC

1NO_XNET_CONNECTION

I2S_CODEC_XSP_TO_AOP_BCLK I2S_CODEC_XSP_TO_AOP_LRCLK I2S_AOP_TO_CODEC_XSP_DOUT I2S_CODEC_XSP_TO_AOP_DIN

ASP_SCLK ASP_LRCK/FSYNC ASP_SDIN ASP_SDOUT

1.0UF

20% 2 6.3V X5R 0201-1

ROOM=FOREHEAD

C6 C5 B5 B6

MSP_SCLK MSP_LRCK/FSYNC MSP_SDIN MSP_SDOUT

11

J10NC

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK I2S_MAGGIE_TO_L26_CODEC_DOUT I2S_L26_CODEC_TO_MAGGIE_DIN

B7 C7 D8 A7

11

C3202 FRONTMIC3_TO_CODEC_BIAS_FILT_RET

WLCSP-1 SYM 3 OF 3

I2S_AP_TO_CODEC_MSP_BCLK I2S_AP_TO_CODEC_MSP_LRCLK I2S_AP_TO_CODEC_MSP_DOUT I2S_CODEC_TO_AP_MSP_DIN

11

M12NC

ROOM=CODEC

4.7UF

K9

WAKE*

JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO

ROOM=CODEC

2

4.7UF

AUDIO_TO_AOP_INT_L

SPI_AP_TO_CODEC_CS_L

SYM 2 OF 3

C3204 LOWERMIC4_TO_CODEC_BIAS_FILT_RET

RESET*

WLCSP-1

ROOM=CODEC

41

FLYP

U3101

20% 6.3V X5R-CERM1 402

4.7UF

VP_MBUS H10

1.0UF

H3

5% 1/32W MF 01005 2

C3221 VA J1

C3217

1

VPROG_CP H11

1

CODEC_RESET_L

1

100K

VP M7

ROOM=CODEC

ROOM=CODEC

VL A5

ROOM=CODEC

C3213

1

VD_FILT C1 VD_FILT E12

20% 2 6.3V CERM-X5R 0402-9

1

VD D12 VD G12

C3211 10UF

4.7UF

R3201 1.00K

1

VCP J11

46 41 40 37 36 32 21 20 18 16 53 52 48 47

GNDCP

ROOM=CODEC

L11

OMIT 1

C3222 1.0UF

20% 2 6.3V X5R 0201-1

ROOM=CODEC

1

C3225 1.0UF

20% 2 6.3V X5R 0201-1

ROOM=CODEC

-VCP_FILT LP_FILT+

M11NC F12

CALTRA_LP_FILTP 1

C3220 0.1UF

20% 2 6.3V X5R-CERM 01005

NC NC

M3 HS_BIAS_FILT M2 HS_BIAS_FILT_REF

D3 D4 D2 C2

TSTO TSTO TSTO TSTO TSTO TSTO TSTO TSTO

D11 B10 D5 D6 E5 E6 E7 K4

TSTI TSTI TSTI TSTI TSTI TSTI TSTI TSTI TSTI

C10 D10 D7 D9 E8 E9 G11 H4 M1

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

A1 A12 B12 E2 E3 E4 E10 F4 F5 F6 F7 F8 F9 F10 G4 G5 G6 G7 G8 G9 H6 H7 H8 H9

NC NC NC NC NC NC NC NC NC NC NC NC

C

B

GND J8

ROOM=CODEC

FILT+

H1

CALTRA_FILTP 1

C3208 10UF

GNDD GNDD GNDD GNDD

GNDHS

GNDP

GNDA

L4

L7

J2

A

A6 B1 E11 F11

20% 2 6.3V CERM-X5R 0402-9 ROOM=CODEC

FILT-

H2

SYNC_MASTER=Sync

CODEC_AGND

SYNC_DATE=06/06/2016

PAGE TITLE 32

AUDIO:CALTRA CODEC (2/2) DRAWING NUMBER

Apple Inc.

XW3202 SHORT-10L-0.1MM-SM 2

051-00482 REVISION

8.0.0

R

1

ROOM=CODEC

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

32 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

32 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D

SPEAKER AMPLIFIER 2

PP1V8_VA

PP_VDD_MAIN

C3326

1

10UF

1

10UF

20% 10V X5R-CERM 2 0402-8 ROOM=SPKAMP2

20% 6.3V 2 CERM-X5R 0402-9 ROOM=SPKAMP2

C3328

1

10UF

20% 6.3V 2 CERM-X5R 0402-9 ROOM=SPKAMP2

C3313

C3329

1

10UF

1

1

2.2UF

20% 6.3V 2 CERM-X5R 0402-9

0.1UF

20% 6.3V 2 X5R-CERM 01005

20% 6.3V 2 X5R-CERM 0201-1

ROOM=SPKAMP2

ROOM=SPKAMP2

L3302

VP

1.2UH-20%-3.0A-0.080OHM 1 2 SPEAKERAMP2_LX PIQA20161T-SM

A2 B2

I2C2_AP_SDA

D6

VBST_B A1 VBST_B B1

CS35L26-A1 WLCSP

SDA

35 34 32 13

12

I2C2_AP_SCL

E6

SCL

AUDIO_TO_AOP_INT_L

A7

INT*

A6

RESET*

SPKAMP1_TO_SPKAMP2_SYNC

F6

ALIVE/SYNC

PDM_ADARE_TO_CONVOY_CLK

E5

AD0/PDM_CLK1

I2S_AOP_TO_MAGGIE_L26_MCLK

B7

MCLK

AP_TO_SPKAMP2_RESET_L 1

20% 2 6.3V X5R-CERM 0201-1 ROOM=SPKAMP2

PP_SPKR2_VBOOST 1

CRITICAL

C3312 220PF

VBST_A C1 VBST_A D1

ROOM=SPKAMP2 47

2.2UF

C

U3301

SW SW

C3316

VA

ROOM=SPKAMP2 47

1

ROOM=SPKAMP2

CRITICAL

C

C3315

19 32 34 35

F5

C3327

A5

53 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 31 30 28

(North)

5% 2 10V C0G-CERM 01005 ROOM=SPKAMP2

1

C3311

1

0.1UF

C3324

1

10UF

10% 2 16V X5R-CERM 0201

10UF

20% 2 10V X5R-CERM 0402-8

20% 2 10V X5R-CERM 0402-8

ROOM=SPKAMP2

C3325

ROOM=SPKAMP2

R3301 100K

5% 1/32W MF 2 01005

29

PDM_ADARE_TO_CONVOY_CLK

ISNS+ F1 ISNS- E1

SPEAKERAMP2_ISENSE_P SPEAKERAMP2_ISENSE_N

1

R3304 100K

5% 1/32W MF 2 01005 ROOM=SPKAMP2

36 35 34 13

36 35 34 32 11

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK

C7

SCLK

I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK

C6

LRCK/FSYNC

36 35 34 32

I2S_MAGGIE_TO_L26_CODEC_DOUT

D7

SDIN

36 35 34 32

I2S_L26_CODEC_TO_MAGGIE_DIN

B6

SDOUT

PDM_CODEC_TO_SPKAMP2_CLK

F7

PDM_CLK0

36 35 34 32 11

31

VSNS+ E2 VSNS- E3

PDM_DATA0

29

PDM_CONVOY_TO_ADARE_DATA

D5

PDM_DATA1

GNDP

B

GNDA

20% 2 10V X5R-CERM 0402-8 ROOM=SPKAMP2

29 29

SPEAKERAMP2_TO_SPEAKER_OUT_POS SPEAKERAMP2_TO_SPEAKER_OUT_NEG

C3331 FILT+ F4

10UF

ROOM=SPKAMP2 NO_XNET_CONNECTION

SPEAKER_TO_SPEAKERAMP2_VSENSE_P SPEAKER_TO_SPEAKERAMP2_VSENSE_N

1

1

AD1 F3 1

C3318

29 45 46 29 45 46

C3323 1000PF

10% 10V 2 X5R 01005

SPEAKERAMP2_FILT

10% 2 10V X5R 01005

ROOM=SPKAMP2

Pg46: Compass Compensation Coil

ROOM=SPKAMP2

1UF

B5 E4 F2

E7

C3308

C3319

OUT+ D2 OUT- C2

A3 A4 B3 B4 C3 C4 C5 D3 D4

PDM_CODEC_TO_SPKAMP2_DATA

ROOM=SPKAMP2

1

10% 6.3V 2 X5R 01005

1000PF

31

10UF

0.01UF

MAKE_BASE=TRUE

ROOM=SPKAMP2

C3306

20% 2 10V X5R-CERM 0402-8

ROOM=SPKAMP2

1 34

1

B

10% 2 10V X5R 402-1 ROOM=SPKAMP2

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

AUDIO:SPEAKER AMP 2 DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

33 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

33 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

SPEAKER AMPLIFIER 1

2

1

(South) D

D

#25112685,Remove C3414

PP1V8_VA

PP_VDD_MAIN

C3407

1

10UF

20% 10V X5R-CERM 2 0402-8

C3424

1

10UF

1

1

20% 6.3V CERM-X5R 2 0402-9

20% 6.3V CERM-X5R 2 0402-9 ROOM=SPKAMP1

ROOM=SPKAMP1

ROOM=SPKAMP1

48

48

35 33 32 13

PULLED LOW ON PG 35 35 13

A2 B2

SPEAKERAMP1_LX

D6

I2C_AOP_SDA

E6

I2C_AOP_SCL

A7

AUDIO_TO_AOP_INT_L

A6

AOP_TO_SPKAMP1_ARC_RESET_L 33

F6

SPKAMP1_TO_SPKAMP2_SYNC

E5

GND

MAKE_BASE=TRUE

36 35 33 13

36 35 33 32 11

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK

36 35 33 32 11

I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK

36 35 33 32

36 35 33 32

B7

I2S_AOP_TO_MAGGIE_L26_MCLK

C7 C6 D7

I2S_MAGGIE_TO_L26_CODEC_DOUT

B6

I2S_L26_CODEC_TO_MAGGIE_DIN

F7 NC

E7 NC

D5

A1 VBST_B B1 VBST_B C1 VBST_A D1 VBST_A

WLCSP

SDA

ROOM=SPKAMP1

CRITICAL

PP_SPKR1_VBOOST 1

C3427 220PF

5% 2 10V C0G-CERM 01005 ROOM=SPKAMP1

INT*

1

C3428 0.1UF

10% 2 16V X5R-CERM 0201 ROOM=SPKAMP1

1

C3403 10UF

20% 2 10V X5R-CERM 0402-8 ROOM=SPKAMP1

1

C3404 10UF

20% 2 10V X5R-CERM 0402-8

F1 ISNS+ E1 ISNS-

ALIVE/SYNC AD0/PDM_CLK1 MCLK

E2 VSNS+ E3 VSNS-

SCLK

1

SPEAKERAMP1_ISENSE_P SPEAKERAMP1_ISENSE_N

1

C3431 10UF

20% 2 10V X5R-CERM 0402-8

ROOM=SPKAMP1

RESET*

ROOM=SPKAMP1

1

C3432 10UF

20% 2 10V X5R-CERM 0402-8 ROOM=SPKAMP1

C3430 0.01UF

10% 2 6.3V X5R 01005

ROOM=SPKAMP1 NO_XNET_CONNECTION

SPEAKER_TO_SPEAKERAMP1_VSENSE_P SPEAKER_TO_SPEAKERAMP1_VSENSE_N

41 41

LRCK/FSYNC D2 OUT+ C2 OUT-

SDIN SDOUT

SPEAKERAMP1_TO_SPEAKER_OUT_POS SPEAKERAMP1_TO_SPEAKER_OUT_NEG

PDM_CLK0 PDM_DATA0 PDM_DATA1

FILT+ GNDP

A3 A4 B3 B4 C3 C4 C5 D3 D4

B

ROOM=SPKAMP1

C

CS35L26-A1

SCL

2.2UF

VA

U3402

SW SW

C3426

F5

VP

28

1

19 32 33 35

20% 2 6.3V X5R-CERM 0201-1

20% 2 6.3V X5R-CERM 01005

C TO TRINITY

C3425 0.1UF

10UF

A5

ROOM=SPKAMP1

C3405

GNDA

AD1

F4

C3422

SPEAKERAMP1_FILT

1000PF

F3 1

1

10% 10V 2 X5R 01005

C3429 2.2UF

B5 E4 F2

53 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 33 31 30 28

ROOM=SPKAMP1

1

41 41

C3434 1000PF

10% 2 10V X5R 01005

B

ROOM=SPKAMP1

20% 2 6.3V X5R-CERM 0201-1 ROOM=SPKAMP1

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

AUDIO:SPEAKER AMP 1 DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

34 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

34 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

ARC DRIVER D

D

#25742582,Add back C3531 for D10x at Pg46 0201 C3525 is at Pg46 53 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 34 33 31 30 28

PP1V8_VA

PP_VDD_MAIN

C3530

1

10UF

C3532

1

1

10UF

20% 10V X5R-CERM 2 0402-8

20% 6.3V CERM-X5R 2 0402-9

ROOM=ARC1

ROOM=ARC1

C3527

1

0.1UF

19 32 33 34 35

C3534 2.2UF

20% 2 6.3V X5R-CERM 01005 ROOM=ARC1

20% 6.3V 2 X5R-CERM 0201-1 ROOM=ARC1

C

28

48

48

34 33 32 13

34 13

A2 B2

ARC1_LX

D6

I2C_AOP_SDA

E6

I2C_AOP_SCL

A7

AUDIO_TO_AOP_INT_L

A6

AOP_TO_SPKAMP1_ARC_RESET_L 1

NC FROM HOMER PER #25452686

R3508 100K

35 34 33 32 19

5% 1/32W MF 2 01005 ROOM=ARC1

PP1V8_VA

MAKE_BASE=TRUE

36 34 33 13 36 34 33 32 11

NOSTUFF

C3501

1

36 34 33 32 11

5% 16V 2 CERM 01005

36 34 33 32

10PF

36 34 33 32

F6 NC

E5

PP1V8_VA

B7

I2S_AOP_TO_MAGGIE_L26_MCLK

C7

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK

C6

I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK

D7

I2S_MAGGIE_TO_L26_CODEC_DOUT

B6

I2S_L26_CODEC_TO_MAGGIE_DIN

F7

ROOM=ARC1

NC

E7

B

NC

F5 VA

U3502

SW SW

VBST_B VBST_B

CS35L26-A1 WLCSP

SDA

VBST_A VBST_A

ROOM=SPKAMP2

CRITICAL

SCL

A1 B1

1

C1 D1

VOLTAGE=8.0V

PP_ARC1_VBOOST

C3526 220PF

5% 2 10V C0G-CERM 01005

1

C3535

1

0.1UF

C3537

1

10UF

10% 2 16V X5R-CERM 0201

ROOM=ARC1

INT*

ISNS+ ISNS-

ALIVE/SYNC AD0/PDM_CLK1 MCLK

VSNS+ VSNS-

SCLK

F1 E1

E2 E3

10UF

20% 2 10V X5R-CERM 0402-8

ROOM=ARC1

C3538

1

10UF

20% 2 10V X5R-CERM 0402-8

ROOM=ARC1

C3524

20% 2 10V X5R-CERM 0402-8

ROOM=ARC1

RESET* 1

ARC1_ISENSE_P ARC1_ISENSE_N

ROOM=ARC1

1

C3539 10UF

20% 2 10V X5R-CERM 0402-8 ROOM=ARC1

C3528 0.01UF

10% 2 6.3V X5R 01005

ROOM=ARC1 NO_XNET_CONNECTION

SOLENOID1_TO_ARC1_VSENSE_POS SOLENOID1_TO_ARC1_VSENSE_NEG

41 41

LRCK/FSYNC SDIN

OUT+ OUT-

SDOUT

D2 C2

VOLTAGE=8.0V

ARC1_TO_SOLENOID1_OUT_POS ARC1_TO_SOLENOID1_OUT_NEG

VOLTAGE=8.0V

41 41

PDM_CLK0 PDM_DATA0 PDM_DATA1

FILT+ GNDP

A3 A4 B3 B4 C3 C4 C5 D3 D4

D5

VP

GNDA

AD1

F4

C3529

ARC1_FILT

1

1000PF

F3 1

10% 10V 2 X5R 01005

C3536 2.2UF

B5 E4 F2

TO TRINITY

A5

C

20% 2 6.3V X5R-CERM 0201-1

ROOM=ARC1

1

C3542

B

1000PF

10% 2 10V X5R 01005

ROOM=ARC1

ROOM=ARC1

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

ARC:DRIVER DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

35 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

35 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D

MAGGIE LDO

MAGGIE APN: 336S00020

APN: 353S00842

U3603

LD39130S-1.2V/AP 46 41 40 37 36 32 21 20 18 16 53 52 48 47

PP1V8_SDRAM

A1

IN

B1

EN

PP1V2_MAGGIE

OUT A2

CSP

1

C3605

1

4UF

GND

0.1UF

20% 2 6.3V X5R-CERM 01005

20% 2 6.3V CER-X5R 0201

B2

C3601

ROOM=ARC_CTRL

ROOM=ARC_CTRL

R3601 1

100

2

PP1V2_MAGGIE_PLL

5% 1/32W MF 01005

1

C3602 0.1UF

20% 2 6.3V X5R-CERM 01005

ROOM=ARC_CTRL

ROOM=ARC_CTRL

C

C VPP_2V5 must be > 1.71V for SPI Slave programming

PP1V8_MAGGIE_IMU C3 SPI_VCCIO1

D4

A5 VCC

ROOM=ARC_CTRL

B3

20% 2 6.3V X5R-CERM 01005

VPP_2V5

ROOM=ARC_CTRL

0.1UF

VCCPLL

20% 2 6.3V X5R-CERM 0201-1

C3606 C4

2.2UF

1

VCCIO_2

C3604

A4

1

VCCIO_0

36 24 18

ICE5LP4K-SWG36I

MAGGIE_TO_HOMER_WAKE SPI_MAGGIE_TO_HOMER_POS_SCLK

46 41 40 37 36 32 21 20 18 16 53 52 48 47

PP1V8_SDRAM

C3603

1

2.2UF

13

20% 6.3V 2 X5R-CERM 0201-1 ROOM=HOMER

B

13

SPI_HOMER_TO_MAGGIE_POS_MISO AOP_TO_MAGGIE_EN MAGGIE_TO_AOP_INT

F6 E6 D6 NC D5 F5 E5

RGB0 RGB1 RGB2 IOT_46B_G0

IOB_2A IOB_3B_G6 IOB_4A IOB_5B IOB_6A IOB_7B

BANK 1

36

C6 NC B6 NC A6 NC B5

IOB_10A IOB_11B_G5 WLCSP IOB_12A_G4_CDONE IOB_16A IOB_20A IOB_25B_G3 IOB_26A IOB_27B IOB_29B IOB_30A IOB_31B IOB_32A_SPI_SO IOB_33B_SPI_SI IOB_34A_SPI_SCK IOB_35B_SPI_CSN

BANK 0

HOMER STM32L0 MICRO STM32L03 APN: 337S00231

U3602

IRLED

BANK 2

NC

A2

R3604

B4 NC F4 E4 F3 E3 C2 B1 D2 E2 C1 B2 F2 D1 E1 F1

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK_R MAGGIE_TO_AP_CDONE UART_AOP_TO_MAGGIE_TXD I2S_MAGGIE_TO_AP_DIN I2S_AOP_TO_MAGGIE_L26_MCLK I2S_MAGGIE_TO_L26_CODEC_DOUT I2S_L26_CODEC_TO_MAGGIE_DIN I2S_AP_TO_MAGGIE_DOUT

SM PP

1

ROOM=HOMER

VDDA

U3601

CRITICAL GND GND

GND_LED

VDD

13 11

2

MAGGIE DRIVES TO ARC, SPKRS, AP, CODEC

I2S_MAGGIE_TO_AP_L26_CODEC_BCLK

I2S_MAGGIE_TO_AP_L26_CODEC_LRCLK SPI_CODEC_MAGGIE_TO_AP_MISO SPI_AP_TO_CODEC_MAGGIE_MOSI SPI_AP_TO_CODEC_MAGGIE_SCLK SPI_AP_TO_MAGGIE_CS_L

11 32 33 34 35

1% 1/32W MF 01005 ROOM=ARC_CTRL

MAGGIE <-> AP (SDIN)

13 33 34 35 32 33 34 35

MAGGIE <-> ARC, SPKRS, CODEC (SDOUT)

32 33 34 35

MAGGIE <-> ARC, SPKRS, CODEC (SDIN)

11

MAGGIE <-> AP (SDOUT)

PP1V8_MAGGIE_IMU 1

R3605

11 32 33 34 35 11 32

5% 1/32W MF 2 01005

MAGGIE DRIVES TO ARC, SPKRS, AP, CODEC

1

18 24 36

R3602 10K

5% 1/32W MF 2 01005

11 32 11 32

B

9

AP_TO_MAGGIE_CRESETB_L

12

ROOM=ARC_CTRL

C5 A3

PP3602 P2MM-NSM

A1

ROOM=HOMER

C4

1

D1

SM PP

12

33.2

10K

CRESET_B D3

PP3601 P2MM-NSM

1

1

R3603 511K

1% 1/32W MF 2 01005

STM32L031E6Y6D

12 12

E5 PA0_CLK_INROOM=HOMER PB0 NC B4 PA1 PB1 NC WLCSP D4 PA2 PB3 E4 PA3 PB6 B3 PA4 PB7 D3 PA5 NC PC14_OSC32_IN E3 PA6 PC15_OSC32_OUT C3 PA7 NC C1 PA8 RST* B1 PA9 BOOT0 C2 PA10 A1 PA13 A2 PA14

UART_HOMER_TO_AP_RXD UART_AP_TO_HOMER_TXD 36 MAGGIE_TO_HOMER_WAKE

R3607 1

100

AP_BI_HOMER_BOOTLOADER_ALIVE_R

2

5% 1/32W MF 01005

13

ROOM=HOMER

47 41 47 41 13 53 17 13

HOMER_TO_AOP_WAKE_INT I2C_HOMER_SCL I2C_HOMER_SDA SWD_AP_BI_HOMER_SWDIO SWD_AP_TO_MANY_SWCLK

E1

VSSA

A

E2 D2 B2 A3 A4

SPI_MAGGIE_TO_HOMER_POS_MOSI

NC

B5 NC C5 NC NOTE: RESET HAS INTERNAL 65K PULLUP D5 PMU_TO_HOMER_RESET_L A5

AP_BI_HOMER_BOOTLOADER_ALIVE 1

R3611 27K

5% 1/32W MF 2 01005

20

12

1

C3607 0.1UF

20% 2 6.3V X5R-CERM 01005 ROOM=HOMER

ROOM=HOMER

#24543115: Scrub Value SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

ARC:MAGGIE DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

36 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

36 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

DISPLAY & TOUCH - POWER SUPPLIES CHESTNUT DISPLAY PMU

PP_CHESTNUT_CP 1

APN:338S1172

20% VOLTAGE=10V 2 X5R-CERM 0402-8

C3722 See Page46

PP_VDD_MAIN

C3710

1

CRITICAL

20% 6.3V 2 CERM-X5R 0402-9

L3704

1.0UH-20%-2.25A-0.15OHM PIXB2016FE-SM

ROOM=CHESTNUT

D1 2

B2

CHESTNUT_LX

47 20

I2C0_AP_SCL

47

I2C0_AP_SDA

6.3V

A2 D3 D2 C3

LCM_TO_CHESTNUT_PWR_EN

39 20

C2

PMU_TO_AOP_TRISTAR_ACTIVE_READY

40 20 13 7

E1

CHESTNUT_TO_PMU_ADCMUX

VIN

NOSTUFF C3726

1

56PF

C4 CF1 E4 CF2

BGA ROOM=CHESTNUT

NOSTUFF C3727

D #24543286: Densense Cap for Chestnut Charge Pump

56PF

5% 2 25V NP0-C0G-CERM 01005

5% 2 25V NP0-C0G-CERM 01005

ROOM=CHESTNUT

ROOM=CHESTNUT

CRITICAL

SW

B3 LCMBST B4 CPUMP

SYNC NO INT PULL

SCL SDA

VNEG

LCM_EN

VNEG(SUB)

200K INT PD

RESET*

HVLDO1

NO INT PULL

ADCMUX

C1

20

1

U3703 TPS65730A0PYFF

ROOM=CHESTNUT

HVLDO2 HVLDO3

PP6V0_LCM_BOOST

E3

PN5V7_LCM_MESON_AVDDN

39

PP5V7_MESON_AVDDH

39

PP5V7_LCM_AVDDH

39

PP5V1_TOUCH_VDDH

39

E2 A4 A3 A1 1

C3711

1

1UF

C3712

1

10UF

20% 2 16V CER-X5R 0201

C3713

1

10UF

20% 2 10V X5R-CERM 0402-8

ROOM=CHESTNUT

10UF

20% 2 10V X5R-CERM 0402-8

ROOM=CHESTNUT

C3714

20% 2 10V X5R-CERM 0402-8

ROOM=CHESTNUT

ROOM=CHESTNUT

1

C3715 4.7UF

20% 2 10V X5R-CERM 0402 ROOM=CHESTNUT

1

C3716 4.7UF

20% 2 10V X5R-CERM 0402

1

C3717 220PF

5% 2 10V C0G-CERM 01005

ROOM=CHESTNUT

ROOM=CHESTNUT

#26634069:D1x, C3715/C3716 to 138S0719 0402 4.7uF

LED BACKLIGHT DRIVER - 6LED

C

PN_CHESTNUT_CN

10UF

B1 PGND1 D4 PGND2

D

ROOM=CHESTNUT

1

AGND

53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

C3707 10UF

CRITICAL

C

D3701 DSN2

APN:353s00640 28

BL_SW2_LX

A

K

25V

NSR05F30NXT5G ROOM=BACKLIGHT

TO TRINITY

CRITICAL

D3702

NSR0530P2T5G 53 46 41 27 26 25 23 21 19 18 10 9 4 40 39 37 35 34 33 31 30 28

PP_VDD_MAIN

28

A

BL_SW1_LX

39

C3702 1

SOD-923-1 ROOM=BACKLIGHT

10UF

20% VOLTAGE=6.3V 2 CERM-X5R 0402-9

U3701

D4 IN

46 11 46 11

47 47

46 9

53 46 26

C3703

1

220PF

2.2UF

20% 2 35V X5R 0402

D3 VIO/HWEN

DWI_PMGR_TO_BACKLIGHT_DATA DWI_PMGR_TO_BACKLIGHT_CLK

C2 SDI C3 SCK

SW2_1 A3 SW2_2 A4

I2C0_AP_SDA I2C0_AP_SCL

B2 SDA A2 SCL

LED1 C1 LED2 B1

AP_TO_MUON_BL_STROBE_EN

D1 TRIG

BB_TO_STROBE_DRIVER_GSM_BURST_IND

D2 INHIBIT

1

C3704 2.2UF

20% 2 35V X5R 0402

1

C3706 2.2UF

20% 35V 2 X5R 0402

1

C3705 2.2UF

20% 2 35V X5R 0402

1

C3721 2.2UF

20% 2 35V X5R 0402

ROOM=BACKLIGHT PLACE_NEAR=U3701:2MM

OUT A1

PP1V8_SDRAM

C3725

SW1 C4

PP_LCM_BL_CAT1 39 PP_LCM_BL_CAT2 39

ROOM=BACKLIGHT

B

B3 B4

B

GND GND

47 46 41 40 36 32 21 20 18 16 53 52 48

DSBGA

CRITICAL

1

2% 2 50V C0G 0201

LM3539A1

ROOM=BACKLIGHT

PP_LCM_BL_ANODE

K

25V

1

2

R3701 200K 1% 1/32W MF 01005

ROOM=BACKLIGHT

MOJAVE MESA BOOST APN:353S00671

L3703

PP_VDD_MAIN

0403 ROOM=MOJAVE

CRITICAL

10UF

U3702

20% 6.3V CERM-X5R 2 0402-9

BGA

B1 SW

ROOM=MOJAVE

PP_VDD_BOOST

C3724

A

A2 VIN 1

38 4

MESA_TO_BOOST_EN

10UF

20% 6.3V 2 CERM-X5R 0402-9

PP17V0_MOJAVE_LDOIN

5% 2 35V NP0-C0G 01005

B2 EN_M A3 EN_S C2 LDOIN

C3708 100PF

VOUT C3

1

C3720 2.2UF

20% 2 35V X5R 0402

ROOM=MOJAVE

A1

ROOM=MOJAVE

1

CRITICAL

AGND

53 38 32 30 25 23 19

PP16V0_MESA

LM3638A0 ROOM=MOJAVE

ROOM=MOJAVE SYNC_MASTER=Sync

PMID C1

SYNC_DATE=06/17/2016

PAGE TITLE

1

C3709 100PF

B3

C3718

1

PGND

53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

1.0UH-20%-0.4A-0.636OHM 1 2 POS18V0_MESA_LX

5% 2 35V NP0-C0G 01005

ROOM=MOJAVE

1

DISPLAY & MESA:POWER

C3719 2.2UF

DRAWING NUMBER

20% 2 35V X5R 0402

Apple Inc.

ROOM=MOJAVE

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

37 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

37 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

MESA POWER 1

PP3V0_MESA

2

PP3V0_MESA_CONN

J3801 BB35C-RA24-3A F-ST-SM

1

C3813

C3815

1

2.2UF

2.2UF

20% 2 6.3V X5R-CERM 0201-1

2.2UF

20% 2 6.3V X5R-CERM 0201-1

ROOM=MAMBA_MESA

C3821

1

C3822

1

0.1UF

20% 2 6.3V X5R-CERM 0201-1

ROOM=MAMBA_MESA

1

ROOM=MAMBA_MESA

C3804 220PF

20% 2 6.3V X5R-CERM 01005

5% 2 10V C0G-CERM 01005

ROOM=MAMBA_MESA

38

PP3V0_MESA_CONN

38

PP16V0_MESA_CONN

38

MAMBA_TO_LCM_MDRIVE_CONN_MESA

ROOM=MAMBA_MESA

GUARD

D

FL3801

150OHM-25%-200MA-0.7DCR 1

PP1V8_MESA 1

45

2

PP1V8_MESA_CONN

LCM_TO_MAMBA_MSYNC_CONN 1

ROOM=MAMBA_MESA

1

2.2UF

C3802

PP3801

5% 25V 2 NP0-C0G-CERM 01005

5% 2 10V C0G-CERM 01005

ROOM=MAMBA_MESA

C3807 56PF

220PF

20% 2 6.3V X5R-CERM 0201-1

P2MM-NSM SM PP 1

38

01005

C3814

45 39

AP_TO_TOUCH_MAMBA_RESET_CONN_L

47

TP_MAMBA_HINT_L I2C_TOUCH_BI_MAMBA_SDA I2C_TOUCH_TO_MAMBA_SCL

38

PP1V8_TOUCH_TO_MAMBA_CONN

47

26

25

2 4 6 8 10 12 14 16 18 20 22 24

1 3 5 7 9 11 13 15 17 19 21 23

28

27

FL3802

2

PP16V0_MESA_CONN

53 37 32 30 25 23 19

1

C3803

MAMBA POWER

5% 2 35V NP0-C0G 01005

C3828

ROOM=MAMBA_MESA

20% 6.3V 2 X5R-CERM 0201-1

47 46 39 38 18

PP1V8_TOUCH

1

150OHM-25%-200MA-0.7DCR

C

R3807

4 VIN

XW3801 SHORT-20L-0.05MM-SM

FL3807

1

1

1

0.00 1

2

ROOM=MAMBA_MESA

38

38

C3812

C

ROOM=MAMBA_MESA

R3805 47 46 39 38 18

PP1V8_TOUCH

1

SPI_AP_TO_MESA_SCLK_CONN

2 1

1

ROOM=MAMBA_MESA

C3811 220PF

5% 2 10V C0G-CERM 01005 ROOM=MAMBA_MESA

150OHM-25%-200MA-0.7DCR 45

1

MAMBA_TO_LCM_MDRIVE 1

2

NOSTUFF

01005 1

ROOM=MAMBA_MESA

56PF

2

SPI_MESA_TO_AP_MISO_CONN

38

MAMBA_TO_LCM_MDRIVE_CONN_MESA

38

C3806 56PF

5% 25V NP0-C0G-CERM 2 01005

R3811 1

20% 2 6.3V X5R-CERM 0201-1

1

38

FL3804

5% 2 25V NP0-C0G-CERM 01005

1% 1/32W MF 01005

C3824 2.2UF

MAMBA DIGITAL I/O

C3817 ROOM=MAMBA_MESA

1

PP1V8_TOUCH_TO_MAMBA_CONN

2

38

56PF

ROOM=MAMBA_MESA

33.2

0.00

ROOM=MAMBA_MESA

C3805 SPI_MESA_TO_AP_MISO

38

5% 2 10V C0G-CERM 01005

0% 1/32W MF 01005

0% 1/32W MF 01005

511K

11

38

220PF

20% 2 10V X5R-CERM 0402-8

C3816 ROOM=MAMBA_MESA

R3808

1% 1/32W MF 2 01005 ROOM=MAMBA_MESA

1

10UF

GND EPAD

38

C3823

R3809 1

38 38

ROOM=MAMBA_MESA

5% 2 25V NP0-C0G-CERM 01005

1% 1/32W MF 2 01005 ROOM=MAMBA_MESA

SPI_AP_TO_MESA_SCLK

38

56PF

511K

11

38

PP2V75_MAMBA_CONN

3 EN

MAMBA_LDO_EN

OMIT

SPI_AP_TO_MESA_MOSI_CONN

01005

2

LP5907SNX-2.75 X2SON VOUT 1

ROOM=PMU

2 ROOM=MAMBA_MESA

D

48

U3801

ROOM=MAMBA_MESA

1

48

TI:353S00576 ST:353S00932

NOTE: OUTPUT IMPDEANCE MUST BE >0.005-OHM IN ORDER TO MEET CAP ESR REQUIREMENT PER LDO SPEC. VENDOR ALSO RECOMMENDS CIN = COUT FOR STABILITY

1

2.2UF

MESA DIGITAL I/O SPI_AP_TO_MESA_MOSI

38

PP_VDD_BOOST

100PF

11

MESA_TO_AOP_FDINT_CONN I2C_MESA_TURTLE_SDA_CONN I2C_MESA_TURTLE_SCL_CONN MESA_TO_BOOST_EN_CONN MESA_TO_AP_INT_CONN SPI_AP_TO_MESA_SCLK_CONN SPI_AP_TO_MESA_MOSI_CONN AOP_TO_MESA_BLANKING_EN_CONN SPI_MESA_TO_AP_MISO_CONN PP2V75_MAMBA_CONN

38

01005 ROOM=MAMBA_MESA

38

ROOM=MAMBA_MESA

5

1

PP1V8_MESA_CONN

30

150OHM-25%-200MA-0.7DCR

PP16V0_MESA

Matches flex_x452_acf, schematic revision 1.5.0 pinout

ROOM=MAMBA_MESA

ROOM=MAMBA_MESA

37 4

29

38

0201 ROOM=MAMBA_MESA

1

CRITICAL

MLB: 516S00141 (RCPT) FLEX: 516S00142 (PLUG)

80-OHM-25%-0.52A-0.17OHM

48 19

2

MAMBA AND MESA CONNECTOR FL3803

19

3

5% 25V 2 NP0-C0G-CERM 01005

ROOM=MAMBA_MESA

ROOM=MAMBA_MESA

C3818 56PF

5% 2 25V NP0-C0G-CERM 01005

ROOM=MAMBA_MESA

ROOM=MAMBA_MESA

R3801

B

11

MESA_TO_AP_INT

1

681

2

1% 1/32W MF 01005

1

MESA_TO_AP_INT_CONN

38

MESA_TO_BOOST_EN_CONN

38

B

C3819 100PF

5% 2 16V NP0-C0G 01005

ROOM=MAMBA_MESA

ROOM=MAMBA_MESA

R3802 37 4

MESA_TO_BOOST_EN

1

681

2

1% 1/32W MF 01005

1

FL3806

150OHM-25%-200MA-0.7DCR

C3801 100PF

13

5% 2 16V NP0-C0G 01005

ROOM=MAMBA_MESA

MESA_TO_AOP_FDINT

1

MESA_TO_AOP_FDINT_CONN

2 01005

1

ROOM=MAMBA_MESA

5% 2 16V NP0-C0G 01005

FL3811

AOP_TO_MESA_BLANKING_EN

1

2

AOP_TO_MESA_BLANKING_EN_CONN

01005

#24543342: stuff 100pF

ROOM=MAMBA_MESA

150OHM-25%-200MA-0.7DCR 13

C3826 100PF

ROOM=MAMBA_MESA

38

1

38

C3825 56PF

5% 2 25V NP0-C0G-CERM 01005 ROOM=MAMBA_MESA

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

B2B:ORB & MESA DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

38 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

38 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7 FL3912

DISPLAY POWER C3901

1

2 1

10UF

C3929

1

ROOM=DISPLAY_B2B

10UF

20% 10V X5R-CERM 2 0402-8

C3933

1

2.2UF

20% 2 10V X5R-CERM 0402-8

ROOM=DISPLAY_B2B

PP5V7_LCM_AVDDH_CONN

1 0201

5

DISPLAY MIPI

240-OHM-25%-0.42A-0.31DCR

PP5V7_LCM_AVDDH

37

6

L3901

C3913

9

90_MIPI_AP_TO_LCM_CLK_P

9

90_MIPI_AP_TO_LCM_CLK_N

CRITICAL 1

3

90_MIPI_AP_TO_LCM_CLK_CONN_P

45

90_MIPI_AP_TO_LCM_CLK_CONN_N

45

90_MIPI_AP_TO_LCM_DATA0_CONN_P

45

2 ROOM=DISPLAY_B2B

ROOM=DISPLAY_B2B

L3902

65OHM-0.7-2GHZ-3.4OHM TAM0605 CRITICAL

240-OHM-25%-0.42A-0.31DCR 2

PP1V8_LCM_CONN 1

ROOM=DISPLAY_B2B

AP/TOUCH INTERFACE

SYM_VER-1

1 0201

D

1

SYM_VER-1

4

FL3906

25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 30 29

2

65OHM-0.7-2GHZ-3.4OHM TAM0605

45

5% 2 10V C0G-CERM 01005

ROOM=DISPLAY_B2B

PP1V8

3

220PF

20% 2 6.3V X5R-CERM 0201-1

ROOM=DISPLAY_B2B

4

C3934

1

2.2UF

45

90_MIPI_AP_TO_LCM_DATA0_P

C3914 220PF

9

5% 2 10V C0G-CERM 01005

20% 2 6.3V X5R-CERM 0201-1

9

4

ROOM=DISPLAY_B2B

1

3

90_MIPI_AP_TO_LCM_DATA0_N

D

2

90_MIPI_AP_TO_LCM_DATA0_CONN_N

45

90_MIPI_AP_TO_LCM_DATA1_CONN_P

45

90_MIPI_AP_TO_LCM_DATA1_CONN_N

45

ROOM=DISPLAY_B2B

L3903

ROOM=DISPLAY_B2B

65OHM-0.7-2GHZ-3.4OHM TAM0605 SYM_VER-1

9

90_MIPI_AP_TO_LCM_DATA1_P

9

90_MIPI_AP_TO_LCM_DATA1_N

4

1

3

CRITICAL

FL3904

2

150OHM-25%-200MA-0.7DCR

ROOM=DISPLAY_B2B 12

2

AP_TO_TOUCH_MAMBA_RESET_L

2

LCM_TO_CHESTNUT_PWR_EN_CONN

01005

1

45

FL3908

ROOM=DISPLAY_B2B

ROOM=MAMBA_MESA

2

PN5V7_LCM_MESON_AVDDN

1 0201

C3909

FL3915

220PF

5% 2 10V C0G-CERM 01005

FL3909

C

150OHM-25%-200MA-0.7DCR 12

1 0201

C3910

1

220PF

33-OHM-25%-1500MA 1

C3932

ROOM=DISPLAY_B2B

2.2UF

C3940

FL3911

5% 2 10V C0G-CERM 01005 ROOM=DISPLAY_B2B

R3915

ROOM=DISPLAY_B2B

20

PMU_TO_LCM_PANICB

10

1

PMU_TO_LCM_PANICB_CONN

2

5% 1/32W MF 01005

C3911

1

FL3922

150OHM-25%-200MA-0.7DCR

45

C3918

11

2

SPI_AP_TO_TOUCH_CS_L

01005

5% 2 16V NP0-C0G 01005

AOP/TOUCH INTERFACE

PP5V1_TOUCH_VDDH

37

0201

ROOM=DISPLAY_B2B

11

NOSTUFF C3922

37

FL3916

FL3901

53 23 20 13

2

LCM_TO_MANY_BSYNC

1 1

ROOM=DISPLAY_B2B

PP_LCM_BL_ANODE_CONN

ROOM=DISPLAY_B2B

1

220PF

B

2% 2 50V C0G 0201

PP_LCM_BL_CAT1

0201

13

ROOM=DISPLAY_B2B

2

UART_TOUCH_TO_AOP_RXD

PP_LCM_BL_CAT1_CONN

1 1

C3904

1

FL3918

0201 ROOM=DISPLAY_B2B

2

UART_AOP_TO_TOUCH_TXD

PP_LCM_BL_CAT2_CONN 1

SPI_TOUCH_TO_AP_MISO

5% 2 25V NP0-C0G-CERM 01005 ROOM=DISPLAY_B2B

2

1 01005

45

1

ROOM=DISPLAY_B2B

C3920

1 1

ROOM=DISPLAY_B2B

C3905

TOUCH_TO_AP_INT_L_CONN

45

C3926

150OHM-25%-200MA-0.7DCR 12

TOUCH_TO_AP_INT_L

2

1 01005

45

ROOM=DISPLAY_B2B

C3921

1

C3927 100PF

5% 2 16V NP0-C0G 01005 ROOM=DISPLAY_B2B

56PF

5% 2 25V NP0-C0G-CERM 01005

5% 2 35V NP0-C0G 01005

45

ROOM=DISPLAY_B2B

FL3920

UART_AOP_TO_TOUCH_TXD_CONN

01005

SPI_TOUCH_TO_AP_MISO_CONN 5% 2 25V NP0-C0G-CERM 01005

ROOM=DISPLAY_B2B

100PF

R3908

ROOM=DISPLAY_B2B

ROOM=DISPLAY_B2B 11

AP_TO_CUMULUS_CLK32K

2

33.2

AP_TO_CUMULUS_CLK_32K_CONN

1

1% 1/32W MF 01005 ROOM=DISPLAY_B2B

AC Coupling Caps A

B

56PF

150OHM-25%-200MA-0.7DCR 13

2

11

5% 2 25V NP0-C0G-CERM 01005

ROOM=DISPLAY_B2B

C3925 56PF

56PF

33-OHM-25%-1500MA

PP_LCM_BL_CAT2

1

ROOM=DISPLAY_B2B

UART_TOUCH_TO_AOP_RXD_CONN

ROOM=DISPLAY_B2B

5% 35V 2 NP0-C0G 01005

37

1

FL3919

100PF

FL3903

2

150OHM-25%-200MA-0.7DCR

01005 1

45

5% 2 25V NP0-C0G-CERM 01005 ROOM=DISPLAY_B2B

01005

150OHM-25%-200MA-0.7DCR

33-OHM-25%-1500MA 37

SPI_AP_TO_TOUCH_MOSI

FL3917

FL3902

2

SPI_AP_TO_TOUCH_MOSI_CONN

C3923 56PF

ROOM=DISPLAY_B2B

ROOM=DISPLAY_B2B

1

11

5% 2 25V NP0-C0G-CERM 01005

C3903

1

FL3924

56PF

VOLTAGE=25.0V

0201

45

150OHM-25%-200MA-0.7DCR

45

C3919

2

ROOM=DISPLAY_B2B

ROOM=DISPLAY_B2B

LCM_TO_MANY_BSYNC_CONN

01005

33-OHM-25%-1500MA

PP_LCM_BL_ANODE

1

5% 25V NP0-C0G-CERM 2 01005

150OHM-25%-200MA-0.7DCR

0.00 0% 1/32W MF 01005

56PF

ROOM=DISPLAY_B2B

2

1

SPI_AP_TO_TOUCH_SCLK

C3912

5% 2 10V C0G-CERM 01005

1

SPI_AP_TO_TOUCH_SCLK_CONN

C3924

R3923

220PF

BACKLIGHT

45

5% 2 25V NP0-C0G-CERM 01005 ROOM=DISPLAY_B2B

PP5V1_TOUCH_VDDH_CONN 1

ROOM=DISPLAY_B2B

SPI_AP_TO_TOUCH_CS_CONN_L 56PF

240-OHM-25%-0.42A-0.31DCR 1

1

ROOM=DISPLAY_B2B

ROOM=DISPLAY_B2B

2

1

100PF

ROOM=DISPLAY_B2B

5% 2 10V C0G-CERM 01005

ROOM=DISPLAY_B2B

C

220PF

PP1V8_TOUCH_CONN 1

45

C3917

ROOM=DISPLAY_B2B 2

220PF

20% 6.3V X5R-CERM 2 0201-1

1

20% 2 6.3V X5R-CERM 0201-1

ROOM=DISPLAY_B2B

2 0201

1

AP_TO_LCM_RESET_CONN_L

5% 1/32W MF 01005

2.2UF

5% 2 10V C0G-CERM 01005

FL3910

PP1V8_TOUCH

2

1 R3901 100K

PP5V7_MESON_AVDDH_CONN 1

ROOM=DISPLAY_B2B

47 46 38 18

1

ROOM=DISPLAY_B2B

2

PP5V7_MESON_AVDDH

01005

AP_TO_LCM_RESET_L

240-OHM-25%-0.42A-0.31DCR 37

To Mamba/Mesa B2B

PN5V7_LCM_MESON_AVDDN_CONN 1

ROOM=DISPLAY_B2B

To Display B2B

ROOM=DISPLAY_B2B

240-OHM-25%-0.42A-0.31DCR 37

C3902

5% 2 10V C0G-CERM 01005

220PF

5% 2 10V C0G-CERM 01005

1

45

C3928 100PF

5% 2 16V NP0-C0G 01005

ROOM=DISPLAY_B2B

SYNC_MASTER=Sync

PP_VDD_MAIN

28 27 26 25 23 21 19 18 10 9 4 53 46 41 40 37 35 34 33 31 30

SYNC_DATE=06/06/2016

PAGE TITLE

1

C3930 220PF

5% 2 10V C0G-CERM 01005 ROOM=DISPLAY_B2B

1

C3931 220PF

5% 2 10V C0G-CERM 01005 ROOM=DISPLAY_B2B

1

C3935 220PF

5% 2 10V C0G-CERM 01005 ROOM=DISPLAY_B2B

1

C3936

1

220PF

C3937 220PF

5% 2 10V C0G-CERM 01005

5% 2 10V C0G-CERM 01005

ROOM=DISPLAY_B2B

ROOM=DISPLAY_B2B

1

1

C3938 220PF

B2B FILTERS: DISPLAY & TOUCH

C3939 220PF

DRAWING NUMBER

5% 10V 2 C0G-CERM 01005

5% 2 10V C0G-CERM 01005

Apple Inc.

051-00482 REVISION

8.0.0

R

ROOM=DISPLAY_B2B

AC return path for LCM MIPI which is referenced to GND and VDD_MAIN

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

39 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

For placement "along the way" as we route from SOC to B2B.

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

39 OF 81

IV ALL RIGHTS RESERVED

8

38 45

220PF

5% 2 10V C0G-CERM 01005

C3916

1

C3915 220PF

1

ROOM=DISPLAY_B2B

1

ROOM=DISPLAY_B2B

150OHM-25%-200MA-0.7DCR

LCM_TO_CHESTNUT_PWR_EN

AP_TO_TOUCH_MAMBA_RESET_CONN_L

01005

FL3913

37 20

1

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D

PP3V0_TRISTAR_ANT_PROX 1

PP_ACC_VAR

C4003

1

1.0UF

TRISTAR 2

20% 2 6.3V X5R-CERM 01005

ROOM=TRISTAR

4 21 41

47 46 41 37 36 32 21 20 18 16 53 52 48

PP1V8_SDRAM

3 1

C4004

D

0.01UF

ROOM=TRISTAR

10% 2 6.3V X5R 01005

z=0.45mm EVT: 343S00091 (P2:343S00078)

VDD_1V8 F3

TRISTAR_TO_PMU_USB_BRICK_ID

1 1

6.34K 2 1% 1/32W MF 01005

C4001 0.01UF

31 31

53 53

L4022

15NH-250MA 1

90_USB_AP_DATA_P

2 0201

90_MIKEYBUS_DATA_P 90_MIKEYBUS_DATA_N

C3 C4

90_USB_BB_DATA_P 90_USB_BB_DATA_N

A1 B1

TRISTAR_USB_BRICK_ID_R

C2

DIG_DP

WLCSP

DIG_DN

90_USB_AP_DATA_L_P 90_USB_AP_DATA_L_N

A3 B3

UART_AP_TO_ACCESSORY_TXD UART_ACCESSORY_TO_AP_RXD

E2 E1

UART_AP_DEBUG_TXD UART_AP_DEBUG_RXD

F2 F1

USB1_DP USB1_DN BRICK_ID

12

15NH-250MA 7

1

90_USB_AP_DATA_N

53 27 26 25 23 21 19 18 10 9 4 46 41 39 37 35 34 33 31 30 28

12

NC

PP_VDD_MAIN 7

220PF

5% 2 10V C0G-CERM 01005

1

C4008

7

SWD_DOCK_TO_AP_SWCLK SWD_DOCK_BI_AP_SWDIO

220PF

5% 2 10V C0G-CERM 01005

ROOM=SOC

P_IN F6 ACC1 C5 ACC2 E5

PP5V0_USB_RVP PP_TRISTAR_ACC1 PP_TRISTAR_ACC2

4 41

D2 D1 A5 B5

1

ROOM=TRISTAR

Sm Footprint: 376S00135

90_TRISTAR_DP1_CONN_P 90_TRISTAR_DP1_CONN_N

DP2 A4 DN2 B4

90_TRISTAR_DP2_CONN_P 90_TRISTAR_DP2_CONN_N

C4006 1UF

4 41

DP1 A2 DN1 B2

CON_DET_L E3

UART0_TX UART0_RX

D6 POW_GATE_EN* 21

UART1_TX UART1_RX

SWITCH_EN E4 HOST_RESET B6

UART2_TX UART2_RX

SDA SCL INT BYPASS

JTAG_CLK JTAG_DIO DVSS DVSS DVSS

C4007

2

5% 1/32W MF 2 01005 ROOM=TRISTAR

20% 2 16V CER-X5R 0201

4 41 4 41

4 41 4 41

TRISTAR_CON_DETECT_L

4 41

TRISTAR_TO_TIGRIS_VBUS_OFF

D3 D4 C6 E6

PMU_TO_AOP_TRISTAR_ACTIVE_READY TRISTAR_TO_PMU_HOST_RESET

7 13 20 37 20

I2C0_AP_SDA I2C0_AP_SCL TRISTAR_TO_AOP_INT TRISTAR_BYPASS

PP4001 P2MM-NSM 1

#25714843: Remove R4003 Weak PD

SM

PP

47 47

B

13

1

C4005 1.0UF

20% 2 6.3V X5R 0201-1 ROOM=TRISTAR

F5 C1 A6

1

10K

POW_GATE_EN* is 6V-tolerant 12

ROOM=TRISTAR

B

12

2 0201

S

ROOM=TRISTAR

USB0_DP USB0_DN

ROOM=TRISTAR

L4021

R4002

DFN

U4001

ROOM=PMU

7

1

C

RV3CA01ZP

G

CBTL1610A3BUK

ROOM=PMU

10% 2 6.3V X5R 01005

1

TRISTAR_REVERSE_GATE

ROOM=TRISTAR

R4001 20

CRITICAL

Q4001 ACC_PWR D5

C

C4002 0.1UF

20% 2 6.3V X5R 0201-1

19 27

PP5V0_USB

VDD_3V0 F4

53 41 29 19

ROOM=SOC

AC return path for USB pairs which is referenced to GND and VDD_MAIN

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

TRISTAR 2 DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

40 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

40 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

ANTENNA

2

LOWER MIC1/4

Please loop in Matt Mow (Antenna Team) when changing these components!

ARC CONTROL

31

LOWERMIC1_TO_CODEC_AIN1_P

1

FL4116

150OHM-25%-200MA-0.7DCR 2 1 LOWERMIC1_TO_CODEC_AIN1_CONN_POS 01005

1

ROOM=DOCK_B2B

41

C4128 56PF

5% 2 25V NP0-C0G-CERM 01005

#26118161: Update FL4104 to 49.9ohm

FL4103

150OHM-25%-200MA-0.7DCR 2

PP3V0_LAT_CONN

1 01005

1

ROOM=DOCK_B2B

R4104

41 47 36

C4134

I2C_HOMER_SCL

1

I2C_HOMER_SCL_CONN

2

41

5% 2 10V C0G-CERM 01005

1

C4135

FL4112

150OHM-25%-200MA-0.7DCR 2

47 36

PP3V0_LAT1_CONN 1

ROOM=DOCK_B2B

I2C_HOMER_SDA

1

41

C4119

FL4108

FL4118

41

C4136

32

56PF

PP_CODEC_TO_LOWERMIC1_BIAS

2

41 35

1

PP1V8_LAT_ARC_CONN

01005

1

ROOM=DOCK_B2B

ARC1_TO_SOLENOID1_OUT_POS LOWERMIC4_TO_CODEC_AIN2_P

ARC1_TO_SOLENOID1_OUT_NEG

C4101

ROOM=DOCK_B2B

LOWERMIC4_TO_CODEC_AIN2_N

Antenna GPIO

5% 2 16V NP0-C0G-CERM 01005 ROOM=DOCK_B2B

0.00

1

2

53

2

BB_TO_LAT_GPO1

41

C4122

1

FL4121

BB_TO_LAT_GPO1_CONN 1

ROOM=DOCK_B2B

41

C4110

32

PP_CODEC_TO_LOWERMIC4_BIAS

SPEAKER1

ROOM=DOCK_B2B

FL4114

1

BB_TO_LAT_GPO2_CONN

41

01005

34

1

C4133

5% 2 10V C0G-CERM 01005

150OHM-25%-200MA-0.7DCR

ROOM=DOCK_B2B

41

220PF

FL4102

2

1

ROOM=DOCK_B2B

ROOM=DOCK_B2B

ROOM=DOCK_B2B

ROOM=DOCK_B2B

01005

5% 2 25V NP0-C0G-CERM 01005

5% 2 16V NP0-C0G-CERM 01005

C

150OHM-25%-200MA-0.7DCR 2 1 PP_CODEC_TO_LOWERMIC4_BIAS_CONN

56PF

BB_TO_LAT_GPO2

C4132

5% 2 25V NP0-C0G-CERM 01005

01005

53

41

56PF

33PF

ROOM=DOCK_B2B

1

FL4101

BB_TO_LAT_ANT_DATA_CONN 1

150OHM-25%-200MA-0.7DCR 2 1 LOWERMIC4_TO_CODEC_AIN2_CONN_NEG ROOM=DOCK_B2B

150OHM-25%-200MA-0.7DCR

0% 1/32W MF 01005

ROOM=DOCK_B2B

FL4120 01005

R4110 BB_TO_LAT_ANT_DATA

5% 10V C0G-CERM 2 01005 31

C4121

C4131

5% 2 25V NP0-C0G-CERM 01005

1

220PF

ROOM=DOCK_B2B

41

33PF

C 53

C4102

1

220PF

BB_TO_LAT_ANT_SCLK_CONN

41

56PF

R4109

ROOM=DOCK_B2B

1

ROOM=DOCK_B2B

5% 10V C0G-CERM 2 01005

1

150OHM-25%-200MA-0.7DCR 2 1 LOWERMIC4_TO_CODEC_AIN2_CONN_POS 01005

ROOM=DOCK_B2B

0% 1/32W MF 01005

ROOM=DOCK_B2B

FL4119

31

2

C4130

5% 2 10V C0G-CERM 01005

C4120 41 35

41

220PF

ROOM=DOCK_B2B

41

5% 2 10V C0G-CERM 01005

0.00

1

ROOM=DOCK_B2B

220PF

1

150OHM-25%-200MA-0.7DCR 2 1 PP_CODEC_TO_LOWERMIC1_BIAS_CONN

ROOM=DOCK_B2B

150OHM-25%-200MA-0.7DCR

BB_TO_LAT_ANT_SCLK

ROOM=DOCK_B2B

01005

5% 2 25V NP0-C0G-CERM 01005

ARC1

C4129

5% 2 25V NP0-C0G-CERM 01005

CKPLUS_WAIVE=I2C_PULLUP

1

D

41

56PF

I2C_HOMER_SDA_CONN

VOLTAGE=3.0V

5% 2 10V C0G-CERM 01005

53

1

ROOM=DOCK_B2B

2

220PF

PP1V8_SDRAM

01005

ROOM=DOCK_B2B

01005

1 01005

53 52 48 32 21 20 18 16 47 46 40 37 36

150OHM-25%-200MA-0.7DCR 2 1 LOWERMIC1_TO_CODEC_AIN1_CONN_NEG

150OHM-25%-200MA-0.7DCR

FL4107

PP3V0_TRISTAR_ANT_PROX

LOWERMIC1_TO_CODEC_AIN1_N

5% 2 25V NP0-C0G-CERM 01005

ROOM=DOCK_B2B

53 40 29 19

31

56PF

ROOM=DOCK_B2B

ROOM=DOCK_B2B

FL4117

CKPLUS_WAIVE=I2C_PULLUP

1% 1/32W MF 01005

220PF

D

49.9

SPEAKER_TO_SPEAKERAMP1_VSENSE_P

150OHM-25%-200MA-0.7DCR 2 1 SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_POS

C4111

01005

1

ROOM=DOCK_B2B

56PF

41

C4126 220PF

5% 2 25V NP0-C0G-CERM 01005

5% 2 10V C0G-CERM 01005

ROOM=DOCK_B2B

FL4115

Per ANT Erdinc, change to cap 34

SPEAKER_TO_SPEAKERAMP1_VSENSE_N

ROOM=DOCK_B2B

150OHM-25%-200MA-0.7DCR 2 1 SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_NEG 01005

1

ROOM=DOCK_B2B

41

C4127 220PF

5% 2 10V C0G-CERM 01005

VOLTAGE=16.0V 40 21 4

B

C4109

1

0.1UF

C4105

1

0.1UF

10% 25V 2 X5R 0201

ROOM=DOCK_B2B

ROOM=DOCK_B2B

PP5V0_USB

C4106 0.1UF

10% 25V X5R 2 0201

ROOM=DOCK_B2B

41 34 41 46 41 41 41

1

C4107

10% 25V 2 X5R 0201

ROOM=DOCK_B2B

C4108

1

330PF

10% 16V CER-X7R 2 01005

5% 25V 2 NP0-C0G-CERM 01005

ROOM=DOCK_B2B

40 4

40 4 40 4

31 41 32

47 47

A 41 35 35 41 41

41 34

53 49

1

5% 2 10V C0G-CERM 01005

50

ROOM=DOCK_B2B

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47

90_TRISTAR_DP2_CONN_P 90_TRISTAR_DP2_CONN_N 90_TRISTAR_DP1_CONN_N 90_TRISTAR_DP1_CONN_P MIKEYBUS_REFERENCE LOWERMIC1_TO_CODEC_AIN1_CONN_POS LOWERMIC1_TO_CODEC_BIAS_FILT_RET I2C_MIC1_SDA_CONN I2C_MIC1_SCL_CONN ARC1_TO_SOLENOID1_OUT_POS SOLENOID1_TO_ARC1_VSENSE_POS PP3V0_LAT_CONN SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_POS

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48

41 34

#25429221:Carrier Dock flex to add +1 ACC2 pin

PP_TRISTAR_ACC2_CONN BB_TO_LAT_GPO2_CONN LOWERMIC4_TO_CODEC_AIN2_CONN_POS LOWERMIC4_TO_CODEC_BIAS_FILT_RET BB_TO_LAT_GPO1_CONN BB_TO_LAT_ANT_SCLK_CONN BB_TO_LAT_ANT_DATA_CONN PP1V8_LAT_ARC_CONN PP3V0_LAT1_CONN

5% 2 10V C0G-CERM 01005

TRISTAR

41 41

ROOM=DOCK_B2B

32 41

51

USB AC Coupling

R4102

41 41 40 4

TRISTAR_CON_DETECT_L

2

1.00K 1

41

TRISTAR_CON_DETECT_CONN_L

5% 1/32W MF 01005

41

1

10-OHM-1.1A

41 40 4

1

PP_TRISTAR_ACC1

01005 ROOM=DOCK_B2B

53 27 26 25 23 21 19 18 10 9 4 46 40 39 37 35 34 33 31 30 28

C4116

PP_VDD_MAIN 1

5% 10V 2 C0G-CERM 01005

PP_TRISTAR_ACC1_CONN 1

C4117

C4143 220PF

ROOM=DOCK_B2B

2

41

AC return path for USB pairs which is referenced to GND and VDD_MAIN

5% 2 16V NP0-C0G 01005

FL4105

41

41

27PF

ROOM=DOCK_B2B

LOWERMIC1_TO_CODEC_AIN1_CONN_NEG PP_CODEC_TO_LOWERMIC1_BIAS_CONN TRISTAR_CON_DETECT_CONN_L

C4104 220PF

41

41

ROOM=SOC

VOLTAGE=4.3V

100PF

ARC1_TO_SOLENOID1_OUT_NEG ARC1_TO_SOLENOID1_OUT_POS SOLENOID1_TO_ARC1_VSENSE_NEG I2C_HOMER_SDA_CONN I2C_HOMER_SCL_CONN

5% 2 16V NP0-C0G 01005

35 41

FL4106

35 41

22-OHM-25%-1800MA

35 41

40 4

PP_TRISTAR_ACC2

1

1

C4118

SYNC_DATE=06/06/2016

PAGE TITLE

PP_TRISTAR_ACC2_CONN

0201

41

SYNC_MASTER=Sync

ROOM=DOCK_B2B

2

B2B:DOCK FLEX

41

DRAWING NUMBER

VOLTAGE=4.3V

Apple Inc.

100PF

#25098110: Decrease DCR

SPEAKERAMP1_TO_SPEAKER_OUT_POS

SPEAKERAMP1_TO_SPEAKER_OUT_NEG 1

ROOM=DOCK_B2B

41 34

C4103 220PF

F-ST-SM

ROOM=DOCK_B2B

SPEAKERAMP1_TO_SPEAKER_OUT_NEG SPEAKER_TO_SPEAKERAMP1_VSENSE_CONN_NEG BB_TO_LAT_GPO3_CONN LOWERMIC4_TO_CODEC_AIN2_CONN_NEG PP_CODEC_TO_LOWERMIC4_BIAS_CONN PP_TRISTAR_ACC1_CONN

B

SPEAKERAMP1_TO_SPEAKER_OUT_POS

245857

1

56PF

#22499940:Change Net Name to POS/NEG 40 4

J4101

5% 2 16V NP0-C0G 01005

52

54

051-00482 REVISION

8.0.0

R

ROOM=DOCK_B2B

DOCK FLEX CONNECTOR

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

41 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

41 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

spare DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

42 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

42 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

spare DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

43 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

43 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

STROBE1

5

4

3

STROBE2

2

1

BUTTONS R4402

PP_STROBE_DRIVER1_WARM_LED

C4402

1

1

220PF

C4409

C4410

27PF

5% 10V 2 C0G-CERM 01005

D

PP_STROBE_DRIVER2_WARM_LED

26 45

1

1

220PF

5% 2 16V NP0-C0G 01005

ROOM=RIGHT_BUTTON

26 45

100

1

C4401

5% 6.3V 2 NP0-C0G 0201 ROOM=RIGHT_BUTTON

BUTTON_POWER_KEY_CONN_L

2

5% 1/32W MF 01005

1

27PF

5% 2 16V NP0-C0G 01005

ROOM=RIGHT_BUTTON

BUTTON_POWER_KEY_L

C4413 27PF

5% 10V 2 C0G-CERM 01005

ROOM=RIGHT_BUTTON

20

1

0201

ROOM=RIGHT_BUTTON

5.5V-6.2PF

DZ4401 ROOM=RIGHT_BUTTON

2

ROOM=RIGHT_BUTTON

D

CHASSIS_GND_BS401 PP_STROBE_DRIVER1_COOL_LED

PP_STROBE_DRIVER2_COOL_LED

26 45

C4406

1

1

220PF

C4408

C4411

27PF

5% 10V C0G-CERM 2 01005

220PF

ROOM=RIGHT_BUTTON

120-OHM-0.220A

C4412 27PF

5% 10V C0G-CERM 2 01005

5% 2 16V NP0-C0G 01005

ROOM=RIGHT_BUTTON

1

20

5% 2 16V NP0-C0G 01005

ROOM=RIGHT_BUTTON

1

BUTTON_RINGER_A

C4418

1

2

BUTTON_RINGER_A_CONN

ROOM=LEFT_BUTTON

ROOM=RIGHT_BUTTON

1

5% 6.3V NP0-C0G 2 0201

0201

5.5V-6.2PF

ROOM=LEFT_BUTTON

DZ4402 ROOM=LEFT_BUTTON

2

150OHM-25%-200MA-0.7DCR 26

STROBE_MODULE_NTC

R4401 1 27K

CHASSIS_GND_BS401

2

STROBE_MODULE_NTC_CONN 45 1

ROOM=RIGHT_BUTTON

C4407 220PF

R4405

5% 2 10V C0G-CERM 01005

20

BUTTON_VOL_DOWN_L

1

C4419

ROOM=RIGHT_BUTTON #24544474: Can R4401 be changed to 5%?

100

100PF

BUTTON_VOL_DOWN_CONN_L

2

5% 1/32W MF 01005

1

5% 16V NP0-C0G 2 01005

1

ROOM=LEFT_BUTTON

DZ4403

2

ROOM=LEFT_BUTTON

CHASSIS_GND_BS401

HAWKING

45

12V-33PF 01005-1

ROOM=LEFT_BUTTON

4 44

C

R4406 #24678255:DOE with 10% and/20% cap

20 12

BUTTON_VOL_UP_L 100PF

0.22UF 1

HAWKING_TO_CODEC_AIN7_N

1

C4420

C4417 31

4 44

01005

0.5% 1/32W MF 01005 2 ROOM=RIGHT_BUTTON

C

45

01005

27PF

FL4404

1

4 44

FL4407

26 45

1

45

2

HAWKING_TO_CODEC_AIN7_N_CONN

1

5% 16V 2 NP0-C0G 01005

45

20% 6.3V X5R 01005

ROOM=LEFT_BUTTON

100

BUTTON_VOL_UP_CONN_L

2

5% 1/32W MF 01005 ROOM=LEFT_BUTTON

1

45

DZ4404

12V-33PF 01005-1

2

ROOM=LEFT_BUTTON

CHASSIS_GND_BS401

4 44

ROOM=RIGHT_BUTTON

FL4405

C4421

150OHM-25%-200MA-0.7DCR 1 2 HAWKING_TO_CODEC_AIN7_C_P

0.22UF 1

HAWKING_TO_CODEC_AIN7_P

31

2

CKPLUS_WAIVE=MISS_N_DIFFPAIR

20% 6.3V X5R 01005

HAWKING_TO_CODEC_AIN7_P_CONN

01005 ROOM=RIGHT_BUTTON

1

C4415 56PF

5% 2 25V NP0-C0G-CERM 01005

ROOM=RIGHT_BUTTON

45

NOSTUFF

1

C4422 180PF

10% 2 10V CERM 01005

ROOM=RIGHT_BUTTON

ROOM=RIGHT_BUTTON

FL4406

150OHM-25%-200MA-0.7DCR 19

B

1

PP1V8_HAWKING

2 01005

PP1V8_HAWKING_CONN 1

ROOM=RIGHT_BUTTON

C4416 2.2UF

20% 2 6.3V X5R-CERM 0201-1 ROOM=RIGHT_BUTTON

MIC2 (ANC REF)

1

45

B

C4414 220PF

5% 2 10V C0G-CERM 01005 ROOM=RIGHT_BUTTON

FL4403

150OHM-25%-200MA-0.7DCR 32

2

PP_CODEC_TO_REARMIC2_BIAS

1

PP_CODEC_TO_REARMIC2_BIAS_CONN

45

01005 ROOM=RIGHT_BUTTON

1

C4403 220PF

5% 2 10V C0G-CERM 01005 ROOM=RIGHT_BUTTON

FL4401

150OHM-25%-200MA-0.7DCR 31

2

REARMIC2_TO_CODEC_AIN3_P

1

REARMIC2_TO_CODEC_AIN3_CONN_P

45

01005 ROOM=RIGHT_BUTTON

1

C4404 56PF

5% 2 25V NP0-C0G-CERM 01005

A

ROOM=RIGHT_BUTTON SYNC_MASTER=Sync

FL4402

PAGE TITLE

150OHM-25%-200MA-0.7DCR 31

2

REARMIC2_TO_CODEC_AIN3_N

SYNC_DATE=06/06/2016

1

B2B FILTERS: RIGHT BUTTON FLEX REARMIC2_TO_CODEC_AIN3_CONN_N

DRAWING NUMBER

45

01005 ROOM=RIGHT_BUTTON

1

Apple Inc.

C4405 56PF

051-00482 REVISION

8.0.0

R

5% 2 25V NP0-C0G-CERM 01005 ROOM=RIGHT_BUTTON

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

44 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

44 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

J4502

BB35C-RA48-3A

516S00151 PLUG

53

J4501 AA26D-S022VA1

25 25 30 25 30 25 48 48

25

50

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48

FOREHEAD FLEX CONNECTOR

51

52

MLB: 516S00146 (MCO REV 27)

54

PP3V0_UT_SVDD_CONN LPDP_UT_BI_AP_AUX_CONN AP_TO_UT_SHUTDOWN_CONN_L UT_AND_NV_TO_LED_DRIVER_STROBE_EN_CONN UT_TO_NV_SYNC_J2501_CONN PP1V8_UT_CONN I2C_UT_SDA_CONN I2C_UT_SCL_CONN PP2V8_UT_AF_VAR_CONN

ROOM=RCAM_B2B

24

23

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

39

22

21

39

26

25

90_LPDP_UT_TO_AP_D2_CONN_N 90_LPDP_UT_TO_AP_D2_CONN_P 90_LPDP_UT_TO_AP_D3_CONN_N 90_LPDP_UT_TO_AP_D3_CONN_P

38

R4501

25 47

25

1 I2C_TOUCH_TO_MAMBA_SCL

200

47

2

1% 1/32W MF 01005

25

39 39

ROOM=DISPLAY_B2B

25

39 39

AP_TO_UT_CLK_CONN

25

PP2V9_UT_AVDD_CONN

25 46

39 39 39

39 25

PP1V2_UT_VDD_CONN

38

MAMBA_TO_LCM_MDRIVE I2C_DISP_EEPROM_SDA_CONN I2C_TOUCH_SCL_CONN SPI_TOUCH_TO_AP_MISO_CONN SPI_AP_TO_TOUCH_CS_CONN_L AP_TO_CUMULUS_CLK_32K_CONN SPI_AP_TO_TOUCH_SCLK_CONN UART_TOUCH_TO_AOP_RXD_CONN AP_TO_LCM_RESET_CONN_L PP5V1_TOUCH_VDDH_CONN PP1V8_TOUCH_CONN PN5V7_LCM_MESON_AVDDN_CONN PP5V7_MESON_AVDDH_CONN

CKPLUS_WAIVE=I2C_PULLUP

LCM_TO_MAMBA_MSYNC_CONN 1

C4507 56PF

5% 2 25V NP0-C0G-CERM 01005

PP4501 P2MM-NSM

ROOM=DISPLAY_B2B

SM

PP

1

39 39

39 4 39 4 39 4 46 4 46 4 46 4

C

F-ST-SM

49

F-ST-SM

25

1

DISPLAY / TOUCH FLEX CONNECTOR MLB: 516S00050

UTAH-D FLEX CONNECTOR 516S00152 RCPT (USED ON MLB) <-- THIS ONE D

2

TP_LCM_PIFA 90_MIPI_AP_TO_LCM_CLK_CONN_P 90_MIPI_AP_TO_LCM_CLK_CONN_N PP_LCM_BL_CAT1_CONN PP_LCM_BL_ANODE_CONN PP_LCM_BL_CAT2_CONN PP_LCM_BL34_CAT1_CONN PP_LCM_BL34_ANODE_CONN PP_LCM_BL34_CAT2_CONN

I2C_DISP_EEPROM_SCL_CONN I2C_TOUCH_BI_MAMBA_SDA SPI_AP_TO_TOUCH_MOSI_CONN TOUCH_TO_AP_INT_L_CONN AP_TO_TOUCH_MAMBA_RESET_CONN_L

47

D

CKPLUS_WAIVE=I2C_PULLUP

47 39 39 38 39

Per #25048465:No Satin flex support in CRB

UART_AOP_TO_TOUCH_TXD_CONN PMU_TO_LCM_PANICB_CONN PP1V8_LCM_CONN PP5V7_LCM_AVDDH_CONN LCM_TO_CHESTNUT_PWR_EN_CONN LCM_TO_MANY_BSYNC_CONN

39 39 39 39 39 39

90_MIPI_AP_TO_LCM_DATA0_CONN_P 90_MIPI_AP_TO_LCM_DATA0_CONN_N

39 39

90_MIPI_AP_TO_LCM_DATA1_CONN_P 90_MIPI_AP_TO_LCM_DATA1_CONN_N

39 39

90_MIPI_AP_TO_LCM_DATA2_CONN_P 90_MIPI_AP_TO_LCM_DATA2_CONN_N

46 46

90_MIPI_AP_TO_LCM_DATA3_CONN_P 90_MIPI_AP_TO_LCM_DATA3_CONN_N

46 46

C

ROOM=FOREHEAD

CRITICAL

J4503 245858036201829 41

29 29

29

29

48 47 29 29 29 46 33 29 48 48 29

B

29 29

PP2V9_NH_AVDD_CONN PP1V8_NH_IO_CONN AP_TO_NH_SHUTDOWN_CONN_L AP_TO_NH_CLK_CONN I2C_NH_SCL_CONN I2C_ALS_CONVOY_SCL_CONN PDM_CONVOY_TO_ADARE_DATA_CONN PP3V0_PROX_CONN SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_N SPEAKERAMP2_TO_SPEAKER_OUT_NEG I2C_PROX_SDA_CONN I2C_PROX_SCL_CONN PROX_BI_AP_AOP_INT_PWM_L_CONN PP_CODEC_TO_FRONTMIC3_BIAS_CONN FRONTMIC3_TO_CODEC_AIN4_CONN_P

37

38

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

39

COMBO BUTTON FLEX CONNECTOR

F-ST-SM

APPLE APN: 516S00150 APPLE APN: 516S00149

90_MIPI_NH_TO_AP_DATA0_P 90_MIPI_NH_TO_AP_DATA0_N

<-- THIS ONE ON MLB (matched MCO rev 27)

9 9

ROOM=RIGHT_BUTTON

90_MIPI_NH_TO_AP_CLK_P 90_MIPI_NH_TO_AP_CLK_N 90_MIPI_NH_TO_AP_DATA1_P 90_MIPI_NH_TO_AP_DATA1_N PP1V2_NH_DVDD_CONN I2C_NH_SDA_CONN ALS_TO_AP_INT_CONN_L I2C_ALS_CONVOY_SDA_CONN PDM_ADARE_TO_CONVOY_CLK_CONN PP3V0_ALS_CONVOY_CONN SPEAKER_TO_SPEAKERAMP2_VSENSE_CONN_P SPEAKERAMP2_TO_SPEAKER_OUT_POS FRONTMIC3_TO_CODEC_AIN4_CONN_N

9

J4504

9

AA37D-S014SVA1 20

PP_STROBE_DRIVER2_COOL_LED

16

15

STROBE_MODULE_NTC_CONN 44 PP1V8_HAWKING_CONN 44 HAWKING_TO_CODEC_AIN7_P_CONN

2

1

4

3

6

5

8

7

BUTTON_RINGER_A_CONN BUTTON_VOL_UP_CONN_L BUTTON_VOL_DOWN_CONN_L

10

9

12

11

14

13

PP_STROBE_DRIVER2_WARM_LED

18

44 26

PP_STROBE_DRIVER1_WARM_LED

22

44 26

MAKE_BASE=TRUE 9 9

44 26

29

44

XW4501 SHORT-20L-0.05MM-SM

48 29 47

44

HAWKING_TO_CODEC_AIN7_N_CONN

1

2

29

44

29

44

29

44

29 33 46 29

F-ST-SM

GND

19

17

PP_CODEC_TO_REARMIC2_BIAS_CONN REARMIC2_TO_CODEC_AIN3_CONN_N REARMIC2_TO_CODEC_AIN3_CONN_P REARMIC2_TO_CODEC_BIAS_FILT_RET I2C_MIC2_SDA_CONN I2C_MIC2_SCL_CONN BUTTON_POWER_KEY_CONN_L

44 44 44 32 47 47 44

B

PP_STROBE_DRIVER1_COOL_LED

26 44

21

40

42

CRITICAL

A

SYNC_MASTER=sync

SYNC_DATE=05/17/2016

PAGE TITLE

B2B FF SPECIFIC DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

45 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

45 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

THIS PAGE UNIQUE TO LARGE FORM FACTOR 2ND BACKLIGHT DRIVER - 4LED PP_LCM_BL34_ANODE 1

C4604

1

220PF

PP_VDD_MAIN

C4601

1

2.2UF

ROOM=BACKLIGHT34

C4611

1

2.2UF

20% 2 35V X5R 0402

20% 2 35V X5R 0402

ROOM=BACKLIGHT34

C4610

1

2.2UF

2% 2 50V C0G 0201 53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

C4609

1

2.2UF

20% 2 35V X5R 0402

ROOM=BACKLIGHT34

C4612

C4602

L4602

2.2UF

ROOM=BACKLIGHT34

9

90_MIPI_AP_TO_LCM_DATA2_P

90_MIPI_AP_TO_LCM_DATA2_P

ROOM=BACKLIGHT34 9

90_MIPI_AP_TO_LCM_DATA2_N

90_MIPI_AP_TO_LCM_DATA2_N

D4602 NSR0530P2T5G

U4601 LM3539A1 D4

37 11 37 11

47 47

37 9

CRITICAL

A ROOM=BACKLIGHT34

OUT A1

PP1V8_SDRAM

D3

VIO/HWEN

DWI_PMGR_TO_BACKLIGHT_DATA DWI_PMGR_TO_BACKLIGHT_CLK

C2 C3

SDI SCK

SW2_1 A3 SW2_2 A4

I2C1_AP_SDA I2C1_AP_SCL

B2 A2

SDA SCL

LED1 C1 LED2 B1

SW1 C4

90_MIPI_AP_TO_LCM_DATA2_CONN_N

45

D4601 DSN2

9

90_MIPI_AP_TO_LCM_DATA3_P

90_MIPI_AP_TO_LCM_DATA3_P

D1

TRIG

BB_TO_STROBE_DRIVER_GSM_BURST_IND

D2

INHIBIT

ROOM=DISPLAY_B2B

4

1

90_MIPI_AP_TO_LCM_DATA3_CONN_P

45

3

2

90_MIPI_AP_TO_LCM_DATA3_CONN_N

45

MAKE_BASE=TRUE

CRITICAL

9

90_MIPI_AP_TO_LCM_DATA3_N

90_MIPI_AP_TO_LCM_DATA3_N MAKE_BASE=TRUE

28

28

FL4601

33-OHM-25%-1500MA

46 46

46

1

PP_LCM_BL34_ANODE

2

ROOM=BACKLIGHT34

AP_TO_MUON_BL_STROBE_EN

D

CRITICAL

SYM_VER-1

BL34_SW2_LX PP_LCM_BL34_CAT1 PP_LCM_BL34_CAT2

2

A ROOM=BACKLIGHT34

CRITICAL

BL34_SW1_LX

3

PP_LCM_BL34_ANODE_CONN

0201

1

ROOM=DISPLAY_B2B

4 45

C4605 220PF

2% 2 50V C0G 0201

ROOM=DISPLAY_B2B

B3 B4

53 37 26

DSBGA

IN

45

TAM0605

NSR05F30NXT5G

SOD-923-1

90_MIPI_AP_TO_LCM_DATA2_CONN_P

GND GND

40 37 36 32 21 20 18 16 53 52 48 47 41

K

1

L4603 65OHM-0.7-2GHZ-3.4OHM

MAKE_BASE=TRUE

K

4

MAKE_BASE=TRUE

1

20% 6.3V CERM-X5R 2 0402-9 ROOM=BACKLIGHT34

ROOM=DISPLAY_B2B

SYM_VER-1

10UF

D

CRITICAL

65OHM-0.7-2GHZ-3.4OHM TAM0605

20% 2 35V X5R 0402

20% 35V 2 X5R 0402

ROOM=BACKLIGHT34

46

FL4602

33-OHM-25%-1500MA 46

1

PP_LCM_BL34_CAT1

2

PP_LCM_BL34_CAT1_CONN

0201

1

ROOM=DISPLAY_B2B

4 45

C4606 100PF

TOUCH I2C

ISP I2C1

C

25 18 17 16 13 12 11 9 8 7 5 52 48 47 39 30 29

47 39 38 18

PP1V8 1

1

R4603 1.00K

30 9

FL4603

R4711

46

10K

1

PP_LCM_BL34_CAT2

I2C_ISP_NV_SCL I2C_ISP_NV_SDA

MAKE_BASE=TRUE MAKE_BASE=TRUE

PP_LCM_BL34_CAT2_CONN 1

ROOM=DISPLAY_B2B

4 45

C4607 100PF

5% 2 35V NP0-C0G 01005 ROOM=DISPLAY_B2B

I2C_TOUCH_TO_MAMBA_SCL

26

2 0201

5% 1/32W MF 2 01005 ROOM=MAMBA_MESA

5% 1/32W MF 2 01005 ROOM=SOC

C

33-OHM-25%-1500MA 1

R4604

I2C_ISP_NV_SCL I2C_ISP_NV_SDA

ROOM=DISPLAY_B2B

PP1V8_TOUCH

1.00K

5% 1/32W MF 2 01005 ROOM=SOC

30 9

5% 2 35V NP0-C0G 01005

47

26

Dock B2B (Pg 41) FL4604

150OHM-25%-200MA-0.7DCR 53

2

BB_TO_LAT_GPO3

1 01005

VDD MAIN CAP AC Coupling Caps

ROOM=DOCK_B2B

ARC CAP

BB_TO_LAT_GPO3_CONN 1

41

C4608 56PF

CHESTNUT CAP

5% 2 25V NP0-C0G-CERM 01005 ROOM=DOCK_B2B

53 46 41 27 26 25 23 21 19 18 10 9 4 40 39 37 35 34 33 31 30 28

53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

PP_VDD_MAIN 1

C4618 220PF

5% 10V 2 C0G-CERM 01005

1

C4603 220PF

5% 2 10V C0G-CERM 01005

ROOM=DISPLAY_B2B

B

ROOM=DISPLAY_B2B

1

C4613 220PF

5% 10V 2 C0G-CERM 01005 ROOM=DISPLAY_B2B

1

C4615

53 28 27 26 25 23 21 19 18 10 9 4 46 41 40 39 37 35 34 33 31 30

PP_VDD_MAIN

C3525

220PF

PP_VDD_MAIN

C3722

1

10UF

5% 2 10V C0G-CERM 01005

10UF

20% 6.3V CERM-X5R 2 0402-9

20% 6.3V CERM-X5R 2 0402-9

ROOM=DISPLAY_B2B

UT B2B

1

ROOM=ARC1

PP2V9_UT_AVDD_CONN

ROOM=CHESTNUT

25 45

1

B

C2507 4UF

20% 6.3V 2 CER-X5R 0201

AC return path for LCM MIPI which is referenced to GND and VDD_MAIN

ROOM=RCAM_B2B

Top Speaker Compass Coil Extra RF GND ACC Buck Caps

SPEAKERAMP2_TO_SPEAKER_OUT_POS SPEAKERAMP2_TO_SPEAKER_OUT_NEG

45 33 29

PP_ACC_BUCK_VAR

27

TP4602 1

29 33 45

A

TP-P55 1

rf GROUND

C2707 2.2UF

1

20% 2 6.3V X5R-CERM 0201-1

R3332

1

1.1K

1.1K

1% 1/32W MF 2 01005

ROOM=TRISTAR

R3333

1% 1/32W MF 2 01005

ROOM=SPKAMP2

ROOM=SPKAMP2

NEG_COMPASS_COIL_COMP

POS_COMPASS_COIL_COMP

1

XW3333

A

SHORT-20L-0.05MM-SM SYNC_MASTER=sync

NO_XNET_CONNECTION

2

SYNC_DATE=06/17/2016

PAGE TITLE

ROOM=MAMBA_MESA

LARGE FORM FACTOR SPECIFIC

OMIT

DRAWING NUMBER

1

C3332

1

220PF

C3333

Apple Inc.

220PF

5% 2 10V C0G-CERM 01005

REVISION

8.0.0

R

5% 2 10V C0G-CERM 01005

ROOM=SPKAMP2

051-00482

ROOM=SPKAMP2

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

46 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

46 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

AP

3

PP1V8

I2C0

R4701

1

R4702

4.02K

D

PP1V8_TOUCH

46 39 38 18

1

R4712 10K

1% 1/32W MF 01005 2 ROOM=SOC

5% 1/32W MF 2 01005 ROOM=MAMBA_MESA 46

I2C0_AP_SCL I2C0_AP_SDA

I2C0_AP_SCL I2C0_AP_SDA

MAKE_BASE=TRUE MAKE_BASE=TRUE

NOSTUFF

C4701

#24544434

NOTE:MAMBA I2C 2.2K PULL-UPS TO PP1V8_TOUCH INSIDE GALILEO ADDING R3803, R3804 AS OPTION FOR TWEAKING VALUE

NOSTUFF

1

4.02K

1% 1/32W MF 01005 2 ROOM=SOC

11

1

1

5% 2 NP0-C0G-CERM 01005

2

25V

ROOM=SOC

37

C4702

D

I2C_TOUCH_TO_MAMBA_SCL I2C_TOUCH_BI_MAMBA_SDA

MAKE_BASE=TRUE

NOSTUFF

C4709

I2C0_AP_SCL I2C0_AP_SDA

1

5% 25V 2 NP0-C0G-CERM 01005

23

56PF

ROOM=MAMBA_MESA

C4711 1

37

1

PP1V8

25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 30 29

1% 1/32W MF 01005 ROOM=SOC 2

1% 1/32W MF 01005 2 ROOM=SOC

I2C1_AP_SCL I2C1_AP_SDA

MAKE_BASE=TRUE MAKE_BASE=TRUE

NOSTUFF

C4703

1

5% 2 NP0-C0G-CERM 01005 25V

46

HOMER

D11/111 ONLY

1

I2C1_AP_SCL I2C1_AP_SDA

56PF 2

ROOM=PMU

5% 25V NP0-C0G-CERM 01005

20

1

20

1

R4713 1.00K

R4714

5% 1/32W MF 01005 ROOM=SOC 2

I2C_HOMER_SCL I2C_HOMER_SDA

I2C1_AP_SCL I2C1_AP_SDA

PP1V8

1 R4705 2.2K

11

I2C2_AP_SCL I2C2_AP_SDA

2

ROOM=SOC

R4716 2.2K

5% 1/32W MF 010052

ROOM=SOC

I2C5_SCL I2C5_SDA

36 41 36 41

11 11

21 21

1 R4706 2.2K 5% 1/32W MF 01005

C

1

ROOM=HOMER

I2C2

11

R4715 2.2K

5% 1/32W MF 2 01005

ROOM=HOMER

ROOM=SOC

1

1.00K

5% 1/32W MF 2 01005

ROOM=PMU

PP1V8

25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 30 29

PP1V8_SDRAM

46 41 40 37 36 32 21 20 18 16 53 52 48

C4704

I2C5

46

NOSTUFF

56PF

5% 1/32W MF 01005

ROOM=DISPLAY_B2B

4.02K

I2C1_AP_SCL 11 I2C1_AP_SDA

25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 30 29

C4712

5% 2 25V NP0-C0G-CERM 01005

ROOM=DISPLAY_B2B

11

#24544426

45

56PF

5% 2 NP0-C0G-CERM 01005 25V

4.02K

TO DISPLAY / TOUCH FLEX 45

20 37

56PF

R4704 1

5% 25V NP0-C0G-CERM 01005

2

I2C_TOUCH_TO_MAMBA_SCL I2C_TOUCH_BI_MAMBA_SDA

I2C1 R4703 1

38

40

ROOM=SOC

I2C0_AP_SCL I2C0_AP_SDA

TO MAMBA / MESA FLEX

C4710

1

ROOM=MAMBA_MESA

40

38

NOSTUFF

56PF

23

56PF

5% 25V NP0-C0G-CERM 01005

I2C_TOUCH_TO_MAMBA_SCL I2C_TOUCH_BI_MAMBA_SDA

MAKE_BASE=TRUE

37

I2C0_AP_SCL I2C0_AP_SDA

NOSTUFF

56PF

C

1

TOUCH

25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 30 29

11

2

I2C3 25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 30 29

PP1V8

2

I2C2_AP_SCL I2C2_AP_SDA

MAKE_BASE=TRUE MAKE_BASE=TRUE

1 R4709 2.2K

33

5% 1/32W MF 01005

33

ROOM=FOREHEAD

R4707

ROOM=SOC

0.00

1 0% 1/32W

I2C_ALS_CONVOY_SCL_CONN

2 MF 01005

45 11

2

1 R4710 2.2K 5% 1/32W MF 01005

ROOM=SOC

ROOM=DOCK

2

FL4730

150OHM-25%-200MA-0.7DCR 2

I2C3_AP_SCL

ckplus_waive=I2C_PULLUP

I2C_MIC1_SCL_CONN

1

41

01005

R4708 0.00

1 0% 1/32W

B

2 MF 01005

ROOM=FOREHEAD

I2C_ALS_CONVOY_SDA_CONN

C4707 56PF

1

5% 25V 2 NP0-C0G-CERM 01005 ROOM=FOREHEAD

1

C4708

TO FOREHEAD FLEX

TO DOCK FLEX

FL4729

45 11

I2C3_AP_SDA

2

100

CKPLUS_WAIVE=I2C_PULLUP

I2C_MIC1_SDA_CONN

1

5% 1/32W MF 01005

56PF

5% 2 25V NP0-C0G-CERM 01005

C4730

1

1

56PF

ROOM=DOCK

C4729 56PF

5% 25V NP0-C0G-CERM 2 01005

ROOM=FOREHEAD

B 41

5% 2 25V NP0-C0G-CERM 01005

ROOM=DOCK_B2B

ROOM=DOCK_B2B

ROOM=RIGHT_BUTTON

FL4732

150OHM-25%-200MA-0.7DCR 2

I2C_MIC2_SCL_CONN

1

45

CKPLUS_WAIVE=I2C_PULLUP

01005

FL4731

TO COMBINED BUTTON FLEX

150OHM-25%-200MA-0.7DCR 2

I2C_MIC2_SDA_CONN

1

45

CKPLUS_WAIVE=I2C_PULLUP

01005 ROOM=RIGHT_BUTTON

C4732

1

1

56PF

C4731 56PF

5% 2 25V NP0-C0G-CERM 01005

5% 25V 2 NP0-C0G-CERM 01005 ROOM=RIGHT_BUTTON

ROOM=RIGHT_BUTTON

FL4742

150OHM-25%-200MA-0.7DCR

A

2

1

I2C_DISP_EEPROM_SCL_CONN

45 SYNC_MASTER=Sync

01005

PAGE TITLE

ROOM=DISPLAY_B2B

FL4741

I2C MAP: AP, TOUCH, HOMER, I2C5

TO DISPLAY FLEX

150OHM-25%-200MA-0.7DCR 2

SYNC_DATE=06/17/2016

DRAWING NUMBER

1

I2C_DISP_EEPROM_SDA_CONN

Apple Inc.

45

01005 ROOM=DISPLAY_B2B

051-00482 REVISION

8.0.0

R

1

C4742 56PF

2

5% 25V NP0-C0G-CERM 01005 ROOM=DISPLAY_B2B

1

C4741 56PF

5% NP0-C0G-CERM 01005

2 25V

ROOM=DISPLAY_B2B

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

47 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

47 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

46 41 40 37 36 32 21 20 18 16 53 52 48 47

46 41 40 37 36 32 21 20 18 16 53 52 48 47

1

1

R4801 2.2K 5% 1/32W MF 01005

5

4

3

PP1V8_SDRAM

PP1V8_SDRAM

2

D

6

0.1UF 1

2

20% 6.3V X5R-CERM 01005

2

R4802 2.2K

ROOM=SOC

5% 1/32W MF 01005

2

#24544699: Support 1MHz

U4802

PP1V8

25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 30 29

1

MAX20312 WLP

13

I2C_AOP_SCL

MAKE_BASE=TRUE

A2 IOVCC1 ROOM=SOC

13

I2C_AOP_SDA

MAKE_BASE=TRUE

B2 IOVCC2

#24550735: ISP I2C0 PU 1

R4808 1.00K

A1 GND

9 9

R4809

5% 1/32W MF 2 01005

ROOM=SOC

I2C_ISP_UT_SCL I2C_ISP_UT_SDA

MAKE_BASE=TRUE

0.00

1

I2C_UT_SCL_CONN

2

0% 1/32W MF 01005

1

ROOM=RCAM_B2B 35

I2C2

TO FCAM FLEX

FL4815

150OHM-25%-200MA-0.7DCR

I2C_PROX_SCL_CONN

1

1

R4815

#24958320:Intentional R4815 Change Reduce undershoot when Prox Driving

2

33.2

I2C_PROX_SDA_CONN

1

45

2

CKPLUS_WAIVE=I2C_PULLUP

1% 1/32W MF 01005

1

1

C4803 56PF

5% 25V 2 NP0-C0G-CERM 01005

ROOM=FOREHEAD

Intentional R4815 Change

ROOM=FOREHEAD

9

C4804 56PF

9

5% 2 25V NP0-C0G-CERM 01005

I2C_UT_SDA_CONN

2

1

ROOM=RCAM_B2B

45

R4810 2.2K 5% 1/32W MF 01005

ROOM=SOC

1

2

R4811 2.2K

45

CKPLUS_WAIVE=I2C_PULLUP

C4816 56PF

5% 25V 2 NP0-C0G-CERM 01005 ROOM=RCAM_B2B

5% 1/32W MF 01005

I2C_ISP_NH_SCL I2C_ISP_NH_SDA

C4817 ROOM=RCAM_B2B

0% 1/32W MF 01005

PP1V8

CKPLUS_WAIVE=I2C_PULLUP

01005

C

1

25 18 17 16 13 12 11 9 8 7 5 52 48 47 46 39 30 29

45

56PF

R4817 0.00

35

ROOM=FOREHEAD

26

CKPLUS_WAIVE=I2C_PULLUP

34

I2C_AOP_SCL I2C_AOP_SDA

26

R4816

See page 46

34

I2C_ISP_UT_SCL I2C_ISP_UT_SDA

MAKE_BASE=TRUE

I2C1

I2C_AOP_SCL I2C_AOP_SDA

D

1.00K

5% 1/32W MF 2 01005

ROOM=SOC

2

1

ISP I2C0

C4807 VCC B1

AOP I2C

7

R4812

ROOM=SOC MAKE_BASE=TRUE

1

0.00

I2C_NH_SCL_CONN

2

45

CKPLUS_WAIVE=I2C_PULLUP

0% 1/32W MF 01005

MAKE_BASE=TRUE

5% 25V 2 NP0-C0G-CERM 01005

1

ROOM=FOREHEAD

ROOM=FOREHEAD

C4812 56PF

C

5% 2 25V NP0-C0G-CERM 01005 ROOM=FOREHEAD

38 19

PP1V8_SDRAM

16 18 20 21 32 36 37 40 41 46 47 48 52 53

PP1V8_MESA 1

R4803

4.7K

5

U4805 6S 3 74LVC1G3157GX Y0 X2SON6 4Z Y1 1

NC

ROOM=MAMBA_MESA

I2C_AOP_SCL_ISO

GND

R4804 ROOM=MAMBA_MESA

ROOM=FOREHEAD

R4806 0% MF

0.00

I2C_MESA_TURTLE_SCL_CONN

1/32W 01005

1% 1/32W MF 2 01005

CKPLUS_WAIVE=I2C_PULLUP

5% 25V 2 NP0-C0G-CERM 01005

38

C4809 56PF

PP1V8_SDRAM

511K

C4813 56PF

ROOM=MAMBA_MESA

1

R4805

1

45

ROOM=FOREHEAD

1

AOP_TO_MESA_I2C_ISO_EN 1

I2C_NH_SDA_CONN

2

0% 1/32W MF 01005

4.7K

2

2 13

1

1% 1/32W MF 2 01005

1% 1/32W MF 2 01005

VCC

R4813 0.00

1

5% NP0-C0G-CERM 01005

16 18 20 21 32 36 37 40 41 46 47 48 52 53

2 25V

5

TO MAMBA/MESA FLEX

ROOM=MAMBA_MESA

VCC

U4806 6S 3 74LVC1G3157GX Y0 X2SON6 4Z Y1 1 GND

R4807

NC

I2C_AOP_SDA_ISO

2 0% MF

2

0.00

I2C_MESA_TURTLE_SDA_CONN

1

1/32W 01005

38

ROOM=MAMBA_MESA

1

C4810 56PF

2

B

5% 25V NP0-C0G-CERM 01005

B

ROOM=MAMBA_MESA

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

I2C MAP AOP DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

48 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

48 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=Sync

SYNC_DATE=06/06/2016

PAGE TITLE

I2C TABLE DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

49 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

49 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

spare

spare

8

7

6

5

4

3

2

1

This page controls elements different accross all MLBs

PCIe Lanes PP801 P2MM-NSM SM

ROOM=SOC

PP

1

D

90_AP_PCIE3_RXD_C_P 90_AP_PCIE3_RXD_C_N

D 8 52 8 52

PP802 P2MM-NSM SM

ROOM=SOC

PP

1

2 0.1UF 90_PCIE_BB_TO_AP_RXD_P 6.3V GND_VOID=TRUE X5R-CERM 01005

53

MAKE_BASE=TRUE

2 0.1UF 90_PCIE_BB_TO_AP_RXD_N 6.3V GND_VOID=TRUE X5R-CERM 01005

53

MAKE_BASE=TRUE

2 0.1UF 90_PCIE_AP_TO_BB_TXD_P 6.3V GND_VOID=TRUE X5R-CERM 01005

53

MAKE_BASE=TRUE

90_PCIE_AP_TO_BB_TXD_N

53

MAKE_BASE=TRUE

90_PCIE_WLAN_TO_AP_RXD_P

53

MAKE_BASE=TRUE

8

90_AP_PCIE2_RXD_C_P

1 C0816 20% ROOM=SOC

8

90_AP_PCIE2_RXD_C_N

1 C0817 ROOM=SOC 20%

C 8

90_AP_PCIE2_TXD_C_P

1 C0815 ROOM=SOC 20%

8

90_AP_PCIE2_TXD_C_N

1 C0818 20% ROOM=SOC

52 8

90_AP_PCIE3_RXD_C_P

2 6.3V X5R-CERM 01005

1 C0811 ROOM=SOC 20%

2 6.3V X5R-CERM 01005

0.1UF

C

GND_VOID=TRUE

0.1UF

GND_VOID=TRUE

25 18 17 16 13 12 11 9 8 7 5 48 47 46 39 30 29 52 8

8

B

8

8 8 8 8 8 8 8 8

90_AP_PCIE3_RXD_C_N

90_AP_PCIE3_TXD_C_P

90_AP_PCIE3_TXD_C_N

90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N PCIE_AP_TO_WLAN_RESET_L PCIE_AP_TO_BB_RESET_L PCIE_WLAN_BI_AP_CLKREQ_L PCIE_BB_BI_AP_CLKREQ_L

1 C0812 ROOM=SOC 20%

2 0.1UF 90_PCIE_WLAN_TO_AP_RXD_N 6.3V GND_VOID=TRUE X5R-CERM 01005

1 C0814 20% ROOM=SOC

2 0.1UF 90_PCIE_AP_TO_WLAN_TXD_P 6.3V GND_VOID=TRUE X5R-CERM 01005

1 C0813 ROOM=SOC 20%

2 6.3V X5R-CERM 01005

0.1UF

90_PCIE_AP_TO_WLAN_TXD_N

53

PP1V8 1

MAKE_BASE=TRUE

R0807 100K

53

5% 1/32W MF 2 01005 ROOM=SOC

MAKE_BASE=TRUE 53 52

53

MAKE_BASE=TRUE

53

MAKE_BASE=TRUE

53

MAKE_BASE=TRUE

53

MAKE_BASE=TRUE

53

MAKE_BASE=TRUE

53

MAKE_BASE=TRUE

53

MAKE_BASE=TRUE

52 53

MAKE_BASE=TRUE

52 53

MAKE_BASE=TRUE

PCIE_WLAN_BI_AP_CLKREQ_L

B

GND_VOID=TRUE

90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N PCIE_AP_TO_WLAN_RESET_L PCIE_AP_TO_BB_RESET_L PCIE_WLAN_BI_AP_CLKREQ_L PCIE_BB_BI_AP_CLKREQ_L

46 41 40 37 36 32 21 20 18 16 53 48 47

PP1V8_SDRAM

R52061 100K

1% 1/32W MF 01005 2 ROOM=RADIO_BB 53 52

#24556007:Parallel to 100kohm R5906_RF(nostuff)

PCIE_BB_BI_AP_CLKREQ_L

A

SYNC_MASTER=david-copy

SYNC_DATE=03/01/2016

PAGE TITLE

MLB UNIQUE DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

52 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

52 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8 77 27 26 25 40 39 37 46 41 40 37 68 60

60 23 35 36 58

7 57 21 34 32 55

55 19 33 21 53

53 18 31 20 52

46 10 30 18 48

41 9 4 28 16 47

60 20

PP_VDD_MAIN PP1V8_SDRAM

6 PP_VDD_MAIN

I32

5

Wifi/BT

PP1V8_SDRAM

4

3

Cellular

77 60 57 55 53 46 41 27 26 25 23 21 19 18 10 9 4 40 39 37 35 34 33 31 30 28 46 41 40 37 36 32 21 20 18 16 68 60 58 55 53 52 48 47

PMUGPIO_TO_WLAN_CLK32K

PMU_TO_WLAN_32K

PMU_TO_WLAN_REG_ON PMU_TO_BT_REG_ON BT_TO_PMU_HOST_WAKE AP_TO_BT_WAKE

PMU_TO_WLAN_REG_ON

65 20

PMU_TO_BT_REG_ON

65 20

BT_TO_PMU_HOST_WAKE

69 20

90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_WLAN_TXD_P 90_PCIE_AP_TO_WLAN_TXD_N 90_PCIE_WLAN_TO_AP_RXD_P 90_PCIE_WLAN_TO_AP_RXD_N PCIE_AP_TO_WLAN_RESET_L PCIE_WLAN_BI_AP_CLKREQ_L WLAN_TO_PMU_HOST_WAKE AP_TO_WLAN_DEVICE_WAKE

100_PCIE_AP_TO_WLAN_REFCLK_P

65 38 37 32 30 25 23 19 60 20 60 20 60 20 60 12

60 52 60 52

D

60 52 60 52 60 52 60 52 60 52 60 52 60 20 60 12

60 12 60 12 60 12

60 12 60 12 60 12

Opposite polarity on Karoo -->

64 12

100_PCIE_AP_TO_WLAN_REFCLK_N

64 20

100_PCIE_AP_TO_WLAN_TX_P

64 12

60 13

PP_VDD_BOOST BBPMU_TO_PMU_AMUX1 BBPMU_TO_PMU_AMUX2 BBPMU_TO_PMU_AMUX3

PP_VDD_BOOST_RF

PP1V8_SDRAM

BBPMU_TO_PMU_AMUX1 BBPMU_TO_PMU_AMUX2 BBPMU_TO_PMU_AMUX3

AP_TO_BBPMU_RADIO_ON_L PMU_TO_BBPMU_RESET_L AP_TO_BB_RESET_L

AP_TO_BBPMU_RADIO_ON_L

AP_TO_BB_RESET_L BB_TO_AP_RESET_ACT_L

100_PCIE_WLAN_TO_AP_RX_P

68 12

100_PCIE_WLAN_TO_AP_RX_N

68 46 37 26

WIFI_MLB

PCIE_AP_TO_WLAN_PERST_L

68 12

PCIE_AP_BI_WLAN_CLKREQ_L

68 12

PCIE_WLAN_TO_PMU_WAKE

68 12

AP_TO_WLAN_DEV_WAKE

UART_AP_TO_WLAN_TXD UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_RTS_L UART_WLAN_TO_AP_CTS_L

64 39 23 20 13

BB_TO_AP_RESET_DETECT_L BB_TO_STROBE_DRIVER_GSM_BURST_IND AP_TO_BB_MESA_ON AP_TO_BB_TIME_MARK AP_TO_BB_COREDUMP LCM_TO_MANY_BSYNC AP_TO_BB_IPC_GPIO1

BB_TO_AP_RESET_DETECT_L

AP_TO_BB_GYRO_FORCE_PWM AP_TO_BB_TIME_MARK AP_TO_BB_COREDUMP_TRIG TOUCH_TO_BBPMU_FORCE_PWM AP_TO_BB_MESA_ON AP_TO_BB_IPC_GPIO2

UART_WLAN_TO_AP_RXD 67 52

UART_AP_TO_WLAN_RTS_L

67 52

UART_WLAN_TO_AP_CTS_L

67 52

UART_AP_TO_BT_TXD

67 52

UART_BT_TO_AP_RXD

67 52

UART_AP_TO_BT_RTS_L

68 52

UART_BT_TO_AP_CTS_L

AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_B

RADIO_MLB

BB_TO_AP_GSM_TXBURST

UART_AP_TO_WLAN_TXD

UART_AP_TO_BT_TXD UART_BT_TO_AP_RXD UART_AP_TO_BT_RTS_L UART_BT_TO_AP_CTS_L

D

PMU_TO_BBPMU_RESET_L

100_PCIE_AP_TO_WLAN_TX_N

68 52

60 13

PP_VDD_MAIN

1

NC

67 52

60 12

PP_VDD_MAIN PP1V8_SDRAM

AP_TO_BT_WAKE

68 12 60 12

2

68 20

AOP_TO_WLAN_CONTEXT_A

90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N 90_PCIE_AP_TO_BB_TXD_P 90_PCIE_AP_TO_BB_TXD_N 90_PCIE_BB_TO_AP_RXD_P 90_PCIE_BB_TO_AP_RXD_N PCIE_AP_TO_BB_RESET_L PCIE_BB_BI_AP_CLKREQ_L BB_TO_PMU_PCIE_HOST_WAKE_L

100_PCIE_AP_TO_BB_REFCLK_P 100_PCIE_AP_TO_BB_REFCLK_N 100_PCIE_AP_TO_BB_TX_P 100_PCIE_AP_TO_BB_TX_N 100_PCIE_BB_TO_AP_RX_P 100_PCIE_BB_TO_AP_RX_N PCIE_AP_TO_BB_PERST_L PCIE_AP_BI_BB_CLKREQ_L PCIE_BB_TO_PMU_WAKE_L

AOP_TO_WLAN_CONTEXT_B UART_AP_TO_BB_TXD

60 11 60 11 60 11 60 11

C 68 60 53 68 60 53

I2S_AP_TO_BT_BCLK I2S_AP_TO_BT_LRCLK I2S_BT_TO_AP_DIN I2S_AP_TO_BT_DOUT

I2S_AP_TO_BT_BCLK

UART_BB_TO_AP_RXD

I2S_AP_TO_BT_LRCK 68 13

I2S_BT_TO_AP_DIN

68 13

I2S_AP_TO_BT_DOUT

61 57 53 61 57 53 60 57 53 60 57 53 61 58 53

UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX

UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX

50_UAT_WLAN_5G_WEST 50_UAT_WLAN_2G_EAST 50_UAT_WLAN_5G_EAST 50_WLAN_G_1 50_WLAN_A_1 50_UAT2_M

68 11

50_UAT_WLAN_5G_WEST 50_UAT_WLAN_2G_EAST

68 11 68 11

50_UAT_WLAN_5G_EAST 68 60 53

50_WLAN_G_1

68 60 53

50_WLAN_A_1

64 55 53

FF SPECIFIC

78 55 53

I16

12

AP_TO_ICEFALL_FW_DWLD_REQ

RADIO_MLB_FF 60 57 53 60 57 53 61 57 53 61 57 53 61 57 53 61 58 53

50_WLAN_A_1 50_WLAN_G_1 50_UAT_WLAN_5G_EAST 50_UAT_WLAN_2G_EAST 50_UAT_WLAN_5G_WEST 50_UAT2_M

50_WLAN_G_1

50_UUAT_LB_MLB_NORTH

50_UAT_WLAN_5G_EAST

50_UAT_MB_HB_SOUTH

50_UAT_WLAN_2G_EAST

50_UAT_LB_MLB_SOUTH

50_UAT_WLAN_5G_WEST

50_UAT1_WEST

50_UAT2_M

50_UAT1_TUNER

VDD_TUNER_RFFE_VIO_1V8 UAT_TUNER_RFFE_CLK 77 60 57 55 53 46 27 26 25 23 21 19 18 10 9 4 41 40 39 37 35 34 33 31 30 28

PP_VDD_MAIN

UAT_TUNER_RFFE_DATA

PP_VDD_MAIN

BUFFER_GPO1

BB_TO_LAT_ANT_SCLK BB_TO_LAT_ANT_SDATA

P2MM-NSM SM

ROOM=UAT_DEBUG

P2MM-NSM SM

ROOM=UAT_DEBUG

P2MM-NSM SM

NFC PP_VDD_MAIN PP1V8_SDRAM

ROOM=UAT_DEBUG

P2MM-NSM SM

ROOM=UAT_DEBUG

78 55 53 78 78 55 53

50_UAT_WLAN_2G_WEST_PLEXER

50_WLAN_A_1

PP3V0_TRISTAR_ARC_PROX

PP5304

PP

PP5301

PP

PP5302

PP

PP5303

PP

50_UAT_WLAN_2G_WEST_PLEXER 50_UUAT_LB_MLB_NORTH 50_UAT_MB_HB_SOUTH 50_UAT_LB_MLB_SOUTH 50_UAT1_WEST 50_UAT1_TUNER

53 57 76

81 55 53

53 57 75

64 55 53 64 55 53 55 12 55 12 55 20

I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_LRCLK I2S_AP_TO_BB_DOUT I2S_BB_TO_AP_DIN

I2S_AP_TO_BB_BCLK

UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX

UART_BB_TO_WLAN_COEX

NFC_SWP NFC_TO_BB_CLK_REQ BB_TO_NFC_CLK NFC_SWP_MUX SE2_READY AP_TO_ICEFALL_FW_DWLD_REQ SE2_PWR_REQ SE2_PRESENT ICEFALL_LDO_ENABLE

NFC_SWP

I33 ieee ieee.std_logic_1164.all work.all TRUE

I2S_AP_TO_BB_LRCLK I2S_AP_TO_BB_DOUT I2S_BB_TO_AP_DIN

UART_WLAN_TO_BB_COEX

78 55 53

53 57 75

67 36 17 13

53 58 76

67 13

19 29 40 41 58 67 40 16 18 20 21 32 36 37 40 41 46 47 48 52 53 55 58 60 68 53 58 68

BB_TO_LAT_ANT_SCLK BB_TO_LAT_ANT_DATA

67 40

75 57 53

75 57 53

50_UAT1_WEST

76 57 53

53 58 68

73 57 53

41 53 58 68 41 53 58 68

73 57 53

1 1

68 58 53

1

68 58 53 76 58 53

1

68 58 53

I10

SE2_READY AP_TO_ICEFALL_FW_DWLD

MAKE_BASE=TRUE

SE2_PWR_REQ SE2_PRESENT ICEFALL_LDO_ENABLE

BB_TO_UAT_SCLK BB_TO_UAT_DATA 50_UAT1_TUNER BUFFER_GPO1

68 58 53 41

PP1V8_SDRAM

68 41

PMU_TO_NFC_EN

68 46

BB_TO_NFC_CLK

BB_TO_LAT_ANT_SCLK BB_TO_LAT_ANT_DATA BB_TO_LAT_GPO1 BB_TO_LAT_GPO2 BB_TO_LAT_GPO3

SWD_AP_TO_BB_CLK SWD_AP_BI_BB_IO USB_BB_VBUS 90_USB_BB_P 90_USB_BB_N

B

50_UAT_WLAN_2G_WEST_PLEXER 50_UAT_LB_MLB_SOUTH 50_UAT_MB_HB_SOUTH 50_UUAT_LB_MLB_NORTH 50_UAT1_WEST

MAKE_BASE=TRUE

UAT_RFFE_CLK

MAKE_BASE=TRUE

UAT_RFFE_DATA

Per JimYang 3/17, D11 only, NC BUFFER_GPO2

PP_VDD_MAIN

50_UAT1_TUNER BUFFER_GPO1

NC

BUFFER_GPO2

LAT_RFFE_CLK LAT_RFFE_DATA

RFFE_GPO1 RFFE_GPO2 RFFE_GPO3

PMU_TO_GNSS_EN

NFC_TO_BB_CLK_REQ

UART_AP_TO_GNSS_TXD

AP_TO_NFC_FW_DWLD AP_TO_NFC_DEV_WAKE

NFC_SWP_MUX

SWD_AP_TO_MANY_SWCLK SWD_AOP_BI_BB_SWDIO PMU_TO_BB_USB_VBUS_DETECT 90_USB_BB_DATA_P 90_USB_BB_DATA_N 50_UAT_WLAN_2G_WEST_PLEXER 50_UAT_LB_MLB_SOUTH 50_UAT_MB_HB_SOUTH 50_UUAT_LB_MLB_NORTH

53 58 68

68 58 53 41

PMU_TO_NFC_EN BB_TO_NFC_CLK NFC_TO_BB_CLK_REQ AP_TO_NFC_FW_DWLD_REQ AP_TO_NFC_DEV_WAKE NFC_TO_PMU_HOST_WAKE

BB_TO_NFC_CLK

53 57 73

64 20

PP3V0_TRISTAR_ANT_PROX PP1V8_SDRAM BB_TO_UAT_SCLK BB_TO_UAT_DATA BUFFER_GPO1

NFC_TO_BB_CLKREQ

53 57 73

68 41

55 20

C

50_UAT2_M

64 55 53

77 60 57 55 53 46 41 27 26 25 23 21 19 18 10 9 4 40 39 37 35 34 33 31 30 28 46 41 40 37 36 32 21 20 18 16 68 60 58 55 53 52 48 47

UART_BB_TO_AOP_RXD

UART_GNSS_TO_AOP_RXD

81 55 53

B

UART_AOP_TO_BB_TXD

UART_AOP_TO_GNSS_TXD

68 11 61 57 53

UART_AOP_TO_BB_TXD UART_BB_TO_AOP_RXD

STOCKHOLM_MLB

UART_GNSS_TO_AP_RXD UART_AP_TO_GNSS_RTS_L

NFC_TO_PMU_HOST_WAKE

UART_GNSS_TO_AP_CTS_L 55 12 55 12

A

55 12 55 12

81 55 53 78 55 53 78 55 53 81 55 53

78 55 53 78 55 53

UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_CTS_L

UART_AP_TO_NFC_TXD

GNSS_TO_PMU_HOST_WAKE

UART_NFC_TO_AP_RXD

AP_TO_GNSS_TIME_MARK

NFC_SWP SE2_READY SE2_PWR_REQ SE2_PRESENT

NFC_SWP

NFC_SWP_MUX ICEFALL_LDO_ENABLE

UART_AP_TO_NFC_RTS_L

SYNC_MASTER=david-copy

UART_NFC_TO_AP_CTS_L

SYNC_DATE=03/01/2016

PAGE TITLE

CELL,WIFI,NFC DRAWING NUMBER

SE2_READY

Apple Inc.

SE2_PWR_REQ SE2_PRESENT

051-00482 REVISION

8.0.0

R

NFC_SWP_MUX ICEFALL_LDO_ENABLE

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

53 OF 53

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

53 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2

1

REV

ECN

CK APPD

DESCRIPTION OF REVISION

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DATE

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

0006532879

ENGINEERING RELEASED

2016-07-06

D

D

STOCKHOLM_MLB JUNE 22, 2016 PP_VDD_MAIN PP1V8_SDRAM

2

C

2

IN

2

IN

PMU_TO_NFC_EN NFC_TO_PMU_HOST_WAKE AP_TO_NFC_DEV_WAKE AP_TO_NFC_FW_DWLD_REQ NFC_TO_BB_CLK_REQ BB_TO_NFC_CLK

2 OUT 2

IN

2

IN

2 OUT 2

IN

2

IN

UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_CTS_L

2 OUT 2

IN

2 OUT

2 2

NFC_SWP SE2_READY SE2_PWR_REQ SE2_PRESENT

IO IN

2

IN

2

IN

C

NFC_SWP_MUX

2 OUT

ICEFALL_LDO_ENABLE

2 OUT

ALTERNATES PART NUMBER

B

ALTERNATE FOR PART NUMBER

132S0436

REFERENCE DESIGNATOR(S)

132S0400

C7504_RF

DESCRIPTION

BOM OPTION

B

0.22UF 20% 6.3V 01005 TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION TABLE_5_ITEM

353S01007

1

ONSEMI,IC LOAD SWITCH, WLCSP4

NFCSW_RF

CRITICAL

BOM OPTIONS TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_ITEM

131S0883

1

220PF, 0201 2% 50V

C7514_RF

D101

TABLE_5_ITEM

131S00081

1

270PF, 0201 2% 25V

C7514_RF

D111

131S00118

1

180PF, 0201 2% 50V

C7518_RF

D111

131S00033

1

680PF, 0201 2% 50V

C7516_RF

D111

131S00081

1

270PF, 0201 2% 25V

C7514_RF

D11_JP

131S0731

1

100PF, 0201 2% 50V

C7518_RF

D11_JP

131S00033

1

680PF, 0201 2% 50V

C7516_RF

D11_JP

131S00081

1

270PF, 0201 2% 25V

C7514_RF

D11_ROW

TABLE_5_ITEM

131S00055

1

22PF, 0201 2% 50V

C7512_RF

D101

TABLE_5_ITEM

TABLE_5_ITEM

131S00117

1

120PF, 0201 2% 50V

C7518_RF

D101

TABLE_5_ITEM

TABLE_5_ITEM

131S00026

1

820PF, 0201 2% 50V

C7516_RF

D101

TABLE_5_ITEM

TABLE_5_ITEM

131S0883

1

220PF, 0201 2% 50V

C7514_RF

D10_JP

TABLE_5_ITEM

TABLE_5_ITEM

131S00055

1

22PF, 0201 2% 50V

C7512_RF

D10_JP

TABLE_5_ITEM

TABLE_5_ITEM

131S00019

A

1

150PF, 0201 2% 50V

C7518_RF

D10_JP

TABLE_5_ITEM

page1

TABLE_5_ITEM

131S0825

1

560PF, 0201 2% 50V

C7516_RF

D10_JP 131S00118

1

180PF, 0201 2% 50V

C7518_RF

D11_ROW

DRAWING TITLE

TABLE_5_ITEM

131S0883

1

220PF, 0201 2% 50V

C7514_RF

A

TABLE_5_ITEM

D10_ROW

SCH,MLB,D11

TABLE_5_ITEM

131S00033

1

680PF, 0201 2% 50V

C7516_RF

D11_ROW

TABLE_5_ITEM

131S00055

1

22PF, 0201 2% 50V

C7512_RF

D10_ROW

DRAWING NUMBER

051-00482

TABLE_5_ITEM

131S00117

1

120PF, 0201 2% 50V

C7518_RF

Apple Inc.

D10_ROW TABLE_5_ITEM

131S00026

1

820PF, 0201 2% 50V

C7516_RF

REVISION

8.0.0

R

D10_ROW

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

1 OF 75

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

54 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

5

4

3

STOCKHOLM

2

5V BOOSTER 2

D

NFBST_RF WLCSP

A3 VIN

PP_VDD_MAIN_NFC 1 C7521_RF

1 C7511_RF

100PF 5% 2 16V NP0-C0G 01005 NFC

15UF 20% 2 6.3V X5R 0402-1 NFC

L7502_RF 1.8UH-0.7A 1

0603 NFC

1

2 NFC_BOOST_SW

B1 SW B2 SW

NFC_BOOST_EN

B3 EN

2

NFC CONTROLLER

FAN48614BUC50X

6

VOUT A1 VOUT A2

C3 AGND

7

C1 PGND C2 PGND

8

VDD_NFC_5V

2

1 C7517_RF

1 C7522_RF

15UF 20% 2 6.3V X5R 0402-1 NFC

100PF 5% 2 16V NP0-C0G 01005 NFC

D

NFC

VDD_NFC_5V

2

1 C7520_RF

VDD_NFC_ESE VOLTAGE=1.80V

C 2 1

OUT

1

IN

1

IN

1

OUT

1

IN

2 1

IN

2 1

OUT

2 1

IN

2 1

OUT

2 1

IN 2

NFC_TO_PMU_HOST_WAKE SE2_PRESENT AP_TO_NFC_FW_DWLD_REQ NFC_TO_BB_CLK_REQ BB_TO_NFC_CLK UART_AP_TO_NFC_TXD UART_NFC_TO_AP_RXD UART_AP_TO_NFC_RTS_L UART_NFC_TO_AP_CTS_L PMU_TO_NFC_EN

D1 A5 B2 A2 A3 C1 B1 D2 A1 E1

VDD_NFC_ESE

E3 E4 F4 B3 B4 E6

NC 1 1 1

IN OUT OUT

SE2_READY ICEFALL_LDO_ENABLE NFC_SWP_MUX

IRQ SVDD_REQ DWL CLK_REQ NFC_CLK_XTAL1 RX TX CTS RTS VEN

F1 A4

IC00 SIM_SWIO GPIO0 A7 IC01 A6 TX_PWR_REQ D5

ESE_DWPM_DBG G7 ESE_DWPS_DBG G6

SMX_RST* SMX_CLK ESE_IO1 SE2_BUSY IC2 EXT_MUX

E2 VSS

NC

2.2UF 20% 2 6.3V X5R-CERM 0201-1

NFC FRONT END C7507_RF 1000PF

1UF 20% 2 10V X5R 0201 NFC

2

1

NFC_RXP

2

1

NFC_RXP_CAP

R7508_RF 560

2

1% 1/20W MF 201 NFC

2% 25V C0G-NP0 0201 NFC L7500_RF 160NH-10%-0.48A-0.33OHM

NFC_RF PN67VEU3-B001D004 UFLGA

C3 XTAL2

0.22UF 20% 2 6.3V X5R 01005 NFC

1 C7505_RF

1 C7527_RF

2.2UF 20% 2 6.3V X5R-CERM 0201-1

2

NC NFC_SWP NFC_TEST_OUT

2

NC NFC_BOOST_EN

2

NFC_RXP NFC_RXN

TX1 G3 TX2 G5

NFC_TXP NFC_TXN

VMID

F7

SE2_ENABLE F2 SE2_SVDD_IN G1

2

0402 NFC

1

BI

1 C7509_RF

680PF 2% 2 25V C0G-NP0 0201 NFC

2 2

2

IN

2

1 2

1

NFC_TXN

2

0402 NFC

NFC_VMID SE2_PWR_REQ PP1V8_SDRAM

180 PHASE SHIFT INTRODUCED BY BALUN DONE FOR BEST ROUTING

L7501_RF 160NH-10%-0.48A-0.33OHM

2

AP_TO_NFC_DEV_WAKE

C

NFC_BALP

NC NC

RX+ F6 RX- F5

WKUP_REQ E5

1

NFC_TXP

BAL0 2 GND 1

1UF 20% 2 10V X5R 0201 NFC

1 C7504_RF

1 C7526_RF

2.2UF 20% 2 6.3V X5R-CERM 0201-1

3 BAL1 4 UNBAL

1UF 20% 2 10V X5R 0201 NFC

2

1 C7506_RF

BALUN_RF ATB161006F-20011 SM

1 C7502_RF

SVDD B7 ESE_VDD C5

1 C7500_RF

AVDD D7

0% 1/32W MF 01005 NFC

VDD_NFC_DVDD

2

OUT

1 2

IN

1 2

C7508_RF 1000PF

G4 TVSS C2 PVSS

2

VDD_NFC_AVDD VOLTAGE=1.80V

VUP G2 TVDD E7

1

VDD_NFC_AVDD

PP_VDD_MAIN_NFC

B6 DVSS C4 DVSS

2

R7502_RF 0.00

VDD_NFC_TVDD

C6 C7 B5 D3

2

PP1V8_SDRAM

VDD VBAT SIM_PMU_VCC PVDD

2 1

D4 AVSS D6 AVSS F3 AVSS

1UF 20% 2 10V X5R 0201 NFC

1 C7503_RF

2

1

NFC_RXN

0.1UF 20% 2 6.3V X5R-CERM 01005 NFC

2

NFC_BALN

2

1

R7509_RF 560

2

1% 1/20W MF 201 NFC

C7512_RF 22PF 1

TP7500_RF 1

NFC_ANT

2% 50V C0G 0201 OMIT_TABLE

680PF 2% 2 25V C0G-NP0 0201 NFC

2% 25V C0G-NP0 0201 NFC

1

NFC_ANT_MATCH

1 C7510_RF

NFC_RXN_CAP

C7514_RF 220PF

1 C7515_RF

1 C7516_RF

1 C7518_RF

1000PF 2% 2 25V C0G-NP0 0201 NFC

820PF 2% 2 25V C0G-NP0 0201 NFC OMIT_TABLE

120PF 2% 2 50V NP0-C0G 0201 OMIT_TABLE

2

2% 50V C0G-CERM 0201 OMIT

2

A

SM-TP1P25-TOP OMIT

TP7505_RF 1

NFC_TEST_OUT

A

TP-P55 NFC OMIT

B

2 1

B

SE2_PWR_REQ 1

R7599_RF 1.00K 5% 1/32W MF 2 01005

NFC LOAD SWITCH OMIT_TABLE

2 1

2 1

A

2 1

UART_AP_TO_NFC_TXD

UART_NFC_TO_AP_RXD

OMIT PP7504_RF P2MM-NSM SM 1

UART_AP_TO_NFC_RTS_L

OMIT PP7505_RF P2MM-NSM SM 1

UART_NFC_TO_AP_CTS_L

OMIT PP7506_RF P2MM-NSM SM 1

PP

PP

PP

2 1

2 1

2 1

NFC_TO_PMU_HOST_WAKE

PP7507_RF P2MM-NSM SM 1

PMU_TO_NFC_EN

OMIT PP7508_RF P2MM-NSM SM 1

AP_TO_NFC_DEV_WAKE

OMIT PP7509_RF P2MM-NSM SM 1

2 1

PP_VDD_MAIN

2 1

PP1V8_SDRAM

B2 ON

PP_VDD_MAIN_NFC

2

PP

PP

GND B1

2 1

PP7503_RF P2MM-NSM SM 1

NFCSW_RF FPF1204UCX A2 VIN WLCSP-COMBOVOUT A1

PP

OMIT 2 1

PP_VDD_MAIN

1

R7520_RF 0.00

2

PP_VDD_MAIN_NFC

2

1% 1/20W MF 0201 NOSTUFF

PP

OMIT

A PAGE TITLE

NFC DRAWING NUMBER

Apple Inc. R

051-00482 8.0.0

REVISION

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

7

6

5

4

3

2

75 OF 75 55 OF 81

SHEET

IV ALL RIGHTS RESERVED

8

SIZE

1

D

8

7

6

5

4

3

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2

1

REV

ECN

CK APPD

DESCRIPTION OF REVISION

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DATE

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

D

8

0006532879

ENGINEERING RELEASED

2016-07-06

D11 RADIO_MLB_FF FEB 05, 2016 PDF PAGE

D

CONTENTS

TABLE_TABLEOFCONTENTS_HEAD

2

METROCIRC

TABLE_TABLEOFCONTENTS_ITEM

LMBRF:

NOLMBRF: TABLE_5_HEAD

PART#

QTY

DESCRIPTION

152S2024

1

1.4NH,1.1A,0201

152S00610

1

3.6NH,2%,1.7A,0.045OHM,0402

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

L8008_RF

CRITICAL

NOLMBRF

L8009_RF

CRITICAL

NOLMBRF

TABLE_5_ITEM

152S2001

1

2.4NH,600MA,0201

L8008_RF

CRITICAL

LMBRF

152S0983

1

6.8NH,2%,1.5A,0.055OHM,0402

L8009_RF

CRITICAL

LMBRF

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

C

C

B

B

?

A

A

DRAWING TITLE

SCH,MLB,D11 DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

1 OF 3

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

56 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

8

7

6

5

4

3

2

1

METROCIRC D11 NORTH-SOUTH METROCIRC 339S00147

D

D11 EAST-WEST METROCIRC 339S00146 EAST MLB

D

WEST MLB

MCEW_RF

FLTPSSL-672E

UPPER MLB RADIO MLB

2

WIFI MLB

BI 2

METROCIRC

IN

LOWER MLB

MCNS_RF

FLTPSSL-765E 6 2 4

50_UAT1_EAST 50_LAT_WLAN_NORTH 50_UUAT_LB_MLB_NORTH

SIGNAL1-U SIGNAL2-U SIGNAL3-U

1 3 5 8 10 12 21 22 23 24 25 26 27 28 29 30 31 32

C

SM

SIGNAL1-L SIGNAL2-L SIGNAL3-L

GND

7 11 9

WIFI MLB

IO

WIFI MLB

IO

METROCIRC

50_UAT_MB_HB_SOUTH 50_LAT_WLAN_SOUTH 50_UAT_LB_MLB_SOUTH

OUT

3 1 5

50_UAT_WLAN_2G_EAST 50_UAT_WLAN_5G_EAST 50_UAT1_EAST

BI

2 4 6 8 9 12 21 22

RADIO MLB WIFI MLB

2

RADIO MLB

IO

33 34 35 36 37 38 39

SIGNAL1-E SIGNAL2-E SIGNAL3-E

SM

SIGNAL1-W SIGNAL2-W SIGNAL3-W

GND

GND

7 10 11

50_UAT_WLAN_2G_WEST 50_UAT_WLAN_5G_WEST 50_UAT1_WEST

2 IO

WIFI MLB

IO

RADIO MLB

23 24 25 26 27 28 29 30

C GND

R6711_RF 3.9PF

2

1

50_UAT_WLAN_2G_WEST

2

50_UAT_WLAN_2G_WEST_PLEXER

RADIO MLB

IO

INOUT +/-0.1PF 25V C0G-CERM 0201

INOUT

1

UP_RFFE OMIT

C6729_RF

7.5NH+/-0.3%-0.4A 0201

UP_RFFE OMIT 2

COAX

WIFI LOWER ANTENNA FEED

B

WIFI_BULK CAP IO

50_WLAN_A_1

PP_VDD_MAIN

1 1

C7610_RF 10UF

20% 2 6.3V CERM-X5R 0402-9

WLAN

1

R7700_RF 0.00 2 1

C7611_RF

C7700_RF 0.2PF +/-0.1PF

2 16V NP0-C0G

1000PF

50_WLAN_A_1_DPLX

0% 1/32W MF 01005 WLAN_RFFE OMIT

1

C7702_RF 4.3NH-3%-0.270A

01005 WLAN_RFFE NOSTUFF

10% 2 10V X5R 01005

01005 WLAN_RFFE OMIT

NOSTUFF

50_WLAN_G_1

0% 1/32W MF 01005 WLAN_RFFE OMIT

4

50_WLAN_G_1_BPF 1

IN/OUT 1

IN/OUT

1

50_WLAN_G_1_M

GND

1

L7701_RF 9.1NH-3%-0.17A-1.7OHM 01005

L7702_RF 9.1NH-3%-0.17A-1.7OHM 01005 WLAN_RFFE OMIT

2

A

2

2

6

HI

4

LO

COM 2

F-ST-SM 2

1 3 5

WLAN_RFFE

R7701_RF 0.00 2 1

50_LAT_WLAN_M 1

GND

C7701_RF 3.6PF

6 5 3 2

IO

W25DI_RF 0805

W2BPF_RF WLAN-BT-LTE L7700_RF 0.00 2 1

JLAT3_RF MM7829-2700

DPX205850DT-9173C1SJ

2

B39242B8847P810 LGA

B

C7703_RF 0.2PF +/-0.1PF

16V 2 NP0-C0G

01005 WLAN_RFFE NOSTUFF

50_WLAN_G_1_DPLX

+/-0.1PF 1 16V NP0-C0G 01005 WLAN_RFFE L7703_RF OMIT 4.0NH-+/-0.1NH-0.27A 01005 WLAN_RFFE OMIT

0% 1/32W MF 01005 WLAN_RFFE OMIT

50_LAT_WLAN_NORTH 1

2

2

50_LAT_WLAN_SOUTH

1 3

C7704_RF 0.2PF +/-0.1PF

2 16V NP0-C0G

01005 WLAN_RFFE NOSTUFF

THROUGH METROCIRC A

2 PAGE TITLE

METROCIRC [2] DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

2 OF 3

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

57 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

8

7

6

5

4

FL6701_RF 3

IO

1

BB_TO_UAT_DATA

0.00

2

0% 1/32W MF 01005

1

1 C6703_RF

7

27PF

2

27PF

0.00

2

BB_TO_UAT_SCLK

IN 3

5%

5% 2 16V NP0-C0G 01005 UAT

150OHM-25%-200MA-0.7DCR PP1V8_SDRAM

8

D

0% 1/32W MF 01005

F-ST-SM

FL6700_RF

IO

1

UAT_TUNER_RFFE_CLK_FILT

505066-0620

1 C6702_RF

1

FL6702_RF

TUNFX_RF

UAT_TUNER_RFFE_DATA_FILT

2

PLEASE CONTACT ANTENNA (MATT MOW) FOR ANY COMPONENT CHANGE.

UAT TUNER FLEX

D

3

VDD_TUNER_RFFE_VIO_1V8_FILT

01005

2

1

4

3

6

5

10

9

2 16V NP0-C0G

01005 UAT

FL6703_RF

150OHM-25%-200MA-0.7DCR

PP3V0_TRISTAR_UAT_TUNER_B2B_FILT

2PP3V0_TRISTAR_ANT_PROX

1

3

01005

UAT 1 C6701_RF

1 C6705_RF

27PF

27PF 5%

5% 2 16V NP0-C0G 01005 UAT

BB_TO_UAT_SCLK

3

1

01005 UAT

1

100PF

C

ALT UAT1 GND

BB_TO_LAT_ANT_SCLK

IN

C5904_RF

2 16V NP0-C0G

C5908_RF

33PF

5% 2 35V NP0-C0G 01005

C

L8007_RF

5% 2 16V NP0-C0G-CERM 01005

560NH-5%-2.80OHM 1

USPDT_VDD

NOSTUFF

2

PP3V0_TRISTAR_ANT_PROX IO

3

0201

BB_TO_UAT_DATA 1

C5905_RF

IN

1

1 C8001_RF

BB_TO_LAT_ANT_DATA

0.1UF

82PF

1

5% 2 6.3V NP0-C0G 01005

20% 2 6.3V X5R-CERM 01005

C5909_RF 22PF

2% 2 16V CERM 01005

C8006_RF 33PF 5%

2 16V NP0-C0G-CERM

01005

4

3

OMIT_TABLE

VDD

IN

2

3 CB

UAT_TUNER_GPO_FIL

WLCSP

RF1

0201 1

2.4NH+/-0.1NH-0.6A 1 6

USPDT_RF

1

2

DC_BLOCK 1

0201

C8008_RF 18PF

C8005_RF 33PF

2% 25V 2 C0H-CERM 0201

GNDA RFGND 5

5%

2

1

BUFFER_GPO1

L8008_RF

USPDT_RF RF1341

L8010_RF 120NH-5%-40MA

2 16V NP0-C0G-CERM

01005

AGND_RF

SP6701_RF

STDOFF-2.2OD0.25H-0.50-1.70

2.85R1.5-NSP 1

LB/MLB/GNSS/MB/HB STANDOFF

B L6708_RF

IO

1

50_UAT1_TUNER

1

0201

1

C6736_RF

L6707_RF

0.3PF

+/-0.05PF 2 25V C0G-CERM 0201

2 50_UAT1_FEED

2% 25V C0H-CERM 0201 UP_RFFE

1

1

C7731_RF

C6714_RF

+/-0.05PF 2 25V C0G 0201

03015

IO

1

UP_RFFE

UP_RFFE NO_XNET_CONNECTION

1

50_UAT2_M

2

C7730_RF

NO_XNET_CONNECTION

+/-0.05PF 2 25V CERM 0201

0402

OMIT_TABLE 2

CHASSIS_GND

50_UAT2_FEED

3

1

0201

0.6PF

2

6.8NH-1.5A-0.055OHM

SUAT2_RF STDOFF-2.56OD1.4ID.99H-SM

0.8NH-+/-0.05NH-1.1A-0.04OHM

0.8PF

18NH-3%-0.22A-0.54OHM

L8009_RF

5G WIFI STANDOFF

UP_RFFE 1

B

3

STDOFF-2.56OD1.4ID.99H-SM

18PF

50_UAT1_NOTCH

2

1

CHASSIS_GND

SUAT1_RF

C6716_RF

1.4NH+/-0.1NH-1.1A

FROM RADIO SCHEMATICS

1

ALT_GND

UP_RFFE

1

NOSTUFF

UP_RFFE

L7709_RF 1.5NH+/-0.1NH-1.0A

UP_RFFE

0201 UP_RFFE

CHASSIS_GND 3

2 1

C6734_RF 100PF

5% 2 16V NP0-C0G 01005 UP_RFFE

1

C6735_RF 18PF

5% 2 16V CERM 01005 UP_RFFE

1

C6730_RF 220PF

5% 2 6.3V CERM 01005

1

C6731_RF 56PF

5% 2 16V NP0-C0G 01005

1

C6732_RF 4.7PF

+/-0.1PF 2 16V NP0-C0G 01005-1

1

C6733_RF 220PF

5% 2 6.3V CERM 01005

A

A PAGE TITLE

UAT MATCH AND TUNER [3] DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

3 OF 3

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

58 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

8

7

6

5

4

3

2

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

1

REV

ECN

CK APPD

DESCRIPTION OF REVISION

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DATE

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

0006532879

ENGINEERING RELEASED

2016-07-06

D1X WIFI_MLB (PERENNIAL) FEBRUARY 1, 2016

D

PDF PAGE 2 3 TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

CSA PAGE 76 77

CONTENTS PERENNIAL WIFI FRONT-END

D

BOM OPTIONS:

TABLE_TABLEOFCONTENTS_ITEM

POWER

D10_JP:

D10_ROW:

D101_WIFI:

TABLE_5_HEAD

2 2

IN

PP_VDD_MAIN PP1V8_SDRAM

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

TABLE_5_ITEM

131S0648

1

CAP,CER,0.3PF,+/-0.05,01005

C7705_RF

CRITICAL

D10_JP

CLOCKS

152S00029

1

IND,1.1NH,UH-Q,01005

R7703_RF

CRITICAL

D10_JP

IN

PMUGPIO_TO_WLAN_CLK32K

131S0893

1

CAP,CER,0.2PF,+/-0.05,01005

C7706_RF

CRITICAL

D10_JP

CONTROL

117S0161

1

RES,MF,0 OHM,1/32W,01005

R7711_RF

CRITICAL

D10_JP

117S0161

1

RES,MF,0 OHM,1/32W,01005

R7702_RF

CRITICAL

D10_JP

152S1980

1

IND,1.0NH,UH-Q,01005

R7704_RF

CRITICAL

D10_JP

131S0404

1

CAP,3.9PF,+/-1.0PF,01005

R6711_RF

CRITICAL

D10_JP

152S2061

1

IND,7.5NH,UH-Q,01005

C6729_RF

CRITICAL

D10_JP

117S0161

1

RES,MF,0 OHM,1/32W,01005

R7700_RF

CRITICAL

D10_JP

152S2043

1

IND,6.2NH,UH-Q,01005

C7702_RF

CRITICAL

D10_JP

152S1998

1 TRUE

IND, 0.8NH,UH-Q,01005

L7700_RF

CRITICAL

D10_JP

152S2043

1

IND,6.2NH,UH-Q,01005

L7701_RF

CRITICAL

D10_JP

152S1853

1

IND,9.1NH,UH-Q,01005

L7702_RF

CRITICAL

D10_JP

131S0401

1

CAP,3.6PF,+/-0.1PF,01005

C7701_RF

CRITICAL

D10_JP

152S00038

1

IND,4.0NH,+/-0.1NH,UH-Q,01005

L7703_RF

CRITICAL

D10_JP

117S0161

1

RES,MF,0 OHM,1/32W,01005

R7701_RF

CRITICAL

D10_JP

1

CAP,CER,0.3PF,+/-0.05,01005

C7705_RF

CRITICAL

D10_ROW

152S00029

1

IND,1.1NH,UH-Q,01005

R7703_RF

CRITICAL

D10_ROW

131S0893

1

CAP,CER,0.2PF,+/-0.05,01005

C7706_RF

CRITICAL

D10_ROW

117S0161

TRUE 1

RES,MF,0 OHM,1/32W,01005

R7711_RF

CRITICAL

D10_ROW

117S0161

TRUE 1

RES,MF,0 OHM,1/32W,01005

R7702_RF

CRITICAL

D10_ROW

152S1988

1 TRUE

IND,2.4NH,UH-Q,01005

R7704_RF

CRITICAL

D10_ROW

117S0161

TRUE 1

RES,MF,0 OHM,1/32W,01005

R6711_RF

CRITICAL

D10_ROW

152S1853

1 TRUE

IND,9.1NH,UH-Q,01005

C6729_RF

CRITICAL

D10_ROW

117S0161

1 TRUE

RES,MF,0 OHM,1/32W,01005

R7700_RF

CRITICAL

D10_ROW

152S2043

1

IND,6.2NH,UH-Q,01005

C7702_RF

CRITICAL

D10_ROW

152S1998

1 TRUE

IND, 0.8NH,UH-Q,01005

L7700_RF

CRITICAL

D10_ROW

152S2043

1

IND,6.2NH,UH-Q,01005

L7701_RF

CRITICAL

D10_ROW

152S1853

1

IND,9.1NH,UH-Q,01005

L7702_RF

CRITICAL

D10_ROW

131S0401

1

CAP,3.6PF,+/-0.1PF,01005

C7701_RF

CRITICAL

D10_ROW

152S00038 TRUE 1

IND,4.0NH,+/-0.1NH,UH-Q,01005

L7703_RF

CRITICAL

D10_ROW

117S0161

RES,MF,0 OHM,1/32W,01005

R7701_RF

CRITICAL

D10_ROW

TABLE_5_ITEM

C

IN

2

IN

2 OUT 2

IN

PMU_TO_WLAN_REG_ON PMU_TO_BT_REG_ON BT_TO_PMU_HOST_WAKE AP_TO_BT_WAKE

2

IN

2

IN

2

IN

2

IN

2 OUT 2 OUT 2 2

IN IO

2 OUT 2

IN

90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_WLAN_TXD_P 90_PCIE_AP_TO_WLAN_TXD_N 90_PCIE_WLAN_TO_AP_RXD_P 90_PCIE_WLAN_TO_AP_RXD_N PCIE_AP_TO_WLAN_RESET_L PCIE_WLAN_BI_AP_CLKREQ_L WLAN_TO_PMU_HOST_WAKE AP_TO_WLAN_DEVICE_WAKE

WLAN UART 2 OUT 2

IN

2 OUT 2

IN

UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_TXD UART_WLAN_TO_AP_CTS_L UART_AP_TO_WLAN_RTS_L

BLUETOOTH UART 2

IN

2 OUT

B

2

IN

2 OUT

UART_AP_TO_BT_TXD UART_BT_TO_AP_RXD UART_AP_TO_BT_RTS_L UART_BT_TO_AP_CTS_L

TABLE_5_ITEM

2

IN IN

TABLE_5_ITEM

2

IN

2 OUT 2

2

IN

IN

2 OUT

IO

3

IO

3

IO

2

IO

2

IO

3

IO

CAP,CER,0.3PF,+/-0.05,01005

C7705_RF

CRITICAL

D101

152S00029

1

IND,1.1NH,UH-Q,01005

R7703_RF

CRITICAL

D101

131S0893

1

CAP,CER,0.2PF,+/-0.05,01005

C7706_RF

CRITICAL

D101

117S0161

1

RES,MF,0 OHM,1/32W,01005

R7711_RF

CRITICAL

D101

117S0161

1

RES,MF,0 OHM,1/32W,01005

R7702_RF

CRITICAL

D101

152S1988

TRUE 1

IND,2.4NH,UH-Q,01005

R7704_RF

CRITICAL

D101

131S0648

TRUE 1

CAP,CER,0.3PF,+/-0.05PF,01005

C7708_RF

CRITICAL

D101

118S0724

TRUE 1

RES,MF, 0 OHM,1/20W, 0201

R6711_RF

CRITICAL

D101

152S2054

TRUE 1

IND,9.1NH,UH-Q,0201

C6729_RF

CRITICAL

D101

117S0161

1

RES,MF,0 OHM,1/32W,01005

R7700_RF

CRITICAL

D101

152S2043

TRUE 1

IND,6.2NH,UH-Q,01005

C7702_RF

CRITICAL

D101

IND, 0.8NH,UH-Q,01005

L7700_RF

CRITICAL

D101

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

152S1998

1 TRUE

152S2043

1

IND,6.2NH,UH-Q,01005

L7701_RF

CRITICAL

D101

152S1853

1

IND,9.1NH,UH-Q,01005

L7702_RF

CRITICAL

D101

131S0401

1

CAP,3.6PF,+/-0.1PF,01005

C7701_RF

CRITICAL

D101

152S00038

1

IND,4.0NH,+/-0.1NH,UH-Q,01005

L7703_RF

CRITICAL

D101

117S0161

1

RES,MF,0 OHM,1/32W,01005

R7701_RF

CRITICAL

D101

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

1

C

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

NOSTUFF:C7729_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF C7700_RF, C7703_RF,C7704_RF

NOSTUFF:C7729_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF C7700_RF, C7703_RF,C7704_RF

D11_JP:

NOSTUFF: C7729_RF,C7711_RF,C7709_RF,C7710_RF, C7707_RF C7700_RF, C7703_RF,C7704_RF

D11_ROW:

D111_WIFI:

TRUE

TABLE_5_HEAD

TABLE_5_HEAD

PART#

TRUE QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

BOM OPTION TABLE_5_ITEM

TABLE_5_ITEM

1 152S00273 TRUE

IND,0.6NH,UH-Q,01005

R7703_RF

CRITICAL

D11_JP

TABLE_5_ITEM

152S00273

1

IND,0.6NH,UH-Q,01005

R7703_RF

CRITICAL

152S00273

1

IND,0.6NH,UH-Q,01005

R7703_RF

CRITICAL

D111

152S1976

1

IND,0.7NH,UH-Q,01005

R7711_RF

CRITICAL

D111

131S0400

1

CAP,CER,3.5PF+/-0.1,01005

R7702_RF

CRITICAL

D111

152S1986

TRUE 1

IND,FILM,2.2NH,UH-Q,01005

R7704_RF

CRITICAL

D111

118S0724

TRUE 1

RES,MF, 0 OHM,1/20W, 0201

R6711_RF

CRITICAL

D111

152S2054

TRUE 1

IND,9.1NH,UH-Q,0201

C6729_RF

CRITICAL

D111

131S0893

1

CAP,CER,0.2PF,+/-0.05PF,01005

C7705_RF

CRITICAL

D111

131S0893

TRUE 1

CAP,CER,0.2PF,+/-0.05PF,01005

C7729_RF

CRITICAL

D111

131S0648

TRUE 1 TRUE

CAP,CER,0.3PF,+/-0.05PF,01005

C7700_RF

CRITICAL

D111

152S1980

TRUE 1

IND,1.0NH,+/-0.1NH,UH-Q,01005

R7700_RF

CRITICAL

D111

131S0648

TRUE 1

CAP,CER,0.3PF,+/-0.05PF,01005

C7702_RF

CRITICAL

D111

131S0405

1 TRUE

CAP,CER,4.0PF,+/-0.1PF,01005

R7701_RF

CRITICAL

D111

152S00273

1 TRUE

IND,0.6NH,+/-1NH,UH-Q,01005

L7700_RF

CRITICAL

D111

152S1853

1

IND,9.1NH,UH-Q,01005

L7701_RF

CRITICAL

D111

152S1853

1

IND,9.1NH,UH-Q,01005

L7702_RF

CRITICAL

D111

117S0161

1

RES,MF,0 OHM,1/32W,01005

C7701_RF

CRITICAL

D111

B

D11_ROW TABLE_5_ITEM

TRUE 1

IND,0.7NH,UH-Q,01005

R7711_RF

CRITICAL

D11_JP

TABLE_5_ITEM

152S1976

1

IND,0.7NH,UH-Q,01005

R7711_RF

CRITICAL

D11_ROW TABLE_5_ITEM

AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_B

I2S_AP_TO_BT_BCLK I2S_AP_TO_BT_LRCLK I2S_BT_TO_AP_DIN I2S_AP_TO_BT_DOUT

131S0400

TRUE 1

CAP,CER,3.5PF+/-0.1,01005

R7702_RF

CRITICAL

D11_JP

TABLE_5_ITEM

131S0400

1

152S1986

TRUE 1

118S0724

TRUE 1

152S2054

TRUE 1

TABLE_5_ITEM

152S1986

1 TRUE

IND,FILM,2.2NH,UH-Q,01005

R7704_RF

CRITICAL

D11_JP

131S0648

1

CAP,CER,0.3PF,+/-0.05PF,01005

C7708_RF

CRITICAL

D11_JP TABLE_5_ITEM

131S0593

1 TRUE

CAP,3.9PF,+/-1.0PF,0201,HI-Q

R6711_RF

CRITICAL

D11_JP

CAP,CER,3.5PF+/-0.1,01005

R7702_RF

CRITICAL

D11_ROW TABLE_5_ITEM

IND,FILM,2.2NH,UH-Q,01005

R7704_RF

CRITICAL

TABLE_5_ITEM

RES,MF,0 OHM,1/20W,0201

CRITICAL

R6711_RF

CRITICAL

C6729_RF

TABLE_5_ITEM

152S2055

TRUE 1

IND,7.5NH,UH-Q,0201

C6729_RF

CRITICAL

D11_JP

TABLE_5_ITEM

131S0893

1

CAP,CER,0.2PF,+/-0.05PF,01005

CRITICAL

C7705_RF

D11_ROW TABLE_5_ITEM

TABLE_5_ITEM

131S0893

TRUE 1

CAP,CER,0.2PF,+/-0.05PF,01005

C7705_RF

CRITICAL

D11_JP

TABLE_5_ITEM

131S0893

TRUE 1

CAP,CER,0.2PF,+/-0.05PF,01005

C7729_RF

CRITICAL

D11_ROW TABLE_5_ITEM

131S0893

UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX

131S0648

TRUE 1

CAP,CER,0.2PF,+/-0.05PF,01005

C7729_RF

CRITICAL

TABLE_5_ITEM

131S0648

D11_JP

TRUE 1 TRUE

CAP,CER,0.3PF,+/-0.05PF,01005

CRITICAL

C7700_RF

D11_ROW

TABLE_5_ITEM

TABLE_5_ITEM

TRUE 1 TRUE

CAP,CER,0.3PF,+/-0.05PF,01005

C7700_RF

CRITICAL

TABLE_5_ITEM

152S1980

D11_JP

TRUE 1

IND,1.0NH,+/-0.1NH,UH-Q,01005

R7700_RF

CRITICAL

D11_ROW TABLE_5_ITEM

TABLE_5_ITEM

152S1980

TRUE 1

IND,1.0NH,+/-0.1NH,UH-Q,01005

R7700_RF

CRITICAL

D11_JP

TABLE_5_ITEM

131S0648

1 TRUE

CAP,CER,0.3PF,+/-0.05PF,01005

C7702_RF

CRITICAL

D11_ROW TABLE_5_ITEM

TABLE_5_ITEM

131S0648

TRUE 1

CAP,CER,0.3PF,+/-0.05PF,01005

C7702_RF

CRITICAL

TABLE_5_ITEM

131S0405

D11_JP

1 TRUE

CAP,CER,4.0PF,+/-0.1PF,01005

R7701_RF

CRITICAL

D11_ROW

TABLE_5_ITEM

TABLE_5_ITEM

131S0405

1 TRUE

CAP,CER,4.0PF,+/-0.1PF,01005

R7701_RF

CRITICAL

D11_JP

TABLE_5_ITEM

152S00273

1 TRUE

IND,0.6NH,+/-1NH,UH-Q,01005

L7700_RF

CRITICAL

D11_ROW

TABLE_5_ITEM

TABLE_5_ITEM

152S00273

1 TRUE

IND,0.6NH,+/-1NH,UH-Q,01005

L7700_RF

CRITICAL

TABLE_5_ITEM

152S1853

D11_JP

1

IND,9.1NH,UH-Q,01005

L7701_RF

CRITICAL

D11_ROW TABLE_5_ITEM

TABLE_5_ITEM

152S1853

1

IND,9.1NH,UH-Q,01005

L7701_RF

CRITICAL

D11_JP

TABLE_5_ITEM

152S1853

1

IND,9.1NH,UH-Q,01005

L7702_RF

CRITICAL

D11_ROW TABLE_5_ITEM

TABLE_5_ITEM

152S1853

1

IND,9.1NH,UH-Q,01005

L7702_RF

CRITICAL

TABLE_5_ITEM

117S0161

D11_JP

1

RES,MF,0 OHM,1/32W,01005

C7701_RF

CRITICAL

D11_ROW

NOSTUFF:C7706_RF, C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF C7703_RF,C7704_RF,L7703_RF

TABLE_5_ITEM

117S0161

1

RES,MF,0 OHM,1/32W,01005

C7701_RF

CRITICAL

NOSTUFF:C7706_RF, C7711_RF,C7709_RF,C7710_RF, C7707_RF C7703_RF,C7704_RF,L7703_RF

A

TABLE_5_ITEM

D11_ROW

TABLE_5_ITEM

COEX

50_UAT_WLAN_5G_WEST 50_UAT_WLAN_2G_EAST 50_UAT_WLAN_5G_EAST 50_WLAN_G_1 50_WLAN_A_1 50_UAT2_M

TABLE_5_ITEM

D11_ROW TABLE_5_ITEM

IND,9.1NH,UH-Q,0201

TABLE_5_ITEM

D11_ROW

TABLE_5_ITEM

ANTENNA 3

1

TABLE_5_ITEM

TABLE_5_ITEM

AUDIO IN

TABLE_5_ITEM

131S0648

TABLE_5_ITEM

TABLE_5_ITEM

2

BOM OPTION

TABLE_5_ITEM

TABLE_5_ITEM

152S1976

2

CRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

AOP

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

WLAN PCIE

DESCRIPTION

TABLE_5_ITEM

TABLE_5_ITEM

2

QTY

TABLE_5_ITEM

131S0648

TABLE_5_ITEM

2

TABLE_5_HEAD

PART#

D11_JP

NOSTUFF:C7706_RF, C7711_RF,C7709_RF,C7710_RF, C7707_RF, C7708_RF C7703_RF,C7704_RF,L7703_RF

WIFI_MLB SCHEMATIC

A

DRAWING TITLE

SCH,MLB,D11 DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

1 OF 77

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

59 OF 81

IV ALL RIGHTS RESERVED

2

1

SIZE

D

8

7

6

5

4

3

2

1

WIFI/BT PP1V8_SDRAM

PP_VDD_MAIN 1

C7600_RF 1 C7601_RF 27PF 0.01UF 5%

2 16V NP0-C0G

PMUGPIO_TO_WLAN_CLK32K

2 1

IN

1

IN

1

OUT

UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX

10%

8 SECI_RX 7 SECI_TX

WLAN_RF 1

2

JTAG_WLAN_SEL

R7600_RF 10K

2 1

IN

2 6.3V X5R

01005 WLAN

0402-9

PP1V8_SDRAM

C7606_RF 0.01UF 10%

2 6.3V CERM-X5R

01005 WLAN

54 LPO_IN

1

C7602_RF 10UF 20%

2 6.3V X5R

VDDIO_1P8V 15

01005 WLAN

1

1

1

C7607_RF 27PF 5%

2 16V NP0-C0G

01005 WLAN

VBAT_RF_VCC 30 VBAT_RF_VCC 31

2 1

VBAT_VCC 28 VBAT_VCC 29

D

1 4 6 18 21 24 27 32 34 36 45 46 47 48 49 50 51 53 57 58 60 65 67 68 69 70 71 72 73

PMU_TO_WLAN_REG_ON

92 WL_REG_ON

LBEE5W11GJ-943

PMU_TO_BT_REG_ON

93 BT_REG_ON

SYM 1 OF 2

BT_DEV_WAKE

55

AP_TO_BT_WAKE

BT_UART_RXD BT_UART_TXD BT_UART_CTS* BT_UART_RTS*

41 42 44 43

UART_AP_TO_BT_TXD UART_BT_TO_AP_RXD UART_AP_TO_BT_RTS_L UART_BT_TO_AP_CTS_L

BT_PCM_CLK BT_PCM_SYNC BT_PCM_OUT BT_PCM_IN

38 37 40 39

I2S_AP_TO_BT_BCLK I2S_AP_TO_BT_LRCLK I2S_BT_TO_AP_DIN I2S_AP_TO_BT_DOUT

IN

1 2

IN

1 2

LGA

5% 1/32W MF 2 01005 WLAN NOSTUFF

2 1

IN

2 2 2 2

61 64 62 2

JTAG_WLAN_SEL JTAG_WLAN_TCK JTAG_WLAN_TMS JTAG_WLAN_TRST_L

JTAG_SEL JTAG_TCK JTAG_TMS JTAG_TRST*

C 11 FAST_UART_TX 10 FAST_UART_RX

2 1

OUT

2 1

IN

UART_WLAN_TO_AP_RXD UART_AP_TO_WLAN_TXD

1

OUT

UART_WLAN_TO_AP_CTS_L

1

IN

UART_AP_TO_WLAN_RTS_L

12 FAST_UART_CTS_IN

2 1

IN

AP_TO_WLAN_DEVICE_WAKE

13 WL_DEV_WAKE

2 1

OUT

BT_TO_PMU_HOST_WAKE

56 BT_HOST_WAKE

3

BI 1

3

IO

BI 1

IO

OUT

1 2

IN

1 2

OUT

1 2

IN

1

IN

1

OUT

1

IN

1

9 FAST_UART_RTS_OUT

50_WLAN_G_0 50_WLAN_G_1

52 2G_ANT_CORE0 5 2G_ANT_CORE1

50_WLAN_A_0 50_WLAN_A_1

59 5G_ANT_CORE0 66 5G_ANT_CORE1

WL_HOST_WAKE

14

WLAN_TO_PMU_HOST_WAKE

PCIE_CLKREQ* PCIE_PERST*

17 16

PCIE_WLAN_BI_AP_CLKREQ_L PCIE_AP_TO_WLAN_RESET_L

PCIE_RDP PCIE_RDN

19 20

90_PCIE_AP_TO_WLAN_TXD_P 90_PCIE_AP_TO_WLAN_TXD_N

IN

1 2

IN

1 2

PCIE_TDP PCIE_TDN

22 23

90_PCIE_WLAN_TO_AP_RXD_P 90_PCIE_WLAN_TO_AP_RXD_N

OUT

1

OUT

1

PCIE_REFCLK_P PCIE_REFCLK_N

25 26

90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_N

CXT_A/JTAG_TDI CXT_B/JTAG_TDO

63 3

AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_B

SR_VLX

33

SR_LVX

VIN_LDO

35

VIN_LDO

B

OUT

1 2

BI

1

IN

1 2

IN

1 2

IN

1 2

IN

1 2

IN

C7604_RF 7.5UF 20% 4V CERM 0402

L7600_RF 2.2UH-20%-0.68A-0.25OHM 1

2

SR_LVX_1

1

3

0806

1

2

C7603_RF 100PF 5%

2 16V NP0-C0G

4

74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 94 95 96 97 98 99 100 101 102 103 104 105

WLAN_RF LBEE5W11GJ-943 LGA SYM 2 OF 2

GND

THRM_PAD

THRM_PAD

106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163

D

C

B

01005 WLAN

2 1

2 1

AOP_TO_WLAN_CONTEXT_A TDI

AOP_TO_WLAN_CONTEXT_B TDO

PP7600_RF P2MM-NSM OMIT SM 1

PP

2 1

PP7601_RF P2MM-NSM OMIT SM 1

PP

2 1

2 1

2 1

2 1

2

UART_WLAN_TO_AP_RXD

UART_AP_TO_WLAN_TXD

2

2 1

2 1

1

PP

2 1

PP7604_RF P2MM-NSM OMIT SM 1

PP

2 1

PP7605_RF P2MM-NSM OMIT SM 1

JTAG_WLAN_TCK

A 2

PP7603_RF P2MM-NSM OMIT SM

PP

2 1

PP7606_RF P2MM-NSM OMIT SM 1

JTAG_WLAN_TMS

JTAG_WLAN_TRST_L

AP_TO_WLAN_DEVICE_WAKE

BT_TO_PMU_HOST_WAKE

PP

2 1

PP7607_RF P2MM-NSM OMIT SM 1

PP

2

PP7608_RF P2MM-NSM OMIT SM 1

PP

2 1

PP7609_RF P2MM-NSM OMIT SM 1

PP

2 1

PMUGPIO_TO_WLAN_CLK32K

PP7610_RF P2MM-NSM OMIT SM 1

TABLE_ALT_HEAD

PP

PP7611_RF P2MM-NSM OMIT SM 1

WLAN_TO_PMU_HOST_WAKE

90_PCIE_AP_TO_WLAN_REFCLK_P

90_PCIE_AP_TO_WLAN_REFCLK_N

90_PCIE_AP_TO_WLAN_TXD_P

90_PCIE_AP_TO_WLAN_TXD_N

PCIE_AP_TO_WLAN_RESET_L

REF DES

COMMENTS:

339S00201

339S00199

ALTERNATE

WLAN_RF

ALT WIFI/BT MODULE

PP

1

PP

PP7613_RF P2MM-NSM OMIT SM 1

PP

PP7614_RF P2MM-NSM OMIT SM 1

PP

PP7615_RF P2MM-NSM OMIT SM 1

PP

2 1

PP7616_RF P2MM-NSM OMIT SM 1

PP

2 1

PP

2 1

PP7618_RF P2MM-NSM OMIT SM 1

PP

2 1

PP7619_RF P2MM-NSM OMIT SM 1

PMU_TO_BT_REG_ON

BOM OPTION

PP7612_RF P2MM-NSM OMIT SM

1

PMU_TO_WLAN_REG_ON

ALTERNATE FOR PART NUMBER

TABLE_ALT_ITEM

PP7617_RF P2MM-NSM OMIT SM

JTAG_WLAN_SEL

PART NUMBER

PP

2 1

PP7620_RF P2MM-NSM OMIT SM 1

UART_AP_TO_BT_TXD

PP

PP7621_RF P2MM-NSM OMIT SM 1

UART_BT_TO_AP_RXD

SYNC_MASTER=WIFI PAGE TITLE

PERENNIAL

PP

PP7622_RF P2MM-NSM OMIT SM 1

UART_AP_TO_BT_RTS_L

DRAWING NUMBER

Apple Inc.

PP

1

PP

PP7624_RF P2MM-NSM OMIT SM 1

AP_TO_BT_WAKE

051-00482 REVISION

8.0.0

R

PP7623_RF P2MM-NSM OMIT SM

UART_BT_TO_AP_CTS_L

SYNC_DATE=01/30/2014

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

76 OF 77

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

PP

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

60 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

WIFI UPPER ANTENNA FEEDS

D

D

OMIT_TABLE

R7704_RF

2.4NH+/-0.1NH-0.370A 2

BI

1

50_WLAN_G_0 1

2 01005

50_UAT_WLAN_2G_EAST 1

C7707_RF 0.2PF

2GHZ UAT

1

BI

C7708_RF 0.6PF +/-0.05PF

+/-0.1PF

16V 2 CERM

2 16V NP0-C0G

01005 WLAN_UP_RFFE OMIT_TABLE

01005 WLAN_UP_RFFE NOSTUFF

OMIT_TABLE 2

BI

R7703_RF 0.00 2 1

50_WLAN_A_0 1

C7705_RF 0.2PF +/-0.1PF

0% 1/32W MF 01005

50_UAT_WLAN_5G_EAST 1

BI

1

5GHZ UAT

C7706_RF 0.2PF +/-0.1PF

16V 2 NP0-C0G

2 16V NP0-C0G

01005 WLAN_UP_RFFE OMIT

01005 WLAN_UP_RFFE OMIT

C

C

JUAT2_RF MM8830-2600B

BI

50_UAT_WLAN_5G_WEST

0% 1/32W MF 1 C7729_RF 01005

0.2PF

+/-0.1PF

2 16V NP0-C0G

01005 WLAN_UP_RFFE OMIT

50_UAT_WLAN_5G_BPF

2

1

LFB185G53CGZE200 1 3

1

C7711_RF 0.2PF +/-0.1PF

2 16V NP0-C0G

01005 WLAN_UP_RFFE OMIT

OMIT_TABLE

R7702_RF 0.00 2 1

50_UAT2_BPF 1

C7709_RF 0.2PF +/-0.1PF

2 16V NP0-C0G

01005 WLAN_UP_RFFE OMIT

0% 1/32W MF 01005

50_UAT2_TEST 1

C7710_RF 0.2PF +/-0.1PF

2 16V NP0-C0G

01005 WLAN_UP_RFFE OMIT

1

2 C

R

50_UAT2_M

1

GND 3

OMIT_TABLE

R7711_RF 0.00 2 1

F-RT-SM

W5BPF_RF 5.15-5.85GHZ-1.2DB

UP_RFFE

B

B

A

A PAGE TITLE

WIFI FRONT-END [77] DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

77 OF 77

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

61 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

8

7

81

6

5

4

3

2

1

ICEFALL, SIM, DEBUG_CONN

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

REV

ECN

CK APPD

DESCRIPTION OF REVISION

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DATE

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

MAV16 RADIO_MLB

20 16 4 3

SYNC <SYNC_MASTER1> <SYNC_MASTER2> <SYNC_MASTER3> <SYNC_MASTER4> <SYNC_MASTER5>

20 7

IN

<SYNC_DATE2>

<SYNC_DATE4>

4 OUT 4 OUT

<SYNC_DATE5>

20 6

BB CONTROL 20 17 3

IN

17 3

IN

20 3

IN

17 7 OUT 17 7 OUT 7

IN

17 7

IN

17 7

IN

3

IN

7

IN

IO IN

20 17 6

IO

20 17 6

IO

AP_TO_BBPMU_RADIO_ON_L PMU_TO_BBPMU_RESET_L AP_TO_BB_RESET_L BB_TO_AP_RESET_DETECT_L BB_TO_STROBE_DRIVER_GSM_BURST_IND AP_TO_BB_IPC_GPIO1 AP_TO_BB_TIME_MARK AP_TO_BB_COREDUMP LCM_TO_MANY_BSYNC AP_TO_BB_MESA_ON

SWD_AP_TO_MANY_SWCLK SWD_AOP_BI_BB_SWDIO PMU_TO_BB_USB_VBUS_DETECT 90_USB_BB_DATA_P 90_USB_BB_DATA_N

IN

ANTENNA 15 14

50_UAT_WLAN_2G_WEST_PLEXER 50_UAT1_WEST 50_UAT_LB_MLB_SOUTH 50_UAT_MB_HB_SOUTH 50_UUAT_LB_MLB_NORTH

IO IO

12

IO

12

IO

14

IO

PCIE 17 6

IN

17 6

IN

6

IN

6

IN

6 OUT 6 7 3 7

7

22

IN IO

IN

17 7 OUT

23 24

7

IN

7

IN

7

IN

25 26

7 OUT

<SYNC_DATE27>

27

20 17 7

28

IN

20 17 7 OUT

29 30

<SYNC_DATE30>

20

IN

20 17

IN

20 17 OUT

SCH: 951-00964 BOM: 939-00826

20 17

IN

20 17

IN

17 3

IN

17 3 OUT 20 OUT 20 17

IN

90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N 90_PCIE_AP_TO_BB_TXD_P 90_PCIE_AP_TO_BB_TXD_N 90_PCIE_BB_TO_AP_RXD_P 90_PCIE_BB_TO_AP_RXD_N PCIE_AP_TO_BB_RESET_L PCIE_BB_BI_AP_CLKREQ_L BB_TO_PMU_PCIE_HOST_WAKE_L

AOP AUDIO I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_LRCLK I2S_AP_TO_BB_DOUT I2S_BB_TO_AP_DIN

WLAN UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX

NFC

NFC_SWP NFC_SWP_MUX SE2_READY AP_TO_ICEFALL_FW_DWLD_REQ SE2_PWR_REQ NFC_TO_BB_CLK_REQ BB_TO_NFC_CLK SE2_PRESENT ICEFALL_LDO_ENABLE

B

TUNER IO

15

IO

7 OUT

ALTERNATES

7 OUT

TABLE_ALT_HEAD

REF DES

C

UART_AOP_TO_BB_TXD UART_BB_TO_AOP_RXD

OUT

BOM OPTION

20 6

20 17 3

21

ALTERNATE FOR PART NUMBER

DEBUG

BBPMU_TO_PMU_AMUX1 BBPMU_TO_PMU_AMUX2 BBPMU_TO_PMU_AMUX3

4 OUT

4 20

MAKE_BASE=TRUE

AMUX

<SYNC_DATE3>

17 7 OUT

PART NUMBER

PP_VDD_BOOST

PP_VDD_BOOST PP1V8_SDRAM

IN

<SYNC_DATE1>

D

PP_VDD_MAIN

IN

DATE

20

B

2016-07-06

POWER

D

C

ENGINEERING RELEASED

AP CONNECTIONS

LAST_MODIFICATION=Wed Jun 29 12:06:01 2016 PAGE CSA CONTENTS 1 page1 62 page1 2 BOM_OMIT_TABLE 63 3 PMU: CONTROL AND CLOCKS 64 4 65 PMU: SWITCHERS AND LDOS 5 BASEBAND: POWER2 66 6 67 BASEBAND: CONTROL 7 BASEBAND GPIOS 68 8 69 TRANSCEIVER0/1: POWER 9 70 TRANSCEIVER0/1: TX PORTS 10 71 TRANSCEIVER0/1: PRX PORTS 11 RECEIVE MATCHING 72 12 LOWER ANTENNA & COUPLERS 73 13 74 DIVERSITY RECEIVE ASM'S 14 75 DIVERSITY RECEIVE LNA'S 15 76 UPPER ANTENNA FEEDS 16 77 PMU: ET MODULATOR 17 TEST POINTS & BOOT CONFIG 78 18 TDD TRANSMIT 79 19 FDD TRANSMIT 80

0006532879

OUT

COMMENTS:

IO

MAKE_BASE=TRUE BB_TO_UAT_SCLK BB_TO_UAT_DATA MAKE_BASE=TRUE

BB_TO_UAT_SCLK BB_TO_UAT_DATA

197S0593

ALTERNATE

Y5501_RF

19P2 MHZ XTAL

197S0598

197S0593

ALTERNATE

Y5501_RF

19P2 MHZ XTAL

138S00101

138S00095

ALTERNATE

ALL

TRANSITION CAP

335S00013

335S0894

ALTERNATE

EPROM_RF

IC EEPROM

353S00253

353S00321

ALTERNATE

SWPMX_RF

IC SWITCH SPDT

155S00235

155S00234

ALTERNATE

UPPDI_RF

NOLMBRF

7 14

50_UAT1_TUNER BUFFER_GPO1 BUFFER_GPO2

DOCK MAKE_BASE=TRUE BB_TO_LAT_ANT_SCLK BB_TO_LAT_ANT_DATA MAKE_BASE=TRUE

BB_TO_LAT_ANT_SCLK BB_TO_LAT_ANT_DATA

TABLE_ALT_ITEM

197S0565

7 14

7 17 7 17

TABLE_ALT_ITEM

TABLE_ALT_ITEM

7 OUT

BB_TO_LAT_GPO1

TABLE_ALT_ITEM

7 OUT

TABLE_ALT_ITEM

BB_TO_LAT_GPO2

TABLE_ALT_ITEM

7 OUT

A ALL:C5616_RF-C5618_RF,C5632_RF-C5634_RF

BB_TO_LAT_GPO3

page1

A

DRAWING TITLE

SCH,MLB,D11 DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

1 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

62 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

8

7

6

5

4

3

2

1

BOM OPTIONS: LMBRF:

NOLMBRF: TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

TABLE_5_ITEM

D

353S00723

1

MLB PAD

MLBPA_RF

CRITICAL

LMBRF

117S0002

1

MLB PAD LAT OUTPUT MATCH

R7105_RF

CRITICAL

LMBRF

152S2042

1

MLB PAD UAT OUTPUT MATCH

R7106_RF

CRITICAL

LMBRF

353S00627

1

MLB LNA

MLBLN_RF

CRITICAL

LMBRF

117S0002

1

MLB LNA OUTPUT MATCH

R6710_RF

CRITICAL

LMBRF

155S00139

1

PENTAPLEXER

PPLXR_RF

CRITICAL

LMBRF

118S0643

1

RES,MF,4.99K OHM,01005

R7506_RF

CRITICAL

LMBRF

155S00193

1

FLTR,DIPLEXER,LB-MB-HB,DPX,SHIELD,0805

UATDI_RF

CRITICAL

LMBRF

155S00158

1

FLTR,DIPLEXER,LB-MB/HB,MIRROR,0805

UPPDI_RF

CRITICAL

LMBRF

337S00284

1

IC,SECURE ELEMENT,BCM20211,WLBGA25

SE2_RF

CRITICAL

LMBRF

138S0739

1

CAP,1UF,0201

C7201_RF

CRITICAL

LMBRF

138S0739

1

CAP,1UF,0201

C7528_RF

CRITICAL

LMBRF

132S0316

1

CAP,0.1UF,01005

C7501_RF

CRITICAL

LMBRF

138S0739

1

CAP,1UF,0201

C7523_RF

CRITICAL

LMBRF

138S0739

1

CAP,1UF,0201

C7524_RF

CRITICAL

LMBRF

138S00032

1

CAP,2.2UF,0201

C7529_RF

CRITICAL

LMBRF

138S00032

1

CAP,2.2UF,0201

C7530_RF

CRITICAL

LMBRF

TABLE_5_ITEM

131S0444

1

DCS/PCS RX FILTER MATCH

R6301_RF

CRITICAL

NOLMBRF

152S2020

1

DCS/PCS RX FILTER MATCH

L6320_RF

CRITICAL

NOLMBRF

155S00149

1

DCS/PCS RX FILTER

GSMRX_RF

CRITICAL

NOLMBRF

152S2005

1

DCS/PCS RX MATCH (DCS)

L6318_RF

CRITICAL

NOLMBRF

131S0319

1

DCS/PCS RX MATCH (DCS)

C6332_RF

CRITICAL

NOLMBRF

131S0630

1

DCS/PCS RX MATCH (DCS)

C6340_RF

CRITICAL

NOLMBRF

152S2005

1

DCS/PCS RX MATCH (DCS)

L6319_RF

CRITICAL

NOLMBRF

131S0385

1

DCS/PCS RX MATCH (DCS)

C6333_RF

CRITICAL

NOLMBRF

131S0630

1

DCS/PCS RX MATCH (DCS)

C6341_RF

CRITICAL

NOLMBRF

155S00163

1

QUADPLEXER

PPLXR_RF

CRITICAL

NOLMBRF

155S00199

1

FLTR,DPX,PASS THRU,LB-MB-HB,SHLD,0805

UATDI_RF

CRITICAL

NOLMBRF

155S00234

1

FLTR,DPX,PASS THRU,LB-MB-HB,UNSHLD,0805

UPPDI_RF

CRITICAL

NOLMBRF

118S0724

1

RES,MF,0OHM,1/20W,0201

R6404_RF

CRITICAL

NOLMBRF

152S2044

1

IND,2.2NH,+/-0.1NH,600MA,0201

R7104_RF

CRITICAL

NOLMBRF

152S00157

1

1.2NH,+/-0.05NH,1.1A,UH-Q,0201

R6703_RF

CRITICAL

NOLMBRF

131S0549

1

18PF,0201,25V

R6708_RF

CRITICAL

NOLMBRF

131S0445

1

CAP,CER,12PF,5%,25V,0201,HI-Q

R6606_RF

CRITICAL

NOLMBRF

TABLE_5_ITEM

D

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

131S0217

1

CAP,100PF,01005

C7531_RF

CRITICAL

LMBRF

118S0627

1

RES,10KOHM,01005

R7512_RF

CRITICAL

LMBRF

TABLE_5_ITEM

C

C

TABLE_5_ITEM

353S00026

1

SE2LDO_RF

LDO,BGA,2X2

CRITICAL

D10 SPECIFIC:

LMBRF TABLE_5_ITEM

131S0630

1

C6345_RF

CAP,CER,NPO/COG,27PF,2%,16V,01005

CRITICAL

LMBRF TABLE_5_HEAD

PART#

TABLE_5_ITEM

131S0341

1

C6348_RF

CAP,CER,COG,3.0PF,+/-0.05,25V,0201,HI-Q

CRITICAL

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

CRITICAL

D10

CRITICAL

BOM OPTION

CRITICAL

D11

LMBRF TABLE_5_ITEM

131S0278

TABLE_5_ITEM

152S2006

1

IND,FILM,6.2NH,3%,400MA,UH-Q,0201

L6322_RF

CRITICAL

LMBRF

131S0630

1

CAP,CER,NPO/COG,27PF,2%,16V,01005

C6315_RF

CRITICAL

LMBRF

152S2006

1

IND,FILM,6.2NH,3%,400MA,UH-Q,0201

L6305_RF

CRITICAL

LMBRF

1

C7120_RF

CAP,CER,COG,1PF,+/-0.1PF,25V,0201,HI-Q

TABLE_5_ITEM

TABLE_5_ITEM

D11 SPECIFIC:

TABLE_5_ITEM

131S0341

1

C6306_RF

CAP,CER,COG,3.0PF,+/-0.05PF,25V,0201,HI-Q

CRITICAL

LMBRF TABLE_5_HEAD

PART#

TABLE_5_ITEM

131S0630

1

C6106_RF

CAP,CER,NPO/COG,27PF,2%,16V,01005

CRITICAL

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

LMBRF TABLE_5_ITEM

131S0425

TABLE_5_ITEM

152S2051

1

IND,1.3NH,1.1A,0201

R6404_RF

CRITICAL

LMBRF

152S2000

1

IND,2.0NH,600MA,0201

R7104_RF

CRITICAL

LMBRF

131S00001

1

CAP,CER,0.1PF,25V,0201

C7119_RF

CRITICAL

LMBRF

118S0724

1

RES,MF,0OHM,1/20W,0201

R6703_RF

CRITICAL

LMBRF

118S0724

1

RES,MF,0OHM,1/20W,0201

R6708_RF

CRITICAL

LMBRF

131S0363

1

CAP,CER,C0G,HQ,0.6PF,+/-0.05PF,25V,0201

C7123_RF

CRITICAL

LMBRF

152S2002

1

IND,2.7NH,+/-0.1NH,600MA,0201,UH-Q

R6605_RF

CRITICAL

LMBRF

131S0337

1

CAP,1.5PF,+/-0.05PF,25V,0201,HQ

C6610_RF

CRITICAL

LMBRF

118S0724

1

RES,MF,0OHM,1/20W,0201

R6606_RF

CRITICAL

LMBRF

131S0275

1

CAP,CER,C0G,0.3PF,+/-0.1PF,25V,0201,HQ

C6416_RF

CRITICAL

LMBRF

1

C7120_RF

CAP,CER,COG,0.5PF,+/-0.05PF,25V,0201,HI-Q

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

B

B

TABLE_5_ITEM

TABLE_5_ITEM

118S0608

1

RES,MF,1K OHM,1%,1/32W,01005

R5911_RF

CRITICAL

LMBRF

152S1356

1

IND,10NH,3%,250MA,HI-Q,0201

C6613_RF

CRITICAL

LMBRF

TABLE_5_ITEM

A

A

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

PMU: CONTROL AND CLOCKS RESET AND CONTROL: PMU

BBPMU_RF

D 20 1

HW_REV_ID

C

0.10V 0.20V 0.30V 0.40V 0.50V 0.60V 0.70V 0.80V 0.90V 1.00V 1.10V 1.20V 1.30V 1.40V 1.50V 1.60V

5 4 3

R5505 887K 422K 255K 180K 124K 102K 82.5K 63.4K 51.1K 51.1K 51.1K 50.0K 39.0K 14.7K 40.2K 6.34K

AP_TO_BB_RESET_L

17 1 20

6

IN

17 1

R5504_RF 20.0K 2 1

PS_HOLD

IN

IN

17 6

5% MF 1/32W 01005 RADIO_PMIC

OUT

17 6

BI

17 6

BI

58 75 43 63 82 25 31

AP_TO_BBPMU_RADIO_ON_L PMU_TO_BBPMU_RESET_L PMIC_RESOUT_L PS_HOLD_PMIC SPMI_CLK SPMI_DATA

CBL_PWR* PON_1 RESIN* PON_RST* PS_HOLD SPMI_CLK SPMI_DATA

SYM 1 OF 5 CONTROL

RADIO_PMIC

D

PMD9645 WLNSP

WLNSP

1% MF 1/32W 01005 RADIO_PMIC

REVISION DEV1 DEV2 DEV 2.1 DEV 3 T181 PP/P1 DEV4 P2 DEV5 EVT EVT DOE

R5501 51.1K 51.1K 51.1K 51.1K 51.1K 51.1K 51.1K 51.1K 51.1K 63.4K 82.5K 100K 100K 51.1K 200K 51.1K

IN

BBPMU_RF

PMD9645

R5502_RF 1.00K 2 1

OPT_1 OPT_2 GND BAT_ID_THERM

52 42 98 53

PCIE PERST OPTION

NC PP_VDD_MAIN

PP_VDD_MAIN

36 46 57 62

1 4 16 20

MAKE_BASE=TRUE

SYM 5 OF 5

GND GND RADIO_PMIC GND GND GND

GND 67

MPPS AND GPIOS: PMU PP_1V8_LDO7

3 4 5

REV_ID 1

R5505_RF

C

6.34K

1% 1/32W MF 2 01005

EVT ALT/CARBON

BBPMU_RF PMD9645 WLNSP

DEV6 CARRIER DVT PVT

20 17 1

IN

5

OUT

PMU_TO_BB_USB_VBUS_DETECT HW_REV1_ID VDDPX_BIAS_UIM2 NC

6

1

OUT

VREF_DAC_BIAS NC

R5501_RF 51.1K

1% 1/32W MF 2 01005

13 51 61 9 4 20 83 88

MPP_01 MPP_02 MPP_03 MPP_04 MPP_05 MPP_06 PA_THERM1 PA_THERM2

SYM 3 OF 5 GPIO_MPP

RADIO_PMIC

GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06

26 15 21 37 32 38

NC

NFC_TO_BB_CLK_REQ NC

IN

17 1

R5511_RF

PCIE_AP_TO_BB_PERST_PMU_L SIM1_REMOVAL_ALARM LCM_TO_MANY_BSYNC

1 IN

7 17

IN

1

0.00

PCIE PERST OPTION

2 PCIE_AP_TO_BB_RESET_L

IN

1 7

1% 1/20W MF 0201

PP_1V8_LDO7

XTAL AND CLOCK: PMU 1

B

1

C5501_RF 0.1UF

20% 2 6.3V X5R-CERM 01005 RADIO_PMIC

R5503_RF 100K

1% 1/32W MF 2 01005 RADIO_PMIC

XTAL_19P2M_OUT

3 3

1

C5502_RF 1000PF

B

Y5501_RF 19.2MHZ-10PPM-7PF-80OHM

XO_THERM

2.0X1.6-SM 1 3

4

XTAL_19P2M_IN

3

BBPMU_RF

2

PMD9645

RADIO_PMIC

WLNSP 17 6

10% 2 6.3V X5R-CERM 01005 RADIO_PMIC

XO_OUT_D0_EN

IN 3

3 3

XO_THERM

XTAL_19P2M_IN XTAL_19P2M_OUT

56

SYM 2 OF 5

BB_CLK_EN

CLOCK

76 41

XO_THERM GND_XOADC

55 65 71

XTAL_19M_IN XTAL_19M_OUT GND_XO_CLK

RADIO_PMIC

LN_BB_CLK 45 BB_CLK 35

50_MDM_PCIE_CLK SHIELD_MDM_19P2M_CLK

OUT

6 17

OUT

6

RF_CLK1 66 RF_CLK2 77

SHIELD_WTR_19P2M_CLK BB_TO_NFC_CLK

OUT

9

OUT

1 17

SLEEP_CLK 72

SHIELD_SLEEP_CLK_32K

OUT

6 17

GND_XO_CLK: VIA DOWN TO GND PLANE

A

SYNC_DATE=04/17/2015 PAGE TITLE

PAGE_TITLE=PMU: CONTROL AND CLOCKS DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

55 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

64 OF 81

IV ALL RIGHTS RESERVED

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

PMU: SWITCHERS AND LDOS SWITCHERS BULK CAPS 20 16 4 3 1

MAKE_BASE=TRUE PP_VDD_MAIN PP_VDD_MAIN

IN

D 1

C5620_RF 15UF 20%

2 6.3V CERM

0402 RADIO_PMIC

4 3 1 20 16

IN

1

PP_VDD_MAIN

4

D

4

L5601_RF 1UH-20%-0.054OHM-3.4A

C5621_RF 15UF

20% 6.3V 2 CERM 0402 RADIO_PMIC GND MAKE_BASE=TRUE

1

PP_VSW_S1

2

2520 RADIO_PMIC

MAKE_BASE=TRUE

PP_VDD_MAIN

PP_VDD_MAIN

2.2UH-20%-0.14OHM-1.6A 1

4

PP_VSW_S2

1

C5622_RF 15UF

BBPMU_RF PP_VDD_MAIN

4

MAKE_BASE=TRUE PP_VDD_MAIN

PP_VDD_MAIN

4

PP_VDD_MAIN

4

4

C5623_RF 15UF

PP_VDD_MAIN

4

MAKE_BASE=TRUE 4

4

GND

4

4

IN

4

4

C5624_RF 15UF

20% 2 6.3V CERM 0402 RADIO_PMIC

20 16 4 3 1

IN

8 4 4 GND

PP_VDD_MAIN

20 16 4 3 1

20% 2 6.3V CERM 0402 RADIO_PMIC

GND

14

VDD_L5_6_15

23

VDD_L7_8

89

VDD_L9

90 47

VIN_VPH1 VIN_VPH2

73

VDD_OTP

MDM_VREF_LPDDR2

78

VREF_DDR

AVDD_BYP

74 79

AVDD_BYP REF_BYP

68

GND_REF

24

VDD_XO_RF

MAKE_BASE=TRUE

0.47UF

10% 2 6.3V CERM-X5R 0201

AVDD_BYP_GND

1

C5601_RF 0.1UF

10% 2 6.3V CER-X5R 01005 RADIO_PMIC

GND_REF OMIT

2

XW5616_RF SHORT-10L-0.1MM-SM

DESENSE CAPS

1 20 16 4 3 1

IN

PP_VDD_MAIN

1

R5601_RF 0.00

0% 1/32W MF 2 01005

OMIT

2

C5635_RF

1

27PF

5% 16V NP0-C0G 01005

2% 16V CERM 01005

VREG_XO_GND

PLACE C5635 AND C5636 NEAR THE PMU

C5617_RF

PP_VSW_S5

1

VREG_XO GND_XO VREG_RF GND_RF_CLK

34 40 60 50

1

C5618_RF

BBPMU_TO_PMU_AMUX3

4 8

OUT

1.85V/1241MA

C

C5633_RF

4

1

PP_1V0_SMPS5

OUT

5

OUT

5

1.01V/1059MA

C5634_RF 25UF

20% 2 6.3V X5R 0402

GND MDM LOW VOLTAGE ANALOG MDM EBI1, DDR CORE MDM CORE MDM PCIE MDM HIGH VOLTAGE ANALOG MDM 1.8V I/O, DDR, SHARED 1.8V VOLTAGE RAIL MDM PLL MDM LOW VOLTAGE USB MEMORY MDM HIGH VOLTAGE USB UIM1

20% 2 6.3V X5R 0402

4

XO XO XO XO XO XO XO XO XO XO XO XO XO XO XO

FRONT END SUPPLY UIM2 GPS LNA RFFE VIO

SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN: SHUTDOWN:

OFF BYP OFF BYP ON BYP OFF OFF ON OFF ON OFF OFF OFF BYP

PP_1V5_LDO1 PP_1V2_LDO2 PP_0V9_LDO3 PP_0V95_LDO4 PP_1V7_LDO5 PP_1V8_LDO6 PP_1V8_LDO7 PP_1V8_LDO8 PP_1V0_LDO9 PP_3V075_LDO10 VDD_SIM1 PP_2V7_LDO12 VDD_SIM2 PP_1V8_LDO14 PP_1V8_LDO15

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

1.23V/124MA 5 1.20V/569MA 8 1.00V/610MA 5 1.00V/88MA 5 1.80V/52MA 1.80V/366MA 3 5 1.80V/15MA 5 1.80V/133MA 5 1.11V/1253MA 5 3.20V/15MA 20 5 1.80V/60MA 14 12 2.70V/62MA 13 5 1.80V/60MA 10 2.70V/5MA 7 1.80V/245MA 12 13 14 16 18 19

VREG_XO 4 VREG_XO_GND 4 VREG_RF_CLK 4 VREG_RF_CLK_GND

VREG_RF_CLK

B

4

1

C5626_RF 1UF

C5604_RF 10UF 20%

20% 2 10V X5R 0201 RADIO_PMIC

6.3V 2 CERM-X5R

0402 RADIO_PMIC

1

20% 2 10V X5R 0201 RADIO_PMIC

1 1

C5605_RF 1UF

C5609_RF 1UF

20% 10V 2 X5R 0201 RADIO_PMIC

20% 2 10V X5R 0201 RADIO_PMIC

C5627_RF 10UF

1

20% 2 6.3V CERM-X5R 0402 RADIO_PMIC

1

1

C5630_RF

20UF

1

C5610_RF 1UF

20% 2 10V X5R 0201 RADIO_PMIC

20% 2 6.3V CERM-X5R 0402

20% 10V 2 X5R 0201 RADIO_PMIC

1

C5608_RF 4.7UF

1

C5611_RF 1UF

20% 2 10V X5R 0201 RADIO_PMIC

1

C5628_RF 1UF

402 RADIO_PMIC

C5612_RF 1UF

20% 2 10V X5R 0201 RADIO_PMIC

20% 2 10V X5R 0201 RADIO_PMIC

20%

6.3V 2 X5R-CERM1

C5613_RF 1UF

VREG_RF_CLK_GND

2

XW5614_RF SHORT-10L-0.1MM-SM

XW5615_RF SHORT-10L-0.1MM-SM

1

1

C5607_RF 1UF

20% 10V 2 X5R 0201 RADIO_PMIC

OMIT

2

XO_GND

4

CORE XO SHUTDOWN: ON

2

RADIO_PMIC

1UF

4

1

20% 2 6.3V X5R 0402

GND

0806

1.16V/1951MA

25UF

20% 2 6.3V X5R 0402

1.0UH-20%-2.7A-0.056OHM

1 C5603_RF

OMIT

A

1

4

C5632_RF

HIGH VOLTAGE LDOS XO SHUTDOWN: ON

L5605_RF

1

PLACE XW CLOSE TO PMU VIA XW DOWN TO THE GND PLANE

GND

2

C5636_RF

100PF

2

VREG_L1 VREG_L2 VREG_L3 VREG_L4_16 VREG_L5 VREG_L6 VREG_L7 VREG_L8 VREG_L9 VREG_L10 VREG_L11 VREG_L12 VREG_L13 VREG_L14 VREG_L15

80 81 39 48 19 3 18 29 100 84 95 85 96 101 30

4

20% 2 10V X5R 0201 RADIO_PMIC

1 1

VREG_XO

1UF

XW5617_RF SHORT-10L-0.1MM-SM

1

1

20% 2 6.3V X5R 0402

25UF

1

1 C5602_RF

2

PP_VSW_S4

BBPMU_TO_PMU_AMUX2

25UF

20% 2 6.3V X5R 0402

2.2UH-20%-0.14OHM-1.6A

VREG_S5 87 VSW_S5 99

VDD_S5 GND_S5

BBPMU_TO_PMU_AMUX3

C5629_RF

C5616_RF

25UF

VDD_L3_4

REF_BYP

1

RADIO_PMIC

RADIO_PMIC

44

4 GND

0806

1.25V/693MA

C5631_RF

MDM MEMORY, MDM USB XO SHUTDOWN: ON

1

0806

BBPMU_TO_PMU_AMUX2

OUT

2

L5604_RF

4

PP_VDD_BOOST PP_VDD_MAIN

PP_VSW_S3

4

20% 2 6.3V CERM-X5R 0402 4

GND

1.0UH-20%-2.7A-0.056OHM

1

PP_1V225_SMPS2

20UF

25UF

VDD_L1_2_16

IN

1

VDD_S4 GND_S4 GND_S4

VREG_S4 12 VSW_S4 2

POWER

4

VDD_OTP

B

VDD_S3 GND_S3 GND_S3

VREG_S3 69 VSW_S3 59 VSW_S3 64

94 93

C5615_RF

20% 2 6.3V CERM-X5R 0402

L5603_RF

10 11 22 27

VREG_S1 VSW_S1 VSW_S1 VSW_S1

RADIO_PMIC

86

IN

6

VREG_S2 91 VSW_S2 97

GND

4

C5625_RF 15UF

VDD_S2 VDD_S2 GND_S2

SYM 4 OF 5

PP_1V225_SMPS2

IN 4

92 103 102

8 1 7

MAKE_BASE=TRUE

MAKE_BASE=TRUE PP_VDD_MAIN PP_VDD_MAIN

1

4

VDD_S1 VDD_S1 GND_S1 GND_S1 GND_S1 GND_S1

GND

PP_VDD_MAIN

4

PP_VDD_MAIN

1

1

20UF

5 16 6 17 28 33

70 49 54

PP_VDD_MAIN

4

MAKE_BASE=TRUE PP_VDD_MAIN PP_VDD_MAIN

GND

PP_VDD_MAIN

4

20 16 4 3 1

GND

4

LOW VOLTAGE LDOS XO SHUTDOWN: ON

RADIO_PMIC

WLNSP

MAKE_BASE=TRUE 4 GND

C

GND

PMD9645

20% 2 6.3V CERM 0402 RADIO_PMIC

0.90V/2685MA

C5614_RF

2 0806

20% 2 6.3V CERM 0402

1

4 5

OUT

20% 2 4V X5R 0603

L5602_RF

4

RADIO_PMIC

IN

1

BBPMU_TO_PMU_AMUX1

43UF

PP_VDD_MAIN

4 3 1 20 16

MDM MODEM XO SHUTDOWN: OFF

RF_CLK_GND

PLACE XW CLOSE TO PMU VIA XW DOWN TO THE GND PLANE

5 4

BBPMU_TO_PMU_AMUX1 MAKE_BASE=TRUE

BBPMU_TO_PMU_AMUX1

OUT

1

SYNC_DATE=04/17/2015 PAGE TITLE

4

BBPMU_TO_PMU_AMUX2 MAKE_BASE=TRUE

BBPMU_TO_PMU_AMUX2

8 4

BBPMU_TO_PMU_AMUX3 MAKE_BASE=TRUE

BBPMU_TO_PMU_AMUX3

OUT

1

OUT

1

PAGE_TITLE=PMU: SWITCHERS AND LDOS DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

56 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

65 OF 81

IV ALL RIGHTS RESERVED

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

BASEBAND: POWER BB_RF MDM9645

D 5 4

PP_1V0_SMPS5

C 5 4

PP_1V0_LDO9

B

5 4

V16 V17 F12 F13 F9 G11 G12 G16 G17 G8 G9 H15 H16 J18 J19 K15 L15 M15 M16 M17 P15 P16 R15 R16 U16 U7 U8 E19 F18 F19 G18 H10 H13 H14 H8 H9 J12 J13 J14 J15 J7 J8 K18 L17 L18 M12 M13 N12 N7 P6 P7 T12 T18 T6 U11 U12 U13 U18 U6 V18

BGA VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE

F7 BBPMU_TO_PMU_AMUX1 4 5 F8 G7 J11 K10 K11 K14 K6 K7 L10 L13 PP_1V2_LDO2 5 4 L14 L6 1 C5755_RF 1 C5729_RF L9 2.2UF 2.2UF M8 20% 20% 6.3V 2 X5R-CERM 2 6.3V M9 X5R-CERM 0201-1 0201-1 N11 RADIO_PMIC RADIO_PMIC N8 P10 P11 P14 20 17 7 6 5 4 PP_1V8_LDO6 R10 R13 20 17 7 6 5 4 PP_1V8_LDO6 R14 R8 1 C5730_RF R9 2.2UF 20% T13 2 6.3V X5R-CERM T8 0201-1 RADIO_PMIC T9

BB_RF

MDM9645

PP_1V8_LDO6

BGA SYM 7 OF 8 PWR2

1

1

C5733_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

1

1

C5736_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

1

C5734_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

1

C5739_RF 2.2UF

20% 6.3V 2 X5R-CERM 0201-1 RADIO_PMIC

1

C5737_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

C22 D22 G22 H22 L22 M22 T22 U22 W2 Y2

VDD_P1 VDD_P1 VDD_P1 VDD_P1 VDD_P1 VDD_P1 VDD_P1 VDD_P1 VDD_P1 VDD_P1

R23

VDD_P2

AA23 AB16 E2 K2 P2

VDD_P3 VDD_P3 VDD_P3 VDD_P3 VDD_P3

C5742_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

1

C5740_RF 2.2UF

20% 6.3V 2 X5R-CERM 0201-1 RADIO_PMIC

C5704_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC NOSTUFF

1

VDD_DDR_CORE_1P8 VDD_DDR_CORE_1P8 VDD_DDR_CORE_1P8 VDD_DDR_CORE_1P8

B23 E1 K23 U1

VDD_DDR_CORE_1P2 VDD_DDR_CORE_1P2 VDD_DDR_CORE_1P2 VDD_DDR_CORE_1P2 VDD_DDR_CORE_1P2

AA1 C23 D1 J23 W1

VDD_SIM1 (PP_UIM1_LDO11)

AA21

VDD_P4

4

VDD_SIM2 (PP_UIM2_LDO13)

AA15

VDD_P5

PP_1V8_LDO6

AB11 M19

VDD_P7 VDD_P7

20 17 7 6 5 4

4 4

5 4

V9 VDD_USB_HS_1P8 AA10 VDD_USB_HS_3P3

PP_1V8_LDO8 PP_3V075_LDO10

AB3 NC W3 NC AA3 NC Y5 Y6 Y7

PP_0V95_LDO4

VDD_USB_SS_0P9 VDD_USB_SS_0P9 VDD_USB_SS_1P8 VDD_PCIE_0P9 VDD_PCIE_0P9 VDD_PCIE_1P8

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC 5 4 PP_1V2_LDO2

1

20% 6.3V 2 X5R-CERM 0201-1 RADIO_PMIC

B12 B3 B15 B7 B18 B8

C5731_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

1

C5732_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

1

C5735_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

1

C5738_RF 2.2UF

20% 2 6.3V 0201-1 RADIO_PMIC

1

1

C5741_RF 0.1UF

20% 2 4V X5R 01005 RADIO_PMIC NOSTUFF

C5743_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

1

VDDPX_BIAS_UIM2

1

C5750_RF 0.1UF

20% 6.3V 2 X5R-CERM 01005 RADIO_PMIC

1

C5747_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

1

C18 C6 C7 E3

C5752_RF 2.2UF 20%

2 6.3V X5R-CERM

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

0201-1 RADIO_PMIC

4

4

C5748_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC PP_0V95_LDO4

VDD_ALWAYS_ON U14 NC VDD_PLL E13 VDD_PLL P19 VDD_QFPROM_PRG F10

C5749_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC NOSTUFF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

C5754_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

VDD_USB_HS_MX V11

C5744_RF 2.2UF

4 5

1

1

PP_1V5_LDO1

1

3

C5751_RF 2.2UF

VDD_A1 B10 VDD_A1 E10 VDD_A2 VDD_A2 VDD_A2 VDD_A2

PP_1V0_LDO9

PP_1V7_LDO5

1

1

C5746_RF 2.2UF

VDD_A3 E7 VDD_A3 E17

VDD_A2 C12 VDD_A2 C15 20 4

C5745_RF 2.2UF

VREF_SDC U21 VREF_UIM Y20

VDD_A2 VDD_A1 VDD_A2 VDD_A1 VDD_A2 VDD_A1

4 5 6 7 17 20

1

4 5

PP_1V8_LDO7

3 4 5

PP_1V8_LDO7

3 4 5

C5753_RF 2.2UF

20% 2 6.3V X5R-CERM 0201-1 RADIO_PMIC

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

BB_RF

MDM9645 BGA SYM 8 OF 8 GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

H7 J10 J16 J17 J22 J6 J9 K1 K12 K13 K16 K17 K8 K9 L11 L12 L16 L23 L7 L8 M10 M11 M14 M18 M6 M7 N10 N13 N14 N15 N16 N17 N18 N6 N9 P1 P12 P13 P17 P18 P8 P9 R11 R12 R17 R18 R7 T10 T11 T14

GND GND GND GND GND GND GND GND GND GND GND GND GND GND

T15 T16 T17 T23 T7 U10 U15 U17 U23 U9 V1 V6 Y4 Y8

C5705_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB BBPMU_TO_PMU_AMUX1

1

1

C5708_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

1

C5711_RF 2.2UF

1

C5714_RF 2.2UF

1

C5717_RF 2.2UF

1

C5720_RF 2.2UF

1

C5723_RF 2.2UF

1

C5726_RF 2.2UF

1

B

C5701_RF 15UF

20% 2 4V X5R-CERM 0201 RADIO_BB

20% 2 4V X5R-CERM 0201 RADIO_BB

20% 2 4V X5R-CERM 0201 RADIO_BB

20% 2 4V X5R-CERM 0201 RADIO_BB

20% 2 4V X5R-CERM 0201 RADIO_BB

20% 2 4V X5R-CERM 0201 RADIO_BB

2 6.3V CERM

1

1

1

1

1

1

1

20%

0402 RADIO_BB

C5706_RF 2.2UF

1

C5709_RF 2.2UF

20% 4V 2 X5R-CERM 0201 RADIO_BB

C5712_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

C5715_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

C5718_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

C5721_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

C5724_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

C5727_RF 2.2UF

20% 4V 2 X5R-CERM 0201 RADIO_BB

C5702_RF 15UF

SYNC_DATE=04/17/2015

20% 2 6.3V CERM 0402 RADIO_BB

PAGE TITLE

PAGE_TITLE=BASEBAND: POWER2 DRAWING NUMBER

(MODEM SUB MEMORY)

PP_1V0_LDO9

1

C5707_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

1

C5710_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

Apple Inc. 1

C5713_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

1

C5716_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

1

C5719_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

1

C5722_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

1

C5725_RF 2.2UF

20% 4V 2 X5R-CERM 0201 RADIO_BB

1

C5728_RF 2.2UF

20% 2 4V X5R-CERM 0201 RADIO_BB

1

051-00482 REVISION

8.0.0

R

C5703_RF 15UF 20%

2 6.3V CERM

0402 RADIO_BB

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

57 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

C

(MSM MODEM)

20% 2 4V X5R-CERM 0201 RADIO_BB

5 4

D

(MSM CORE)

PP_1V0_SMPS5

A

VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM VDD_MODEM

VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM

1

5 4

SYM 6 OF 8 PWR1

A1 A11 A12 A15 A17 A2 A22 A23 A4 A6 A7 A9 AA5 AB1 AB10 AB15 AB21 AB23 AB5 AB7 AB9 B13 B19 B20 B21 B22 B5 C1 C11 C16 C2 C20 C21 C4 C9 D2 D21 D23 E14 E15 E16 E18 E21 E22 E23 E6 E8 E9 F11 F14 F15 F16 F17 F23 G10 G13 G14 G15 G19 G23 H11 H12 H17 H18 H19 H23 H6

7

6

5

4

3

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

66 OF 81

IV ALL RIGHTS RESERVED

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

BASEBAND: CONTROL AND INTERFACES BB_RF

MDM9645

D

BGA

D 17 3

IN

17 3

OUT

3

17 7 6 5 4 20

IN

17 3

IN

PP_1V8_LDO6 1

IN

20 17

T2 U3 F2

SHIELD_SLEEP_CLK_32K XO_OUT_D0_EN SHIELD_MDM_19P2M_CLK

V19 V3

BB_JTAG_RST_L PMIC_RESOUT_L

1.00K

17 6

20 1

SWD_AP_TO_BB_CLK_BUFFER

SWD_AOP_BI_BB_SWDIO

BB_RF

CONTROL

MDM9645 BGA SYM 4 OF 8

RESOUT* V2 NC PS_HOLD PS_HOLD U2

SRST* RESIN*

R6 NC T3 NC W23 U19 NC W22 V22 NC V21 NC

R5807_RF

5% 1/32W MF 2 01005

SLEEP_CLK CXO_EN CXO

SYM 1 OF 8

MODE_0 MODE_1

SDC1_CLK SDC1_CMD SDC1_DATA_0 SDC1_DATA_1 SDC1_DATA_2 SDC1_DATA_3

TCK TRST* TMS TDI TDO

R21 V23 T21 T19 R19 R22

OUT

4

3

1

NC NC NC NC NC NC

SPMI_CLK Y17 SPMI_DATA AB18

SPMI_CLK SPMI_DATA

BI

3 17

BI

3 17

R5801_RF 240

1

R5802_RF 240

1% 1/32W MF 2 01005 RADIO_BB

1% 1/32W MF 01005 2 RADIO_BB

PLACE CLOSE TO E1

PLACE CLOSE TO T3

BDM_CAL EBI1_CAL MDM_VREF_LPDDR2 1

C5804_RF 0.1UF

10% 2 10V X5R-CERM 0201

D3 V5 K22 G21 K21 U5

BDM_ZQ EBI1_CAL VREF_DQ_BDM EBI1_VREF EBI1_VREF EBI1_VREF

MEMORY

RADIO_BB

NOSTUFF AT CARRIER PP_1V8_LDO6

20 17 7 6 5 4

NOSTUFF

C

C

5

U5801_RF

SOT1226 SWD_AP_TO_BB_CLK_BUFFER 4

2

6 17

NC

1

3

NC

20 1

SWD_AP_TO_MANY_SWCLK

74AUP1G34GX

BB_RF

MDM9645 BGA SYM 2 OF 8 10

10

IN

IN

SHIELD_XCVR0_PRX_CA2_I SHIELD_XCVR0_PRX_CA2_Q

B9 A10

BBRX_IP_CH0 BBRX_QP_CH0

ANALOG_RF

BBRX_IP_FB C10 BBRX_QP_FB B11

SHIELD_XCVR0_TX_FB_RX_I

IN

BB_RF

9 10

MDM9645 SHIELD_XCVR0_TX_FB_RX_Q

IN

BGA

9 10

SYM 5 OF 8 10

10

IN

IN

SHIELD_XCVR0_DRX_CA2_I SHIELD_XCVR0_DRX_CA2_Q

A8 C8

BBRX_IP_CH1 BBRX_QP_CH1

GNSS_BB_IP E11 GNSS_BB_QP E12

SHIELD_GPS_RX_I SHIELD_GPS_RX_Q

USB_PCIE IN

IN

10 17 3

10

10

10

10

3

IN

IN

IN

IN

IN

SHIELD_XCVR1_DRX_I

C5

SHIELD_XCVR1_DRX_Q

B6

B4

SHIELD_XCVR1_PRX_I

A5

SHIELD_XCVR1_PRX_Q

C5801_RF

10

0.1UF

IN

10

IN

10

IN

10

IN

20% 2 6.3V X5R-CERM 01005

BBRX_QP_CH2

BBRX_IP_CH3 BBRX_QP_CH3

C13 C19

TX_DAC_VREF TX_DAC_VREF

SHIELD_XCVR0_PRX_CA1_I SHIELD_XCVR0_PRX_CA1_Q

A3 C3

BBRX_IP_CH5 BBRX_QP_CH5

SHIELD_XCVR0_DRX_CA1_I SHIELD_XCVR0_DRX_CA1_Q

B2 B1

BBRX_IP_CH6 BBRX_QP_CH6

VREF_DAC_BIAS

1

BBRX_IP_CH2

F21 NC F22 NC H21 NC J21 NC

NC NC NC NC

TX_DAC0_IP TX_DAC0_IM TX_DAC0_QP TX_DAC0_QM

C17 B17 A16 B16

TX_DAC1_IP TX_DAC1_IM TX_DAC1_QP TX_DAC1_QM

C14 NC B14 NC A13 NC A14 NC A20 A21 A18 NC A19 NC F1 NC F6 NC G1 NC G6 NC Y3 NC

ET_DAC0_P ET_DAC0_M ET_DAC1_P ET_DAC1_M DNC DNC DNC DNC DNC

SHIELD_XCVR0-1_TX_I_P SHIELD_XCVR0-1_TX_I_N SHIELD_XCVR0-1_TX_Q_P SHIELD_XCVR0-1_TX_Q_N

PCIE_USB_SYSCLK USB_HS_REXT

BI

90_USB_BB_DATA_P 90_USB_BB_DATA_N

V10 Y10

USB_HS_DP USB_HS_DM

PCIE_TX_P AB6 PCIE_TX_M AA6

90_PCIE_BB_TO_AP_RXD_P 90_PCIE_BB_TO_AP_RXD_N

20 17 1

OUT

1

OUT

9

OUT

1

OUT

9

OUT

9

OUT

9

1

USB_SS_TX_P USB_SS_TX_M

PCIE_RX_P AA8 PCIE_RX_M AB8

90_PCIE_AP_TO_BB_TXD_P 90_PCIE_AP_TO_BB_TXD_N

IN

1

IN

1

USB_SS_RX_P USB_SS_RX_M

PCIE_REXT AA7

AB2 NC AA2 NC AA4 NC AB4 NC

R5806_RF

4.02K 1% 1/32W MF 2 01005

PLACE CLOSE TO U12 SHIELD_ET_DAC_P SHIELD_ET_DAC_N

PCIE_REFCLK_P V8 PCIE_REFCLK_M V7

AA9 Y9

90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_N

10 20 17 1

B

IN

50_MDM_PCIE_CLK BB_USB_TRXTUNE

OUT

16

OUT

16

NC

Y1

IN

1 17

IN

1 17

B

PCIE_CAL_RES 1

USB_SS_REXT

R5803_RF 1.43K

1% 1/32W MF 2 01005 RADIO_BB

PLACE CLOSE TO AA10

A

SYNC_DATE=04/17/2015 PAGE TITLE

PAGE_TITLE=BASEBAND: CONTROL DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

58 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

67 OF 81

IV ALL RIGHTS RESERVED

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

BASEBAND: GPIOS PP_1V8_LDO6

BB_RF

R5911_RF R5912_RF 1.00K

1% 1/32W MF 01005

D

SKU R5911_RF ROW NOSTUFF JP 1.0 KOHM

RADIO_BB NOSTUFF

R5912_RF NOSTUFF NOSTUFF

7 7 1

IN

1

IN 1

1 17 1 1

OUT IN OUT IN

17

MAV13 = BB_LAT_0 RF_BB_LAT_1 RF_BB_LAT_2 RF_BB_LAT_3

18 17 OUT 19 19 18 17 19 12

OUT 19 12

C

1.00K

1

2

1% 1/32W MF 01005

MDM9645 1

2

RADIO_BB OMIT_TABLE

SKU_ID

SKU_ID2

BB_EEPROM_I2C_SDA BB_EEPROM_I2C_SCL I2S_BB_TO_AP_LRCLK I2S_AP_TO_BB_DOUT I2S_BB_TO_AP_DIN I2S_BB_TO_AP_BCLK UART_BB_TO_AOP_RXD UART_AOP_TO_BB_TXD

FAST_BOOT_SELECT0 75_RFFE6_SCLK 75_RFFE6_SDATA 75_RFFE7_SCLK 75_RFFE7_SDATA

MAV13 = WDOG DIS

17 1

OUT

17 13

OUT

17 12

OUT

17 12

OUT

BUFFER ON RFFE5 SCLK/SDATA_A IS OUTPUT

BGA V15 NC AA19 NC AB14 NC Y15 NC T1 R3 R2 NC R1 NC T5 NC P3 NC R5 P5 V13 AA12 Y13 AA13 V14 AA14 Y14 NC AB13 NC AB19 NC P21 NC P23 NC Y18 NC N19 P22 NC N3 N2 N1 N5 M3 NC M2 NC M1 NC M5 NC L5 NC L3 NC L2 L1 N22 F5

BB_TO_STROBE_DRIVER_GSM_BURST_IND RX-DSPDT_CTL2 FBRX-DSPDT_CTL1 FBRX-DSPDT_CTL2

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 GPIO_32 GPIO_33 GPIO_34 GPIO_35 GPIO_36 GPIO_37 GPIO_38 GPIO_39

GPIO_40 GPIO_41 GPIO_42 GPIO_43 GPIO_44 GPIO_45 GPIO_46 GPIO_47 GPIO_48 GPIO_49 GPIO_50 GPIO_51 GPIO_52 GPIO_53 GPIO_54 GPIO_55 GPIO_56 GPIO_57 GPIO_58 GPIO_59 GPIO_60 GPIO_61 GPIO_62 GPIO_63 GPIO_64 GPIO_65 GPIO_66 GPIO_67 GPIO_68 GPIO_69 GPIO_70 GPIO_71 GPIO_72 GPIO_73 GPIO_74 GPIO_75 GPIO_76 GPIO_77 GPIO_78 GPIO_79

SYM 3 OF 8 GPIO

F3 NC K3 K5 NC J3 NC J2 J1 J5 H3 H2 H1 Y16 NC N23 AA16 V12 K19 NC Y23 L19 AA22 M23 NC AB22 NC Y12 NC AB17 Y22 NC M21 NC Y11 AA11 L21 W21 AA17 NC AA18 N21 NC AB12 NC H5 G3 G2 G5 Y21 Y19 AB20 AA20

SHIELD_GSM_TX_PHASE

OUT

1

75_RFFE3_SDATA 75_RFFE3_SCLK 75_RFFE4_SDATA 75_RFFE4_SCLK BB_TO_LAT_ANT_DATA BB_TO_LAT_ANT_SCLK

BI OUT BI OUT

13 17

2

13 17

9

C5902_RF 22PF PLACE CAP CLOSE TO MDM 2% 16V IMPROVES RXBN BY 4DB CERM

RF1352

01005

9 17 19 18 16 14 13 12 4

9 17

4 VIO

PP_1V8_LDO15

WLCSP

GPO1 1 GPO2 8

1 7 17 1 7 17 17 7 1

AP_TO_BB_TIME_MARK UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX

IN OUT IN

1 17

17 7 1

D

RFBUF_RF

BB_TO_LAT_ANT_SCLK

2 SCLK

BB_TO_LAT_ANT_DATA

3 SDATA

BUFFER_GPO1 BUFFER_GPO2

SCLK_A 5

BB_TO_UAT_SCLK

SDATA_A 6

BB_TO_UAT_DATA

BB_TO_AP_RESET_DETECT_L AP_TO_BB_COREDUMP AP_TO_BB_IPC_GPIO1

OUT

1 17

IN

1 17

BI

1 1

1 7 14

1 7 14

WDOG DIS CONFLICT

1 17 20 1 17 20

GND

USID=0XF

7

20 17 7 6 5 4

1

RFCAL_QCN

BB_TO_PMU_PCIE_HOST_WAKE_L

OUT

1 17

17 7 1

PCIE_BB_BI_AP_CLKREQ_L

BI

0.00

1 7

PCIE_AP_TO_BB_RESET_L AP_TO_BB_MESA_ON FAST_BOOT_SELECT1

R5909_RF 1 2

BB_TO_LAT_ANT_SCLK

BI

1

BI

3 17

IN

1 3

BB_TO_UAT_SCLK

1 7 14

0% 1/32W MF 01005

RADIO_BB NOSTUFF

17

1

SIM1_REMOVAL_ALARM

BI OUT

5% 16V NP0-C0G 01005

17 7 1

BB_TO_LAT_ANT_DATA

1

16 17 9 17

BI

9 17

BI

17 20

0.00

2

BB_TO_UAT_DATA

C

1 7 14

0% 1/32W MF 01005

16 17

BI

IN

R5910_RF

100PF

2

75_RFFE2_SDATA 75_RFFE2_SCLK 75_RFFE1_SDATA 75_RFFE1_SCLK SIM1_IO SIM1_DETECT SIM1_RST SIM1_CLK

C5903_RF

RADIO_BB NOSTUFF 20 1

PP1V8_SDRAM

17 20 17 20

OUT

1

17 20

C5906_RF 0.01UF

10% 2 6.3V X5R 01005

1

C5907_RF 33PF

5% 2 16V NP0-C0G-CERM 01005

GPIO_RF QM18064 A3 VIO

RFFE USAGE TABLE B

20 17 7 6 5 4

WTR3925 QFE3100 DIV MODULES WTR4905 TUNERS + ELNAS 2G PA,MLB PA,MB/HB TDD PA,MB/HB FDD PA LB PA, COUPLERS

1

PP_1V8_LDO6

1% 1/32W MF 01005 2 RADIO_BB NOSTUFF

1

1

R5907_RF 10K

PCIE_BB_BI_AP_CLKREQ_L

A1

1% 1/32W MF 2 01005 RADIO_BB

BB_TO_LAT_ANT_DATA

A2 SDATA

BB_TO_LAT_GPO1 BB_TO_LAT_GPO2 BB_TO_LAT_GPO3

1 1 1

NC

GND

USID=0X8

B

C5901_RF 1UF

20% 2 10V X5R 0201 RADIO_BB

4 5 6 7 17 20

1

R5908_RF 10K

1% 1/32W MF 2 01005 RADIO_BB

VCC

PCIE PULL-UPS TO BB RAIL

A

A1 SCLK

A4 B1 B2 B4

BB EEPROM

PP_1V8_LDO6

R5906_RF 100K

7 1

17 7 1

BB_TO_LAT_ANT_SCLK

GPO1 GPO2 GPO3 GPO4

B3

RFFE1 RFFE2 RFFE3 RFFE4 RFFE5 RFFE6 RFFE7

17 7 1

WLCSP

EPROM_RF CAT24C08C4A 7

BB_EEPROM_I2C_SCL

B1 SCL

WLCSP RADIO_BB

SDA B2

SYNC_DATE=04/17/2015 PAGE TITLE

BB_EEPROM_I2C_SDA

BASEBAND GPIOS

7

DRAWING NUMBER

Apple Inc.

VSS

051-00482 REVISION

8.0.0

A2

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

59 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

68 OF 81

IV ALL RIGHTS RESERVED

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

TRANSCEIVER: POWER D

STAR ROUTING

D

DEFAULT_RESISTOR_0.001OHM_2_1

R6001_RF 8 4

IN

1 PP_0V9_LDO3 DEFAULT_CAPACITOR_1e+06pF_2_1

1

C6001_RF 10UF

20% 2 6.3V CERM-X5R 0402 RADIO_TRANSCEIVER

0.00

2

0% 1/32W MF 01005

35MA

PP_VDD_XCVR0_RF1_TX_VCO

XCVR0_RF

DEFAULT_CAPACITOR_100000pF_2_1 DEFAULT_CAPACITOR_27.000000pF_2_1 1

RADIO_TRANSCEIVER

C6018_RF

0.1UF

20% 2 6.3V X5R-CERM 01005

1

WTR3925-2-TR-03-1

C6010_RF

27PF

WLPSP

5% 2 16V NP0-C0G 01005

RADIO_TRANSCEIVER

R6005_RF 1

0.00

2

0% 1/32W MF 01005

175MA

PP_VDD_XCVR0_RF1_TX

DEFAULT_CAPACITOR_100000pF_2_1 1

C6019_RF

0.1UF

20% 2 6.3V X5R-CERM 01005 DEFAULT_RESISTOR_0.001OHM_2_1

1

XCVR0_RF

C6011_RF

27PF

WLPSP

5% 2 16V NP0-C0G 01005

88

0.00

2

0% 1/32W MF 01005

67

1

45

VDD_RF1_DIG

DEFAULT_CAPACITOR_100000pF_2_1 DEFAULT_CAPACITOR_27.000000pF_2_1 64

VDD_RF1_RX1

LDO_CAP 23

20% 2 6.3V X5R-CERM 0201-1

VDD_RF1_RX2

VDD_RF2 30

25MA

PP_VDD_XCVR0_RF1_DIG

1

VDD_XCVR0_RF2_LDO_BYPASS

SYM 4 OF 5 PWR

VDD_RF1_TVCO RADIO_TRANSCEIVER VDD_RF1_TSIG

RADIO_TRANSCEIVER

R6006_RF 1

C6380_RF CAN BE 0201 (TBD)

WTR3925-2-TR-03-1

C6020_RF

0.1UF

20% 2 6.3V X5R-CERM 01005 DEFAULT_RESISTOR_0.001OHM_2_1

1

C6012_RF

49

27PF

C6024_RF 2.2UF

5% 2 16V NP0-C0G 01005

250MA

RADIO_TRANSCEIVER

BBPMU_TO_PMU_AMUX3

IN

R6007_RF

C

1

0.00

2

0% 1/32W MF 01005

1

DEFAULT_CAPACITOR_100000pF_2_1 DEFAULT_CAPACITOR_27.000000pF_2_1 1

C6021_RF

0.1UF

20% 2 6.3V X5R-CERM 01005 DEFAULT_RESISTOR_0.001OHM_2_1

1

GND

58 56 42 72

GND GND GND GND

28 84 21 91 20 90 19 89 102

GND GND GND GND GND GND GND GND GND

55

GND

GND 94

RADIO_TRANSCEIVER

GND GND GND GND GND GND GND

1

C6003_RF 0.47UF

20% 2 4V CERM-X5R-1 201 RADIO_TRANSCEIVER

C6013_RF

27PF

5% 2 16V NP0-C0G 01005

87 81 17 52 37 36 61

GND 53 GND 54 GND GND GND GND GND GND GND GND GND

4 8

DEFAULT_CAPACITOR_100000pF_2_1 DEFAULT_CAPACITOR_4700pF_2_1

40MA

PP_VDD_XCVR0_RF1_RX1

3

SYM 5 OF 5 GND

C6005_RF 4700PF

57 82 83 26 27 71 63 41 48

C

GND 38 GND 25 GND 31

10%

2 6.3V X5R

01005 RADIO_TRANSCEIVER

RADIO_TRANSCEIVER

R6008_RF 1

0.00

2

0% 1/32W MF 01005

250MA

PP_VDD_XCVR0_RF1_RX2

DEFAULT_CAPACITOR_100000pF_2_1 DEFAULT_CAPACITOR_27.000000pF_2_1 1

C6022_RF

0.1UF

20% 2 6.3V X5R-CERM 01005

1

C6014_RF

27PF

5% 2 16V NP0-C0G 01005

RADIO_TRANSCEIVER

XCVR1_RF WTR4905 WLNSP SYM 5 OF 5

9 13 16 21 24 25 26 27 29 30

B STAR ROUTING

DEFAULT_RESISTOR_0.001OHM_2_1

R6002_RF 8 4

IN

PP_0V9_LDO3 1

1

20%

250MA

2

PP_VDD_XCVR1_RF1_DIG

1

RADIO_TRANSCEIVER

2 6.3V X5R-CERM

C6007_RF

0.1UF

20% 2 6.3V X5R-CERM 01005

0201-1 RADIO_TRANSCEIVER

1

WLNSP

RADIO_TRANSCEIVER

2

0% 1/32W MF 01005

40MA

RADIO_TRANSCEIVER

C6008_RF

0.1UF

20% 2 6.3V X5R-CERM 01005

VDD_RF1_DIG

33 VDD_RF1_RX 23 VDD_RF1_TX DEFAULT_CAPACITOR_27.000000pF_2_1

PP_VDD_XCVR1_RF1_RX

1

SRM 4 OF 5

50

1

PWR

C6002_RF 0.47UF

20% 2 4V CERM-X5R-1 201 RADIO_TRANSCEIVER

WTR4905

5% 2 16V NP0-C0G 01005

R6003_RF

0.00

1

XCVR1_RF

C6015_RF

27PF

RADIO_TRANSCEIVER 1

BBPMU_TO_PMU_AMUX3

25MA

IN

4 8

DEFAULT_CAPACITOR_4700pF_2_1

0% 1/32W MF 01005

C6006_RF 2.2UF

0.00

1

C6004_RF 4700PF

GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND

GND

32 35 37 39 40 42 45 48 52

B

10%

2 6.3V X5R

01005 RADIO_TRANSCEIVER

VDD_RF2 44 VDD_RF2_LDO 34

VDD_XCVR1_RF2_LDO_BYPASS 1

C6023_RF 2.2UF

C6016_RF

20% 2 6.3V X5R-CERM 0201-1

27PF

5% 2 16V NP0-C0G 01005

RADIO_TRANSCEIVER

R6004_RF 1

0.00 0% 1/32W MF 01005

2

1

C6009_RF

0.1UF

20% 2 6.3V X5R-CERM 01005

A

175MA

PP_VDD_XCVR1_RF1_TX

RADIO_TRANSCEIVER

1

C6017_RF

27PF

5% 2 16V NP0-C0G 01005

SYNC_DATE=04/17/2015

RADIO_TRANSCEIVER

PAGE TITLE

PAGE_TITLE=TRANSCEIVER0/1: POWER DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

60 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

69 OF 81

IV ALL RIGHTS RESERVED

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

OMIT_TABLE

TRANSCEIVER: TX PORTS

C6106_RF 27PF 9

1

50_XCVR0_TX_HMB1_B11_B21

2

50_XCVR0_TX_B11_B21_PA_IN

OUT

19

2% 16V CERM 01005 RADIO_TRANSCEIVER

DEFAULT_INDUCTOR_2.800000nH_2_1

DEFAULT_CAPACITOR_22.000000pF_2_1

L6110_RF

C6116_RF

2.8NH-+/-0.1NH-0.36A

D 9

XCVR0_RF

1

50_XCVR0_TX_HMB2_B38_B40_B41

01005

WTR3925-2-TR-03-1

1

9 6

IN

9 6

IN

9 6

IN

9 6

IN

10 6

OUT

10 6

OUT

17 7

IN

17 7

IN

76 75 68 60

SHIELD_XCVR0-1_TX_I_P SHIELD_XCVR0-1_TX_I_N SHIELD_XCVR0-1_TX_Q_P SHIELD_XCVR0-1_TX_Q_N

9 1

SHIELD_XCVR0_TX_FB_RX_I SHIELD_XCVR0_TX_FB_RX_Q

47 62

75_RFFE1_SCLK 75_RFFE1_SDATA

DEFAULT_CAPACITOR_1000pF_2_1

TX_BB_IP TX TX_BB_IM RADIO_TRANSCEIVER TX_BB_QP TX_BB_QM TX_FBRX_BBI TX_FBRX_BBQ

1000PF SHIELD_WTR_19P2M_CLK

IN

1

46

2

SHIELD_XCVR0_19P2M_CLK_WTR_IN

10% 6.3V X5R-CERM 01005

1

C6112_RF 1.0PF

18

OUT

19

DEFAULT_CAPACITOR_1.200000pF_2_15% 16V CERM 01005

C6113_RF

C6107_RF 27PF

9 9 9

9

L6111_RF

1

2

1

50_XCVR0_TX_FBRX_IN_UNBAL

01005

C6118_RF

1

1.5PF

50_XCVR0_TX_FBRX_IN

2

50_XCVR0_TX_B1_B3_B4_B25_PA_IN 1

2% 16V CERM 01005 RADIO_TRANSCEIVER IN

L6102_RF 10NH-3%-140MA

12

01005 NOSTUFF RADIO_TRANSCEIVER

2% 16V CERM 01005 RADIO_TRANSCEIVER

C6117_RF 1.5PF

+/-0.1PF 2 16V NP0-C0G 01005-1

2

1

50_XCVR0_TX_HMB3_B1_B3_B4_B25

C6105_RF 27PF

3.0NH+/-0.1NH-200MA

9

1

+/-0.1PF 2 16V NP0-C0G 01005 NOSTUFF

OUT

9

100_XCVR0_TX_FBRX_IN_WTR TX_FBRX_P 8 16 TX_FBRX_M NC

XO_IN

2 50_XCVR0_TX_B38_B40_B41_PA_IN

+/-0.05PF 2 16V NP0-C0G-CERM 01005

66 NC 59 NC 51 NC 44 NC 101 50_XCVR0_TX_HMB1_B11_B21 100 50_XCVR0_TX_HMB2_B38_B40_B41 50_XCVR0_TX_HMB3_B1_B3_B4_B25 93 50_XCVR0_TX_HMB4_B7_B30 86

TX_HMLB1 80 NC 50_XCVR0_TX_HMLB2_B34_B39 TX_HMLB2 74

C6110_RF 9 3

TX_LB1 TX_LB2 TX_LB3 TX_LB4 TX_MHB1 TX_MHB2 TX_MHB3 TX_MHB4

RFFE_CLK RFFE_DATA

1

1.2PF

WLPSP SYM 3 OF 5

D

22PF

2 50_XCVR0_TX_HMB2_B38_B40_B41_MATCH

2

DEFAULT_INDUCTOR_2.800000nH_2_1

+/-0.1PF 2 16V NP0-C0G 01005-1

DEFAULT_CAPACITOR_22.000000pF_2_1

L6109_RF

C6115_RF

2.8NH-+/-0.1NH-0.36A 9

1

50_XCVR0_TX_HMB4_B7_B30

2

22PF 1

50_XCVR0_TX_HMB4_B7_B30_MATCH

01005 1

C

2

50_XCVR0_TX_B7_B30_PA_IN

OUT

19

DEFAULT_CAPACITOR_1.200000pF_2_1 5% 16V CERM 01005

C6114_RF

1.2PF

C

+/-0.05PF 2 16V NP0-C0G-CERM 01005

C6108_RF 27PF 9

1

50_XCVR0_TX_HMLB2_B34_B39

2

50_XCVR0_TX_B34_B39_PA_IN

OUT

18

2% 16V CERM 01005 RADIO_TRANSCEIVER

C6101_RF 27PF 9

50_XCVR1_TX_HMLB1_G1800_G1900

1

2

50_XCVR1_TX_G1800_G1900_PA_IN

2% 16V CERM 01005 RADIO_TRANSCEIVER

OUT

18

1

L6101_RF 10NH-3%-140MA 01005 NOSTUFF RADIO_TRANSCEIVER 2

B C6102_RF 27PF

XCVR1_RF

9

WTR4905

50_XCVR1_TX_HMLB2_B8_B20_B26_B27

SYM 2 OF 5 9 6 9 6

IN IN

9 6

IN

9 6

IN

7

17 7

14 19

SHIELD_XCVR0-1_TX_Q_P SHIELD_XCVR0-1_TX_Q_N

3 8 57

SHIELD_GSM_TX_PHASE

IN

56 51

75_RFFE4_SDATA 75_RFFE4_SCLK

IN

17 7

TX_BB_IP TX_BB_IM TX_BB_QP TX_BB_QM GP_DATA

TX

TX_DA1 TX_DA2 TX_DA3 TX_DA4 TX_DA5

1 18 12 2 7

TX_FBRX 31

50_XCVR1_TX_HMLB1_G1800_G1900 50_XCVR1_TX_HMLB2_B8_B20_B26_B27 NC 50_XCVR1_TX_HMLB4_B12_B13_B28 50_XCVR1_TX_HMLB5_G850_G900

50_XCVR1_TX_FBRX_IN

9

55

IN

SHIELD_WTR_19P2M_CLK

1

OUT

19

OUT

19

OUT

18

1

L6103_RF 10NH-3%-140MA

9

2

9

12

C6103_RF 27PF

RFFE_DATA RFFE_CLK

9

50_XCVR1_TX_HMLB4_B12_B13_B28

1

2

50_XCVR1_TX_B12_B13_B28_PA_IN

2% 16V CERM 01005 RADIO_TRANSCEIVER

XO_IN

2 SHIELD_XCVR1_19P2M_CLK_WTR_IN

5% 6.3V CERM 01005

1

C6111_RF 68PF

5% 2 25V NP0-C0G-CERM 01005

C6104_RF 27PF

NOSTUFF

A

50_XCVR1_TX_B8_B20_B26_B27_PA_IN

01005 NOSTUFF RADIO_TRANSCEIVER

100PF 9 3

2

9

DEFAULT_CAPACITOR_1000pF_2_1

C6109_RF

1

2% 16V CERM 01005 RADIO_TRANSCEIVER

WLNSP SHIELD_XCVR0-1_TX_I_P SHIELD_XCVR0-1_TX_I_N

B

9

50_XCVR1_TX_HMLB5_G850_G900

1

2

50_XCVR1_TX_G850_G900_PA_IN

2% 16V CERM 01005 RADIO_TRANSCEIVER

SYNC_DATE=04/17/2015 PAGE TITLE OFFPAGE=TRUE

1

TRANSCEIVER0/1: TX PORTS DRAWING NUMBER

L6104_RF 10NH-3%-140MA

Apple Inc.

01005 NOSTUFF RADIO_TRANSCEIVER

051-00482 REVISION

8.0.0

R

2

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

61 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

70 OF 81

IV ALL RIGHTS RESERVED

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

TRANSCEIVER: PRX, DRX, & GPS PORTS D

WTR3925-2-TR-03-1

WTR3925-2-TR-03-1

WLPSP

WLPSP 104 NC 96 NC 103 NC 95 NC 11 11 11 11 11 11

11 11 11 11

50_XCVR0_PRX_PMB1_B4 50_XCVR0_PRX_PMB2_B1_B4 50_XCVR0_PRX_PMB3_B3 50_XCVR0_PRX_PMB4_B34_B39 50_XCVR0_PRX_PMB5_B25 50_XCVR0_PRX_PMLB6_B11_B21 50_XCVR0_PRX_PHB1_B7 50_XCVR0_PRX_PHB2_B40_EXT 50_XCVR0_PRX_PHB3_B38_B40_B41 50_XCVR0_PRX_PHB4_B30

PRX_LB1 PRX_LB2 PRX_LB3 PRX_LB4

99 92 106 98 105 97

PRX_MB1 PRX_MB2 PRX_MB3 PRX_MB4 PRX_MB5 PRX_MLB6

73 65 85 79

PRX_HB1 PRX_HB2 PRX_HB3 PRX_HB4

D

XCVR0_RF

XCVR0_RF SYM 1 OF 5 PRX

PRX_CA1_BBI 69

SHIELD_XCVR0_PRX_CA1_I

OUT

6

RADIO_TRANSCEIVER

PRX_CA1_BBQ 77

SHIELD_XCVR0_PRX_CA1_Q

OUT

6

PRX_CA2_BBI 39

SHIELD_XCVR0_PRX_CA2_I

OUT

6

PRX_CA2_BBQ 33

SHIELD_XCVR0_PRX_CA2_Q

OUT

6

NC NC NC NC

11

IN

11

IN

11

IN

11

IN

11

IN

11

11

NC

50_XCVR0_DRX_DMB2_B34 50_XCVR0_DRX_DMB3_B1_B4 50_XCVR0_DRX_DMB4_B39 50_XCVR0_DRX_DMB5_B3_B25 50_XCVR0_DRX_DMLB6_B11_B21

NC

50_XCVR0_DRX_DHB2_B7_B38_B41

IN

NC

50_XCVR0_DRX_DHB4_B30_B40

IN

10

NC

50_GPS_RX

5 12 4 11

DRX_LB1 DRX_LB2 DRX_LB3 DRX_LB4

15 22 7 14 6 13

DRX_MB1 DRX_MB2 DRX_MB3 DRX_MB4 DRX_MB5 DRX_MLB6

43 50 29 35

DRX_HB1 DRX_HB2 DRX_HB3 DRX_HB4

2 10

DNC GNSS_L1

SYM 2 OF 5 DRX_GPS

DRX_CA1_BBI 78

SHIELD_XCVR0_DRX_CA1_I

OUT

6

DRX_CA1_BBQ 70

SHIELD_XCVR0_DRX_CA1_Q

OUT

6

DRX_CA2_BBI 34

SHIELD_XCVR0_DRX_CA2_I

OUT

6

DRX_CA2_BBQ 40

SHIELD_XCVR0_DRX_CA2_Q

OUT

6

GNSS_BBI 18

SHIELD_GPS_RX_I

OUT

6

GNSS_BBQ 32

SHIELD_GPS_RX_Q

OUT

6

RADIO_TRANSCEIVER

GP_DATA 24

NC

C

C

XCVR1_RF WTR4905 WLNSP SYM 3 OF 5 11 11

17 11 6

50_XCVR1_PRX_PLB1_B12_B13_B20_B28_B29 50_XCVR1_PRX_PLB2_B8_B26_B27

NC 11 11

PRX_LB1 PRX_LB2 PRX_LB3

4 10 5

50_XCVR1_PRX_PMB1_G1800 50_XCVR1_PRX_PMB2_G1900

NC

PRX

PRX_BBI 15

SHIELD_XCVR1_PRX_I

PRX_BBQ 20

SHIELD_XCVR1_PRX_Q

OUT

6

OUT

6

XCVR1_RF WTR4905 WLNSP SYM 1 OF 5

PRX_MB1 PRX_MB2 PRX_MB3

11

IN

11

IN

50_XCVR1_DRX_DLB1_B12_B13_B20_B28_B29 50_XCVR1_DRX_DLB2_B8_B26_B27 NC

28 22

NC NC

PRX_HB1 PRX_HB2

NC

50_XCVR1_DRX_DMB2_B3 11

NC NC NC

B

1

4

DRX_LB1 DRX_LB2 DRX_LB3

59 53

DRX_MB1 DRX_MB2

38 43

DRX_HB1 DRX_HB2

58

GNSS_IN

DRX_GPS

DRX_BBI 47

SHIELD_XCVR1_DRX_I

OUT

6

DRX_BBQ 36

SHIELD_XCVR1_DRX_Q

OUT

6

GNSS_BBI 46 SHIELD_XCVR0_TX_FB_RX_I

OUT

6 9

GNSS_BBQ 41 SHIELD_XCVR0_TX_FB_RX_Q

OUT

6 9

B

GPS FILTER

L6200_RF

120NH-5%-40MA PP_1V8_LDO14

49 54 60

2

0201 GNSS

PLACE NEAR U_WTR

1 C6201_RF

0.1UF 20%

2 6.3V X5R-CERM

01005 GNSS

7

GFILT_RF DEFAULT_RESISTOR_0.001OHM_2_1

15

A

IN

50_GNSS

1 RFIN

GLNA_RF SKY65766-13 LGA

R6201_RF RFOUT 9

3 LNA_EN

50_DRX_GPS_LNA_OUT 1

2 4 5 6 8

GND

1

C6204_RF 2.0PF

GNSS

+/-0.1PF 2 16V NP0-C0G 01005

NOSTUFF

0.00

0% 1/32W MF 01005

2

50_DRX_GPS_LNA_MATCH 1

GPS-GNSS

SAFGB1G56XA0F57 LGA 1 UNBAL_PRT

UNBAL_PRT 4 GND

C6205_RF 2.0PF

+/-0.1PF 2 16V NP0-C0G 01005

2 3 5 6

VDD

L6201_RF 10NH-3%-0.170A 50_GPS_FILTER_OUT 1

C6203_RF 1.6PF

1

2

50_GPS_RX

10

01005 SYNC_DATE=04/17/2015 PAGE TITLE

+/-0.1PF 2 16V NP0-C0G 01005

PAGE_TITLE=TRANSCEIVER0/1: PRX PORTS DRAWING NUMBER

NOSTUFF

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

62 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

71 OF 81

IV ALL RIGHTS RESERVED

2

1

SIZE

D

A

8

7

6

5

4

3

2 L6318_RF

PRIMARY & DIVERSITY RECEIVE MATCHING

GSMRX_RF

DC BLOCKING CAP VALUES CANNOT BE MORE THAN 33PF

NOSTUFF

19

50_LAT_MLB_G1800_G1900_PA_RX

IN

1

5% 6.3V NP0-C0G 0201

GSM1800 4

50_XCVR1_G1800_DIPLEX_IN

GSM1900 3

50_XCVR1_G1900_DIPLEX_IN

1

GND

3.6NH+/-0.1NH-0.5A

2 50_XCVR0_PRX_PMB2_G1900_MATCH

6 5 2

RADIO_TRANSCEIVER

1

C6333_RF

0201

0201

D

C6341_RF 27PF

5.1NH-3%-0.4A

L6320_RF

RADIO_TRANSCEIVER

2 OMIT_TABLE

1

+/-0.1PF 16V NP0-C0G 01005

19

1

IN

27PF

2 50_XCVR1_PRX_PLB1_B12_B13_B20_B28_B29_MATCH 0201

19

IN

L6304_RF

2

1

50_XCVR0_PRX_PMB5_B25_MATCH

C6305_RF

2% 16V CERM 01005 RADIO_TRANSCEIVER

0201

L6313_RF

2

RADIO_TRANSCEIVER

1

50_XCVR0_B11_B21_PA_PRX

1

OMIT_TABLE

2

10

1

C6307_RF

2 16V CERM 01005

C

50_XCVR0_PRX_PMB3_B3

2

10

0201

RADIO_TRANSCEIVER

3.0NH+/-0.1NH-0.6A 1

2% 16V CERM C6352_RF 01005 27PF RADIO_TRANSCEIVER 2%

L6306_RF

50_XCVR0_PRX_PMB3_B3_MATCH

2% 16V CERM 01005 RADIO_TRANSCEIVER

10

NOSTUFF 1

50_XCVR0_PRX_PMLB6_B11_B21

2

50_XCVR1_PRX_PLB2_B8_B26_B27

2

1.9NH-+/-0.1NH-0.6A-0.12OHM

RADIO_TRANSCEIVER

27PF IN

2

1

RADIO_TRANSCEIVER

2% 16V CERM 01005 RADIO_TRANSCEIVER

+/-0.05PF 25V C0G-CERM 0201

C6316_RF 19

1

C6306_RF 3.0PF

1

IN

27PF

2 50_XCVR1_PRX_PLB2_B8_B26_B27_MATCH 0201

27PF

2 50_XCVR0_PRX_PMLB6_B11_B21_MATCH

50_XCVR0_B3_PRX-DSPDT_OUT

1

50_XCVR1_B8_B26_B27_PA_PRX

C6315_RF

0201

C

19

OMIT_TABLE

L6305_RF

IN

C6329_RF

15NH-3%-0.3A-0.7OHM

6.2NH-3%-0.4A 19

10

2 16V CERM 01005

10

0201

OMIT_TABLE

50_XCVR1_PRX_PLB1_B12_B13_B20_B28_B29

2

RADIO_TRANSCEIVER

3.1NH-+/-0.1NH-0.5A-0.17OHM 1

50_XCVR0_PRX_PMB5_B25

2

1

NOSTUFF

1.6NH-+/-0.1NH-1A-0.05OHM

27PF 1

50_XCVR0_B25_PA_PRX

D

2% 16V CERM 1 C6351_RF 01005 27PF RADIO_TRANSCEIVER 2%

RADIO_TRANSCEIVER

C6314_RF

10

C6328_RF

20NH-3%-0.25A-0.8OHM 50_XCVR1_B12_B13_B20_B28_B29_PA_PRX

50_XCVR1_PRX_PMB2_G1900

2

2% 16V CERM 01005 RADIO_TRANSCEIVER OMIT_TABLE

2.0PF

RADIO_TRANSCEIVER OMIT_TABLE

2

L6312_RF

10

RADIO_TRANSCEIVER

L6319_RF

OMIT_TABLE

2

2% 16V CERM 01005 RADIO_TRANSCEIVER

2 OMIT_TABLE

+/-0.1PF 25V C0G-CERM 0201

1 COMMON

50_XCVR1_G1800_G1900_DIPLEX_OUT

1

C6332_RF 2.0PF

RADIO_TRANSCEIVER

1

27PF

2

2 50_XCVR0_PRX_PMB1_G1800_MATCH 0201

OMIT_TABLE

LGA

R6301_RF 1

1

C6340_RF OMIT_TABLE 27PF 50_XCVR1_PRX_PMB1_G1800

OMIT_TABLE

5.1NH-3%-0.4A

GSM1800-1900 B8856

1

2 0201

RADIO_TRANSCEIVER

L6307_RF

C6342_RF

4.3NH+/-3%-0.5A

C6308_RF

0201

RADIO_TRANSCEIVER

L6308_RF

19

1

IN

1.9NH-+/-0.1NH-0.6A-0.12OHM IN

1

50_XCVR0_B34_B39_PA_PRX

2

2

+/-0.1PF 25V C0G-CERM 0201

L6309_RF

2

IN

1

50_XCVR0_B7_PA_PRX

2

1

C6310_RF 18

IN

1

0.00

2

1

2.5NH+/-0.1NH-0.6A 2

10

1

C6311_RF

1

2 0201

50_XCVR0_PRX_PHB4_B30

2

IN

50_XCVR0_B11_B21_PA_DRX

1

2

C6348_RF 3.0PF 1

1

L6323_RF

IN

1

50_XCVR0_B3_B25_DRX-DSPDT_OUT

50_XCVR0_DRX_DMLB6_B11_B21

L6321_RF

19

IN

50_XCVR0_B40_PA_PRX_EXT_FIL

1

2

50_XCVR1_DRX_DMB2_B3 10

L6325_RF

5% 6.3V NP0-C0G 0201

3.2NH+/-0.1NH-0.5A 1

2 0201

C6344_RF

C6349_RF

3.2NH+/-0.1NH-0.5A 2

1

2

50_XCVR0_DRX_DMB5_B3_B25 10

2% 16V CERM 01005 RADIO_TRANSCEIVER

SYNC_DATE=07/21/2015 PAGE TITLE

RECEIVE MATCHING DRAWING NUMBER

4.3NH+/-3%-0.5A

2

27PF 1

RADIO_TRANSCEIVER

0201

OMIT_TABLE

10

C6338_RF

2 50_XCVR1_DRX_DMB2_B3_MATCH

RADIO_TRANSCEIVER

27PF

1

1

10

10

0201

2

RADIO_TRANSCEIVER

C6346_RF 27PF 1

50_XCVR0_PRX_PHB2_B40_EXT_MATCH

0201

2

SHUNT COMPONENT WITH BAND 40 FILTER

Apple Inc.

50_XCVR0_PRX_PHB2_B40_EXT 10

2% 16V CERM 01005 RADIO_TRANSCEIVER

RADIO_TRANSCEIVER

RADIO_TRANSCEIVER OMIT_TABLE

IN

50_XCVR1_B3_DRX-DSPDT_OUT

50_XCVR0_DRX_DMB4_B39

2

50_XCVR1_DRX_DLB2_B8_B26_B27

2

0201

2 50_XCVR0_DRX_DMB5_B3_B25_MATCH

RADIO_TRANSCEIVER

+/-0.05PF 25V C0G-CERM 0201

13

2% 16V CERM 01005 RADIO_TRANSCEIVER

0201

2

L6324_RF

2.4NH+/-0.1NH-0.6A

10

2.4NH+/-0.1NH-0.6A

6.2NH-3%-0.4A

50_XCVR0_DRX_DMLB6_B11_B21_MATCH

2% 16V CERM 01005 RADIO_TRANSCEIVER OMIT_TABLE

IN

1

50_XCVR0_B39_MBHB-DRX-ASM_OUT

L6322_RF

27PF 19

13

10

13

C6345_RF

IN

1

50_XCVR1_B8_B26_B27_LB-DRX-ASM_OUT

50_XCVR0_DRX_DMB3_B1_B4

2

27PF

RADIO_TRANSCEIVER

A

13

C6325_RF

2% 16V CERM 01005 RADIO_TRANSCEIVER

2.1NH-+/-0.1NH-0.6A-0.12OHM

RADIO_TRANSCEIVER

IN

C6320_RF

50_XCVR_PRX_PHB4_B30_MATCH

1% 1/20W MF 0201

13

1

50_XCVR0_B1_B4_MBHB-DRX-ASM_OUT

C6337_RF

2% 16V CERM 01005 RADIO_TRANSCEIVER

2% 16V CERM 01005 RADIO_TRANSCEIVER

27PF

2

10

27PF

50_XCVR0_PRX_PHB3_B38_B40_B41

2

10

27PF

50_XCVR0_DRX_DMB2_B34

2

C6324_RF

2% 16V CERM 01005 RADIO_TRANSCEIVER

L6311_RF 0.00

IN

1

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

63 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

SHEET

72 OF 81

IV ALL RIGHTS RESERVED

5

B

50_XCVR1_DRX_DLB1_B12_B13_B20_B28_B29

2

2% 16V CERM 01005 RADIO_TRANSCEIVER

27PF

L6301_RF

1

IN

2% 16V CERM 01005 RADIO_TRANSCEIVER

27PF 50_XCVR0_B34_MBHB-DRX-ASM_OUT

1

50_XCVR1_B12_B13_B20_B28_B29_LB-DRX-ASM_OUT

C6323_RF

10

C6319_RF

RADIO_TRANSCEIVER

1

50_XCVR0_PRX_PHB1_B7

2

2

0201

50_XCVR0_B30_PA_PRX

27PF 13

13

RADIO_TRANSCEIVER 50_XCVR0_PRX_PHB3_B38_B40_B41_MATCH

10

C6336_RF

0201

+/-0.1PF 25V C0G 201

1% 1/20W MF 0201

19

10

1.0PF

RADIO_TRANSCEIVER

50_XCVR0_B38_B40_B41_PA_PRX

2

50_XCVR0_DRX_DHB4_B30_B40

2

2% 16V CERM 01005 RADIO_TRANSCEIVER

50_XCVR0_PRX_PMB4_B34_B39

1

C6302_RF

2% 16V CERM 01005

1

50_XCVR0_B30_B40_MBHB-DRX-ASM_OUT

IN

10

C6335_RF 27PF

13

50_XCVR0_DRX_DHB2_B7_B38_B41

2

2% 16V CERM 01005 RADIO_TRANSCEIVER

3.9NH+/-0.1NH-0.5A

50_XCVR0_PRX_PHB1_B7_MATCH

1

0201

L6310_RF

RADIO_TRANSCEIVER

27PF 19

25V +/-0.1PF C0G-CERM 0201

27PF

RADIO_TRANSCEIVER

2% 16V CERM 01005 RADIO_TRANSCEIVER

0201

C6318_RF

DC BLOCKING CAP VALUES CANNOT BE MORE THAN 33PF

27PF

C6301_RF

B

2.2PF

10

1

C6334_RF

2 50_XCVR0_DRX_DHB2_B7_B38_B41_MATCH

C6350_RF

C6317_RF

3.3NH+/-0.1NH-0.5A 1

IN

1

50_XCVR0_B7_B41_B38_MBHB-DRX-ASM_OUT

50_XCVR0_PRX_PMB2_B1_B4

2

50_XCVR0_PRX_PMB4_B34_B39_MATCH

0201

13

2% 16V CERM 01005 RADIO_TRANSCEIVER

1.2PF 1

L6328_RF

3.0NH+/-0.1NH-0.6A

27PF 1

C6309_RF

RADIO_TRANSCEIVER

10

C6343_RF

2 50_XCVR0_PRX_PMB2_B1_B4_MATCH 0201

18

2

+/-0.1PF 25V C0G-CERM 0201

4.3NH+/-3%-0.5A

50_XCVR0_PRX_PMB1_B4

2

2% 16V CERM 01005 RADIO_TRANSCEIVER

1.2PF 1

50_XCVR0_B1_B4_PA_PRX

1

1

IN

27PF

2 50_XCVR0_PRX_PMB1_B4_MATCH

2

19

1

50_XCVR0_B4_PA_PRX

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

LOWER ANTENNA AND COUPLER JLAT1_RF

MM7829-2700 F-ST-SM

PP_2V7_LDO12

R6402_RF

14 13 12 4

2

D

1.3NH+/-0.1NH-1.1A 1 C6407_RF

1 C6409_RF

18PF 2% 2 16V CERM 01005

0.1UF 20% 2 6.3V X5R-CERM 01005

1

LATDI_RF

1 C6410_RF

19

BI

19

BI

50_LAT_LB_COMBINER_IN 50_LAT_MB_HB_COMBINER_IN

6 LB 0805-LGA 4 MB-HB

ANT

LATCP_RF

2NH+/-0.1NH-0.6A 2

50_LAT_LB_MB_HB_COMBINER_OUT

1

SKY16705-21

2

50_LAT_LB_MB_HB_CPL_IN

0201

1 3 5

GND

1 C6403_RF

1 C6402_RF

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

NC

FL6402_RF

1 13

RFIN1 RFIN2

6

USID

10-OHM-1.1A

19 18 16 14 13 12 7 4 19 12 7

BI

19 12 7

IN

1

PP_1V8_LDO15 75_RFFE7_SDATA 75_RFFE7_SCLK

IN

2

5 12 8

PP_1V8_LDO15_LATCP

01005

RFOUT1 RFOUT2

2 14

RF_CPL1 RF_CPL2

4 16

LGA

VIO SDATA SCLK

50_LAT1_ANT

1

1

C6411_RF

3

0.7PF

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

VDD

R6401_RF

LFD21829MMY1E339

2 0201

9

D

+/-0.05PF 2 25V C0G-CERM 0201

NOSTUFF

50_LAT_LB_MB_HB_CPL_ANT

NC

50_XCVR0_LAT_CPLD 50_XCVR1_LAT_CPLD

12 12

PP_2V7_LDO12

14 13 12 4

1 C6419_RF

1 C6420_RF

1 C6401_RF

18PF 2% 2 16V CERM 01005

18PF 2% 2 16V CERM 01005

0.033UF 20% 2 4V X5R-CERM 01005

3 7 10 11 15

GND

USID=0X6

1 C6414_RF

8

18PF 2% 2 16V CERM 01005

VDD

SWLATCP_RF

C

C

CXA4439GC-E

9

OUT

9

OUT

6 10

50_XCVR0_TX_FBRX_IN 50_XCVR1_TX_FBRX_IN 17 7 17 7

7 9

FBRX-DSPDT_CTL1 FBRX-DSPDT_CTL2

RF1 RF2

LGA-1

VCTL1 VCTL2

RF1A RF1B

5 4

50_XCVR0_LAT_CPLD 50_XCVR0_UAT_CPLD

RF2A RF2B

2 1

50_XCVR1_UAT_CPLD 50_XCVR1_LAT_CPLD

12 12

12 12

3

GND

UPPER ANTENNA COUPLER PP_2V7_LDO12

1

9

14 13 12 4

VDD

B

19

BI

6 LB 0805-LGA OMIT_TABLE 4 MB-HB

18PF 2% 2 16V CERM 01005

0.1UF 20% 2 6.3V X5R-CERM 01005

ANT

2

1

50_UAT_LB_MLB_COMBINE

1 C6405_RF

GND 1 3 5

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

R6400_RF 0.00

50_UAT_LB_MLB_CPL_IN

2

1% 1/20W MF 0201

19

50_UAT_MB_HB_CPL_IN

FL6401_RF 10-OHM-1.1A

1 C6404_RF

18PF 16 14 2% 2 25V C0H-CERM 0201 NOSTUFF

13 12 7 4 19 18 19 12 7

BI

19 12 7

IN

IN

PP_1V8_LDO15 75_RFFE7_SDATA 75_RFFE7_SCLK

1

2 01005

PP_1V8_LDO15_UATCP

1 13

RFIN1 RFIN2

6

USID

5 12 8

RFOUT1 RFOUT2

2 14

RF_CPL1 RF_CPL2

4 16

LGA

VIO SDATA SCLK

2

50_UAT_LB_MLB_SOUTH

1% 1/20W 1 C6417_RF MF 0201 18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

SKY16705-21

LFD21829MMY1E339 50_UAT_LB_COMBINER_IN 50_UAT_MLB_COMBINER_IN

1 C6408_RF

UATCP_RF

UATDI_RF

19

1 C6406_RF

R6405_RF 0.00

1

1

OUT

C6418_RF

18PF 5% 2 16V CERM 01005

NOSTUFF

B

50_UAT_LB_MLB_CPL_OUT 50_UAT_MB_HB_CPL_ANT

50_XCVR0_UAT_CPLD 50_XCVR1_UAT_CPLD

R6404_RF

12

1.3NH+/-0.1NH-1.1A

12

1

2

50_UAT_MB_HB_SOUTH

OUT

1

0201 1 C6415_RF OMIT_TABLE

GND 0.033UF 20% 2 4V X5R-CERM 01005

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

3 7 10 11 15

1 C6400_RF

USID=0X7

1

C6416_RF 0.3PF

+/-0.1PF 2 25V C0G-CERM 201

OMIT_TABLE

A

SYNC_DATE=04/17/2015 PAGE TITLE

PAGE_TITLE=LOWER ANTENNA & COUPLERS DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

64 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

73 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

7

6

5

4

DIVERSITY RECEIVE

3

2

1

LB DRX ASM 14 13 12 4

D

D

PP_2V7_LDO12 1 C6501_RF

1 C6505_RF

0.1UF 20% 2 6.3V X5R-CERM 01005

18PF 2% 2 16V CERM 01005

9

8

R6501_RF

VDD 11

11

50_XCVR1_B12_B13_B20_B28_B29_LB-DRX-ASM_OUT

NC

50_XCVR1_B8_B26_B27_LB-DRX-ASM_OUT

19 18 16 14 13 12 7 4

IN

17 13 7

BI

17 13 7

IN

2 12 3 11

VLB_RX0 VLB_RX1 LB_RX0 LB_RX1

3.9NH+/-0.1NH-0.5A

LBDSM_RF

ANT 16 50_LAT-UAT_LB-DRX-ASM_ANT

HFQSWEWUA LGA

1

18PF 2% 2 16V CERM 01005

0.033UF 20% 2 4V X5R-CERM 01005

0201

1

C6507_RF

IN

19

C6510_RF

2.0PF

+/-0.1PF 2 25V C0G-CERM 0201

+/-0.1PF 2 25V C0G-CERM 0201

NOSTUFF

NOSTUFF

19 20 21

1 C6503_RF

50_LB_DRX

EPAD

1 4 8 10 13 14 15 17 18

GND 1 C6514_RF

2

2.0PF

5 VIO 7 SDATA 6 SCLK

PP_1V8_LDO15 75_RFFE3_SDATA 75_RFFE3_SCLK

1

USID=0X9

C

C

MB HB DRX ASM 14 13 12 4

PP_2V7_LDO12 1 C6504_RF

1 C6506_RF

0.1UF 20% 2 6.3V X5R-CERM 01005

18PF 2% 2 16V CERM 01005

3

18

18PF 2% 2 16V CERM 01005

1 C6502_RF

50_XCVR0-1_B3_B25_MBHB-DRX-ASM_OUT 50_XCVR0_B1_B4_MBHB-DRX-ASM_OUT 11 50_XCVR0_B30_B40_MBHB-DRX-ASM_OUT 11 50_XCVR0_B7_B41_B38_MBHB-DRX-ASM_OUT 50_XCVR0_B34_MBHB-DRX-ASM_OUT 11 50_XCVR0_B39_MBHB-DRX-ASM_OUT 11

VDD

SWDSM_RF CXA4430GC-E

11

50_XCVR1_B3_DRX-DSPDT_OUT 50_XCVR0_B3_B25_DRX-DSPDT_OUT

LGA

RFIN

CTRL 1

B

5

GND

11

2

RX-DSPDT_CTL2

MIPI_VDD B3_B25_RX B1_B4_RX MHBDSM_RF D5315 B30_B40_RX LGA B7_B38/B41B_B41_RX B34_RX B39_RX

R6502_RF ANT1 10

1

50_LAT_MB-HB-DRX-ASM_ANT1

7 17 19 18 16 14 13 12 7 4

1 C6513_RF

18PF 2% 2 16V CERM 01005

IN

17 13 7

BI

17 13 7

IN

22 MIPI_VIO 20 MIPI_SDATA 21 MIPI_SCLK

PP_1V8_LDO15 75_RFFE3_SDATA 75_RFFE3_SCLK

1

ANT2 8 GND

C6508_RF

2.0PF

+/-0.1PF 2 25V C0G-CERM 0201

THRM_PAD

0

2

5% 1/20W MF 201

50_LAT_MB_HB_DRX 1

18PF 2% 2 16V CERM 01005

IN

19

C6511_RF

B

2.0PF

+/-0.1PF 2 25V C0G-CERM 0201

NOSTUFF 1 C6515_RF

23 24 25 26

11

4 RF1 6 RF2

2 3 15 16 13 14

1 4 5 6 7 9 11 12 17 19

14 13 12 4

PP_2V7_LDO12

NOSTUFF

R6503_RF 1

50_UAT_MB-HB-DRX-ASM_ANT2

USID=0XA

1

C6509_RF

2.0PF

+/-0.1PF 2 25V C0G-CERM 0201

NOSTUFF

0

5% 1/20W MF 201

2

50_UAT_MB-HB-DRX-LNA_OUT_RX 1

IN

14

C6512_RF

2.0PF

+/-0.1PF 2 25V C0G-CERM 0201

NOSTUFF

A

SYNC_DATE=04/17/2015 PAGE TITLE

PAGE_TITLE=DIVERSITY RECEIVE ASM'S DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

65 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

74 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

DIVERSITY RECEIVE LNAS LB DRX LNA 14

PP_MHBLN_RF

D 10

D VDD 14

3

50_UAT_LB-DRX-LNA_TX_RX

LBLN_RF

TX_RX

ANT

14 50_UAT_LB-DRX-LNA_ANT

15

SKY13702-17 LGA

BI IN

VIO SDATA SCLK GND

1 C6617_RF 1 C6619_RF 1 C6620_RF

18PF 2% 2 16V CERM 01005

0.033UF 20% 2 4V X5R-CERM 01005

1 2 4 5 6 11 12 13 15 16 17 18 19 20 21 22

18PF 2% 2 16V CERM 01005

EPAD 23 24 25

14 7 1 14 7 1

9 7 8

PP_1V8_LDO15 BB_TO_UAT_DATA BB_TO_UAT_SCLK

19 18 16 14 13 12 7 4

USID=0X2

MB/HB DRX LNA 1

50_UAT_LB_SPLIT_OUT

1% 1/20W MF 0201 OMIT_TABLE

UPPDI_RF

BI

50_UUAT_LB_MLB_NORTH

1

2

1% 1/20W 0201

1 C6611_RF

LFD21829MMP5E222 50_UAT_LB_MLB_SPLIT_IN

1 C6601_RFMF

1 C6602_RF

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

2

LGA ANT OMIT_TABLE

GND

50_UAT_LB-DRX-LNA_TX_RX

14 13 12 4

1

PP_2V7_LDO12

1 C6614_RF

14

1 C6629_RF

1 C6625_RF

0.1UF 20% 2 6.3V X5R-CERM 01005

18PF 2% 2 16V CERM 01005

PP_MHBLN_RF

VDD 1

2.7NH+/-0.1NH-0.6A 1

2 01005

R6605_RF

50_UAT_MLB_SPLIT_OUT

C

FL6602_RF

150OHM-25%-200MA-0.7DCR

14

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

LB 4 MB-HB 6

5 3 1

1

R6601_RF 0.00

2

20

C

R6606_RF 0.00

2

13

50_UAT_MLB-DRX-LNA_TX_RX

4 2

50_UAT1_WEST 50_UAT_MB-HB-DRX-LNA_OUT_RX

MHBLN_RF

IN_TX OUT_RX

ANT 16

SKY13703-21

50_UAT_MB-HB-DRX-LNA_ANT

15

LGA

14

0201

OMIT_TABLE 1

1.5PF

+/-0.05PF 2 25V C0G-CERM 0201

OMIT_TABLE

14 7 1

BI

14 7 1

IN

C6613_RF

10NH-3%-250MA

21 23 22

PP_1V8_LDO15 BB_TO_UAT_DATA BB_TO_UAT_SCLK

VIO SDATA SCLK GND

0201

EPAD

2 OMIT_TABLE

25 26 27 28

C6610_RF

IN

1 3 5 6 7 8 9 10 11 12 13 14 15 17 18 19 24

1

19 18 16 14 13 12 7 4

USID=0X3 B

MLB DRX LNA

B

FL6603_RF

150OHM-25%-200MA-0.7DCR 1

PP_2V7_LDO12

2 01005

PP_MLBLN_RF 1 C6627_RF

1 C6622_RF

0.1UF 20% 2 6.3V X5R-CERM 01005

18PF 2% 2 16V CERM 01005

1

14 13 12 4

VDD 14

50_UAT_MLB-DRX-LNA_TX_RX

MLBLN_RF

6 OUT_RX

ANT 13

LMRX2HJB-H68

50_UUAT_MLB

15

LGA OMIT_TABLE

14 7 1

BI

14 7 1

IN

PP_1V8_LDO15 BB_TO_UAT_DATA BB_TO_UAT_SCLK

2 4 3

VIO SDATA SCLK GND

EPAD 15 16

IN

5 7 8 9 10 11 12 14

19 18 16 14 13 12 7 4

USID=0X4

A

SYNC_DATE=04/17/2015 PAGE TITLE

DIVERSITY RECEIVE LNA'S DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

66 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

75 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

CDS_LIB=apple

1

SIZE

D

A

8

7

6

5

4

3

2

1

UPPER ANTENNA FEEDS D

D OMIT_TABLE R6708_RF 14

BI

50_UAT_LB-DRX-LNA_ANT

0.00

1

2

50_UUAT_LB_PLEXER

1% 1/20W MF 0201 UP_RFFE

1 C6726_RF

UAT1

18PF 2%

2 25V C0H-CERM

0201 UP_RFFE NOSTUFF

OMIT_TABLE R6710_RF 1

2

1% 1/20W MF 0201 UP_RFFE

OMIT_TABLE R6703_RF 14

BI

50_UAT_MB-HB-DRX-LNA_ANT

1

0.00

2

1% 1/20W MF 0201 UP_RFFE

C

50_UUAT_MLB_PLEXER 1 C6728_RF

18PF

2% 2 25V C0H-CERM 0201 UP_RFFE NOSTUFF

10 8 14 1 17

F-RT-SM

PPLXR_RF

LB MLB MB-HB WIFI GNSS

50_UAT1_TUNER

ACFM-W312-AP1 R6705_RF

LGA OMIT_TABLE

ANT 5

1

50_UAT1

2

R6715_RF

50_UAT1_MATCH

1

0.00

2

TO ANTENNA TUNER 1

50_UAT1_TEST

2 C

1% 1/20W MF 0201 UP_RFFE

1% 1/20W MF 0201 UP_RFFE

50_UUAT_HB_PLEXER

R

BI

1

GND UP_RFFE

1

1 C6711_RF

GND

18PF

2% 25V 2 C0H-CERM 0201 UP_RFFE NOSTUFF

0.00

3

50_UUAT_MLB

EPAD

1

C6713_RF

L6700_RF

18PF

19

BI

JUAT1_RF

MM8830-2600B

2 3 4 6 7 9 11 12 13 15 16 18

14

0.00

2% 2 25V C0H-CERM 0201

56NH-100MA-3.9OHM 0201

C

UP_RFFE NOSTUFF

NOSTUFF 2

1

50_UAT_WLAN_2G_WEST_PLEXER

BI

R6709_RF 10

50_GNSS

1

0.00

2

1% 1/20W MF 0201 UP_RFFE

50_GNSS_PLEXER 1 C6727_RF

18PF 2%

2 25V C0H-CERM

0201 UP_RFFE NOSTUFF

B

B

A

SYNC_DATE=04/17/2015 PAGE TITLE

PAGE_TITLE=UPPER ANTENNA FEEDS DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

67 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

76 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

8

7

6

5

4

3

2

1

PMU: ET MODULATOR D

D

C

18

19 18

PP_VPA_APT

PP_1V8_LDO15

IN

C

4 7 12 13 14 18 19

PP_QPOET_VCC_PA PP_VDD_MAIN

19 18

PP_PA_VBATT

1

C6801_RF

6

IN

6

IN 17 7 17

SHIELD_ET_DAC_P SHIELD_ET_DAC_N 75_RFFE2_SCLK 7 75_RFFE2_SDATA

17 16

AMP_IN+ AMP_IN-

20% 2 6.3V X5R-CERM 0201-1

VDD_VBATT 12 VDD_VBATT 13

VDD_LDO 24 VDD_LDO 25

VDD_BUCK 20 VDD_BUCK 21

VDD_1P8 15

7 VCC_PA_GSM 8 VCC_PA_GSM

2 3

5 VCC_PA_ET 6 VCC_PA_ET

PA_VBATT

10

2.2UF

TRIM_14 TRIM_18

26 23

USID_LSB

19

QPOET_RF

2103-601507-10

SCLK SDATA

LGA

1

C6802_RF

2.2UF

20% 6.3V 2 X5R-CERM 0201-1

1

C6803_RF

2.2UF

20% 2 6.3V X5R-CERM 0201-1

1

C6804_RF

2.2UF

20% 2 6.3V X5R-CERM 0201-1

1

1 3 4 16 20

C6805_RF

2.2UF

20% 2 6.3V X5R-CERM 0201-1

NC

4 11 18 27 28 29 30 31 32 1 9 14 22

GND

B

B

DESENSE CAPS 20 16 4 3 1

IN

PP_VDD_MAIN 1

C6806_RF

1

C6807_RF 27PF

100PF

2

5% 16V NP0-C0G 01005

2

2% 16V CERM 01005

PLACE C6806 AND C6807 NEAR THE QPOET

A

A PAGE TITLE

PMU: ET MODULATOR DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

68 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

8

7

6

5

4

3

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

77 OF 81

IV ALL RIGHTS RESERVED

2

1

SIZE

D

8

7

6

5

4

3

2

1

MLB TEST POINTS BBPMU

BASEBAND SM

SM

PP

75_RFFE1_SDATA

7 9

PP

OMIT

1

SWD_AP_TO_BB_CLK_BUFFER

SM

P2MM-NSM

P2MM-NSM

SM

P2MM-NSM

PP6919_RF

PP6906_RF

P2MM-NSM 1

DEFAULT FAST_BOOT[2:0] USB = 0X2

PP6945_RF

PP7000_RF

D

BOOT CONFIG

PP

6

PP

1

BB_JTAG_RST_L

1

PMIC_RESOUT_L

20 7 6 5 4

PP_1V8_LDO6

D

3 6

OMIT

6 20

OMIT

OMIT

NOSTUFF

PP6905_RF

1

P2MM-NSM

PP6952_RF

P2MM-NSM

P2MM-NSM

SM PP

PP6920_RF

PP6907_RF

P2MM-NSM 1

7 9 PP

OMIT

1

PMU_TO_BB_USB_VBUS_DETECT

PP

1 3 20

PP

OMIT

PP

1

NFC_TO_BB_CLK_REQ

PP

1 3

PP6944_RF SM

7 16

PP

PP

1

SIM1_REMOVAL_ALARM

7 12

1

BB_TO_PMU_PCIE_HOST_WAKE_L

1 7

OMIT

3 7

OMIT

PP6939_RF

PP6924_RF

P2MM-NSM

SIM

P2MM-NSM

SM

SM

75_RFFE3_SDATA

7 13

PP

OMIT

P2MM-NSM PP

SM PP

1

1

50_MDM_PCIE_CLK

PP

7 13

P2MM-NSM SM

SPMI_DATA

3 6 PP

PP6926_RF

SM

SM

SM PP

7 9

1

XO_OUT_D0_EN

PP

OMIT

OMIT

SIM1_IO

7 20

C

PP6969_RF

P2MM-NSM

3 6

1

OMIT

PP6912_RF P2MM-NSM

P2MM-NSM PP

1

OMIT

PP6941_RF 75_RFFE4_SDATA

PP6953_RF

SM

OMIT

1

3 6

P2MM-NSM

3 6

OMIT

75_RFFE3_SCLK

SPMI_CLK

PP6925_RF

SM

P2MM-NSM

1

OMIT

PP6911_RF

PP6940_RF

C

OMIT

FBRX-DSPDT_CTL2

SM

P2MM-NSM

75_RFFE2_SCLK

OMIT

PP

FAST_BOOT_SELECT0

1 3

P2MM-NSM

PP6909_RF

SM

1

7

PMU_TO_BBPMU_RESET_L

PP6923_RF

P2MM-NSM PP

1

1

OMIT

OMIT

1

PP

2

7 FAST_BOOT_SELECT1

SM

SM

SM

7 16

2

PP6900_RF

R6922_RF 10K

1% 1/32W MF 01005 RADIO_DEBUG

1% 1/32W MF 01005 RADIO_DEBUG

1 3 20

7 12

P2MM-NSM

P2MM-NSM

75_RFFE2_SDATA

AP_TO_BBPMU_RADIO_ON_L

OMIT

FBRX-DSPDT_CTL1

PP6921_RF

PP6908_RF

1

1

P2MM-NSM

PP6943_RF SM

1

OMIT

OMIT

P2MM-NSM

PP

SM

SM

75_RFFE1_SCLK

SM

1

R6921_RF 10K

1

P2MM-NSM SM

UART_BB_TO_AOP_RXD

1 7 PP

OMIT

1

SIM1_DETECT

7 20

OMIT

PP6913_RF P2MM-NSM

PP6942_RF SM

PP

PP

1

PP6972_RF

SM

P2MM-NSM

75_RFFE4_SCLK

1

BB_TO_NFC_CLK

P2MM-NSM SM

1 3

OMIT

7 9

PP

OMIT

PP6903_RF P2MM-NSM PP

BB_TO_LAT_ANT_DATA

PP

1 7

1

SHIELD_SLEEP_CLK_32K

PP

3 6

PP

P2MM-NSM

BB_TO_LAT_ANT_SCLK

PP

SM

1 7

OMIT

PP

1

BB_TO_STROBE_DRIVER_GSM_BURST_IND 1 7

PP

PP

7 18 19

PP6917_RF

OMIT

90_USB_BB_DATA_P

1 6 20

1

ICEFALL

PP6977_RF P2MM-NSM SM

AP_TO_BB_COREDUMP

1 7 PP

OMIT

P2MM-NSM

1

OMIT

P2MM-NSM

SM PP

SM 1 7

SM

75_RFFE6_SCLK

7 20

P2MM-NSM

BB_TO_AP_RESET_DETECT_L

PP6931_RF

P2MM-NSM 1

1

OMIT

OMIT

PP6935_RF

SIM1_CLK

PP6974_RF

SM

PP6933_RF

SM

1

OMIT P2MM-NSM

P2MM-NSM PP

SM

1 7

PP6930_RF

PP6904_RF 1

P2MM-NSM

AP_TO_BB_TIME_MARK

OMIT

OMIT

OMIT

1

7 20

PP6973_RF

SM

SM

SM

1

P2MM-NSM

P2MM-NSM

SIM1_RST

OMIT

PP6929_RF

PP6914_RF

1

1

90_USB_BB_DATA_N

1 6 20

OMIT

SM

PP6936_RF

PP

1

UART_BB_TO_WLAN_COEX

OMIT

P2MM-NSM PP

1

PP7500_RF

SM

SM

PP

SM

B

PP6978_RF P2MM-NSM

1 7 20

1

P2MM-NSM

AP_TO_ICEFALL_FW_DWLD_REQ

1 20

OMIT

75_RFFE6_SDATA

PP6918_RF P2MM-NSM

PP6938_RF

SM PP

SE2_READY

1 20

B

OMIT

1

UART_WLAN_TO_BB_COEX

PP6979_RF

PP7501_RF

SM

SM

P2MM-NSM

P2MM-NSM SM

1 7 20

OMIT

PP

1

RX-DSPDT_CTL2

PP

7 13

1

P2MM-NSM

SIM1_SWP

20

OMIT

OMIT

NFC_SWP_MUX

1 20

P2MM-NSM

SM

PCIE

1

PP7502_RF

P2MM-NSM PP

PP

OMIT

PP6980_RF

P2MM-NSM

1

7 18 19

OMIT

PP6915_RF

PP

1

SM

SE2_SWP

20 PP

OMIT

1

SE2_PWR_REQ

1 20

OMIT

SM PP

1

90_PCIE_AP_TO_BB_REFCLK_P

PP6981_RF

1 6

P2MM-NSM

OMIT

SM PP

PP6916_RF

1

ICEFALL_LDO_ENABLE

1 20

OMIT

P2MM-NSM SM PP

1

90_PCIE_AP_TO_BB_REFCLK_N

1 6

OMIT

PCIE GND PP6970_RF

PP6971_RF

SM

SM

P2MM-NSM

A

PP

OMIT

1

P2MM-NSM PP

A

1 PAGE TITLE

OMIT

TEST POINTS & BOOT CONFIG DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

69 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

78 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

8

7

6

5

4

3

2

1

TDD TRANSMIT 2G PA

D

D

FL7001_RF 600-OHM-25%-0.1A

PP_PA_VBATT

1

19 16

2

PP_VPA_APT

2GPA_VBATT

16

0201-1

C7004_RF

1

1.0UF

27PF

VBATT

1 C7007_RF

2.2UF

2.2UF

SKY77363 9

IN

50_XCVR1_TX_G850_G900_PA_IN

7 LBRFIN

9

IN

50_XCVR1_TX_G1800_G1900_PA_IN

12 HBRFIN

19 18 16 14 13 12 7 4

IN

19 18 17 7

BI

19 18 17 7

IN

20% 2 6.3V X5R-CERM 0201-1

1 C7008_RF 1 C7001_RF

18PF 2% 2 16V CERM 01005

LGA

C7011_RF 27PF 1

50_TX_G850_G900_PA_OUT

LBRFOUT

1

HBRFOUT

6

1 C7009_RF

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

11 VIO 9 SDATA 10 SCLK

PP_1V8_LDO15 75_RFFE6_SDATA 75_RFFE6_SCLK

0.1UF 20% 2 6.3V X5R-CERM 01005

VCC

GSMPA_RF

GND

C7017_RF 27PF

13

1

5% 2 16V NP0-C0G 01005

5% 6.3V NP0-C0G 0201

1

50_TX_G1800_G1900_PA_OUT

1 C7010_RF

USID=0X5

2

C7012_RF 27PF

EPAD 2 4 5

C

1 C7006_RF 20% 2 6.3V X5R-CERM 0201-1

5% 16V 2 NP0-C0G 01005

8

20% 2 6.3V X5R 0201-1

C7005_RF

3

1

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

2

5% 6.3V NP0-C0G 0201

50_TX_G850_G900_PA_OUT_M OUT

19

1 C7013_RF

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

C 50_TX_G1800_G1900_PA_OUT_M OUT

19

MB HB TDD PA

1 C7014_RF

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

PP_1V8_LDO15 75_RFFE6_SDATA 19 16

IN BI

4 7 12 13 14 16 18 19 7 17 18 19

PP_QPOET_VCC_PA 1 20% MF

IN

0.00

1

+/-0.1PF 2 16V NP0-C0G 01005

SCLK 13

SDATA 12

VIO 14

VCC2 9

VCC1 8

C7015_RF 5.6PF

TDD_PAD_VCC1

VBATT 11

+/-0.1PF 2 16V NP0-C0G 01005

7 17 18 19

R7002_RF

01005

MLB_PA_VBATT

75_RFFE6_SCLK

1 1/32W

19

C7016_RF

5.6PF

TDDPA_RF

B

9

9

IN

50_XCVR0_TX_B34_B39_PA_IN

3

RFIN_MB

IN

50_XCVR0_TX_B38_B40_B41_PA_IN

5

RFIN_HB

B

AFEM-8065-AP1 LGA-1 ANT

11

OUT

50_XCVR0_B38_B40_B41_PA_PRX

27

RX_B38_B40_B41

11

OUT

50_XCVR0_B34_B39_PA_PRX

25

RX_B34_B39

16 50_TDD_PA_ANT_M

OUT

19

THRM_PAD 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

1 2 4 6 7 10 15 17 19 21 22 24 26 28 23 20 18

GND

USID=0XF

A

SYNC_DATE=04/17/2015 PAGE TITLE

PAGE_TITLE=TDD TRANSMIT DRAWING NUMBER

Apple Inc.

051-00482 REVISION

8.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

PAGE

70 OF 72

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SHEET

79 OF 81

IV ALL RIGHTS RESERVED

8

7

6

5

4

3

2

1

SIZE

D

A

7

6

R7107_RF 0.00

1 C7105_RF

1

LB_PA_VBATT R7108_RF DEFAULT_CAPACITOR_1e+06pF_2_1 0.00

2

0% 1/32W MF 01005

1

C7103_RF

1 C7104_RF

1.0UF

18PF 2% 2 16V CERM 01005

0% 1/32W MF 2 01005

D

LB_SNUBBER

1

68PF

2% 2 6.3V NP0-C0G 01005

C7126_RF

1 C7127_RF

33PF

0.033UF 20% 2 4V X5R-CERM 01005 NOSTUFF

5% 2 16V NP0-C0G-CERM 01005

NOSTUFF

NOSTUFF

1

9

IN IN

50_XCVR1_TX_B8_B20_B26_B27_PA_IN

2

50_XCVR1_TX_B12_B13_B28_PA_IN

3

C7101_RF

0.00

1

2 1/32W MF 01005

13

11

50_TX_G850_G900_PA_OUT_M

18

OUT

50_LB_DRX

12

LB_DIV

50_XCVR1_B8_B26_B27_PA_PRX

26

LB_RX0

25

LB_RX1

24

VLB_RX0

OUT

NC 11

OUT

50_XCVR1_B12_B13_B20_B28_B29_PA_PRX

NC

23

2G_TX

1

C7128_RF

1 C7129_RF

1 C7133_RF

33PF

0.033UF 20% 2 4V X5R-CERM 01005 NOSTUFF

0.033UF 20% 2 4V X5R-CERM 01005

5% 2 16V NP0-C0G-CERM 01005

1

IN

4 7 12 13 14 16 18 19 7 12

BI IN

7 12

D

R7101_RF 18PF

1

50_LAT_LB_PA_ANT

2

50_LAT_LB_COMBINER_IN

2% 25V C0H-CERM 0201

1

1

C7111_RF

LB PA

ANT1 16

BI

12

C7120_RF 1.0PF

22NH-3%-0.25A

IN

PP_1V8_LDO15 75_RFFE7_SDATA 75_RFFE7_SCLK

2 01005

0%

824-915

+/-0.1PF 2 25V C0G 201

0201 18

2

NOSTUFF

LGA1

RFIN1

1/32W MF 01005

10% 2 10V CERM 01005

SKY78100-14

RFIN0

0%

180PF

LBPA_RF 9

0.00

1

C7130_RF

1

LB_PAD_VCC1

VBATT 7

20% 2 6.3V X5R 0201-1

18PF 2% 2 16V CERM 01005

R7111_RF

SCLK 9

1

VIO 10

PP_PA_VBATT

VCC1 41

19 18 16

R7112_RF 1

PP_1V8_LDO15_PA 75_RFFE7_SDATA_PA 75_RFFE7_SCLK_PA

1% 1/32W MF 2 01005

DEFAULT_RESISTOR_0.001OHM_2_1

2

10-OHM-1.1A

1.00

DEFAULT_RESISTOR_0.001OHM_2_1

3

R7114_RF

R7130_RF

SDATA 8

PP_QPOET_VCC_PA

NOSTUFF 1

VCC2 40

19 18 16

4

OMIT_TABLE

2

ANT2 14

1

50_UAT_LB_PA_ANT

VLB_RX1

R7102_RF 0.00

1 C7112_RF

43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

1 4 5 6 11 13 15 17 19 20 21 22 27 28 29 30 31 32 33 34 35 36 37 38 39 42

1% 1/20W MF 0201

50_UAT_LB_COMBINER_IN

BI

12

824-915

1 C7121_RF

18PF 2% 25V 2 C0H-CERM 0201 NOSTUFF

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

THRM_PAD

GND

2

NOSTUFF 1

USID=0XD

R7131_RF 1.00

19 18 16

PP_QPOET_VCC_PA

1% 1/32W MF 2 01005

DEFAULT_RESISTOR_0.001OHM_2_1

MLB_TDD_SNUBBER

R7113_RF 0.00

2

18

0% 1/32W MF 01005

1

MLB_PA_VBATT

C7113_RF

1 C7114_RF

1.0UF

18PF 2% 2 16V CERM 01005

RXFIL_RF BAW-B40F-RX

9

IN

QM21140 LGA

2

50_XCVR0_TX_B11_B21_PA_IN

2% 6.3V 2 NP0-C0G 01005

PP_1V8_LDO15 75_RFFE6_SDATA 75_RFFE6_SCLK

NOSTUFF

VBATT 25

20% 2 6.3V X5R 0201-1

C

C7131_RF 68PF

18PF 2% 2 16V CERM 01005

VIO 22

1

PP_PA_VBATT

1

VCC2 27

19 18 16

VCC1 28

C

1 C7117_RF

IN BI IN

4 7 12 13 14 16 18 19 7 17 18 19 7 17 18 19

SCLK 23

FDD TRANSMIT

5

SDATA 24

8

MLBPA_RF HRPDAF025

RFIN_MLB

LGA

1

R7105_RF 0.00

OMIT_TABLE 19

1 B40RXOUT

50_XCVR0_B40B_PA_PRX

B40ANT 4

50_XCVR0_B40_PA_PRX_EXT_FIL

OUT

MLB PA

6 5 3 2

1

1

L7122_RF

L7123_RF 1.0PF

4.7NH-3%-0.270A

11

+/-0.1PF 2 16V NP0-C0G 01005

01005

OUT

11

OUT

50_XCVR0_B11_B21_PA_PRX

20

50_XCVR0_B11_B21_PA_DRX

18

ANT1 14

50_LAT_MLB_PA_ANT

ANT2 12

50_UAT_MLB_PA_ANT

1 C7122_RF

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

PRX

50_LAT_MLB_G1800_G1900_PA_RX BI

11 19

R7106_RF

1428-1463

1.8NH+/-0.1NH-0.8A

DRX

1428-1463

1% 1/20W MF 0201 OMIT_TABLE

11

GND

2

1

2

2

50_UAT_MLB_COMBINER_IN BI

12

0201

OMIT_TABLE THRM_PAD

GND

B

1

C7123_RF

B

NOSTUFF 1

R7132_RF 1.00

DEFAULT_RESISTOR_0.001OHM_2_1

MBHB_SNUBBER

R7109_RF

C7106_RF

1 C7108_RF

1.0UF

18PF 2% 2 16V CERM 01005

0% 1/32W MF 2 01005

9

IN

9

IN

18 19 11

13

A

IN OUT

OUT

OUT

11 11 11

OUT

11

OUT

11

RFIN_GSM RFIN_MB RFIN_HB

2% 2 6.3V NP0-C0G 01005

PP_1V8_LDO15 75_RFFE6_SDATA 75_RFFE6_SCLK

NOSTUFF

BI IN

4 7 12 13 14 16 18 19 7 17 18 19 7 17 18 19

27

28

26

IN

MBHBPA_RF

R7103_RF

1.8NH+/-0.1NH-0.8A

AFEM-8055-AP1

19

11

34 31 32

68PF

SCLK

50_TX_G1800_G1900_PA_OUT_M 50_XCVR0_TX_B1_B3_B4_B25_PA_IN 50_XCVR0_TX_B7_B30_PA_IN

VBATT

IN

C7132_RF

MBHB_FDD_PAD_VCC1 29

20% 2 6.3V X5R 0201-1

0.00

18PF 2% 2 16V CERM 01005

VIO

1

R7110_RF

1

38

0% 1/32W MF 01005

18

1

MBHB_FDD_PA_VBATT DEFAULT_CAPACITOR_1e+06pF_2_1

1 C7110_RF

VCC2

2

37

1

VCC1

PP_PA_VBATT

19 18 16

0.00

OMIT_TABLE

USID=0XB

1% 1/32W MF 2 01005

SDATA

PP_QPOET_VCC_PA

19 18 16

+/-0.05PF 2 25V CERM 0201

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

1 3 4 5 6 7 8 9 10 11 13 15 16 17 19 21 26

0.6PF

7 8

50_TDD_PA_ANT_M 50_LAT_MLB_G1800_G1900_PA_RX

LGA

50_LAT_MB_HB_DRX 50_XCVR0_B40B_PA_PRX

10 11

MB_HB_DRX DCS_PCS_RX

50_XCVR0_B1_B4_PA_PRX 50_XCVR0_B3_PRX-DSPDT_OUT 50_XCVR0_B7_PA_PRX

1 3 5 17 19 21

RX_B1 RX_B3 RX_B7 RX_B4 RX_B25 RX_B30

50_XCVR0_B4_PA_PRX 50_XCVR0_B25_PA_PRX 50_XCVR0_B30_PA_PRX

1

50_LAT_MB_HB_PA_ANT

TRX2 TRX3

2 50_LAT_MB_HB_COMBINER_IN 0201

MB/HB PA

ANT1

14

ANT2

13

1710-2690

1 NOSTUFF C7118_RF 18PF 2% 2 25V C0H-CERM 0201 R7104_RF

1 C7124_RF

2NH+/-0.1NH-0.6A 1

50_UAT_MB_HB_PA_ANT

2

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

OMIT_TABLE

C7119_RF

BI

+/-0.05PF 2 25V C0G 0201

OMIT_TABLE

43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

2 4 12 15 16 18 20 22 23 24 25 30 33 35 36 39 40 41 42 6 9

EPAD

12

1710-2690 1 C7125_RF

18PF 2% 2 25V C0H-CERM 0201 NOSTUFF

0.1PF

GND

SYNC_DATE=04/17/2015

50_UAT_MB_HB_CPL_IN

0201 1

12

BI

USID=0XE 8

7

6

5

4

3

2

1

A

8

7

6

5

4

3

2

1

SWP MUX

ICEFALL

D PP1V8_ICEFALL_LDO

20

20 7 1

1 C7501_RF

PP1V8_SDRAM

1 7 20

OUT

B3 A3 B1 A1 A2

NC NC NC NC NC

VDDO_NFC E1

1C7523_RF

1UF 20% 2 10V X5R 0201 SE2

SE2_PRESENT

1 C7524_RF

1UF 20% 2 10V X5R 0201 SE2

NC

NC SE2_SWP

NFC_SWP

1

2

R7512_RF

1 17

IN

SE2LDO_RF

SE2 OMIT_TABLE

17 1

2 6.3V X5R-CERM

R7511_RF IN

2

PP1V8_ICEFALL_LDO

0201-1 SE2 OMIT_TABLE

20

LP5907UVX-1.825-S DSBGA A1 VIN VOUT A2

PP_VDD_MAIN

20 16 4 3 1

20

C

GND

2.2UF 20%

2 6.3V X5R-CERM

1% 1/20W MF 0201 NOSTUFF

PP1V8_ICEFALL_LDO

B1 VEN

ICEFALL_LDO_ENABLE

1 C7529_RF

20%

1

17 20

NC

2.2UF

PP1V8_SDRAM

SIM1_SWP

ICEFALL LDO

1 17

1 C7530_RF

20 7 1

B0 3

NFC_SWP_R

OMIT_TABLE

0.00

GND 2

OMIT_TABLE

B5 D5 C4 D1

1% 1/32W MF 2 01005

17 20

0% 1/32W MF 01005 NFC

17 20

SE2_PWR_REQ

TCAL_CLK B2

10K

C

IN

IN

VSS VSS VSS VSS

1

SE2_SWP

VER 1

R7510_RF 0.00

NC

REG_PU D3

C1 NC

5 VCC 4 A

AP_TO_ICEFALL_FW_DWLD_REQ

DWP E2 SWP E3

E4 GPIO_0 D4 GPIO_1

SE2_READY

17 1

SWPMX_RF

OMIT_TABLE

DB_RX B4 DB_TX A4

WLBGA

NFC_SWP_MUX

IN

NLAS3257CMX2TCG DFN 6 S B1 1

OMIT_TABLE

BCM20211CP

SPI_CLK SPI_CS SPI_INT SPI_MISO SPI_MOSI

17 1

0.1UF 20% 2 6.3V X5R-CERM 01005 SE2

SE2_RF

R7506_RF 4.99K 1% 1/32W MF 2 01005 NFC OMIT_TABLE

PP1V8_SDRAM 1 C7525_RF

1

1

1

VDDO_HOST_2 A5

OMIT_TABLE

NOSTUFF

VDDC C5 VDDC E5

1UF 20% 2 10V X5R 0201 SE2

VDD1P8_BYP D2

0.1UF 20% 2 6.3V X5R-CERM 01005 SE2 OMIT_TABLE

1UF 20% 2 10V X5R 0201 SE2

VDD1P2 C2

1C7201_RF

VDD1P8 C3

1C7528_RF

VDD_SE2_1V8 VOLTAGE=1.80V VDD_SE2_1V2 VOLTAGE=1.20V

B2

D

0201-1 SE2 OMIT_TABLE

1

C7531_RF

100PF

5% 2 6.3V CERM 01005

OMIT_TABLE

DEBUG CONNECTOR

SIM CARD CONNECTOR 20 17 7

SIM1_IO

20 17

SIM1_SWP J_DEBUG

20-5857-036-001-829 F-ST-SM 1

9

SIM_DETECT 8

SIM_DETECT_GND

SIM1_DETECT

OUT

7 17 20

DZ6905_RF SG-WLL-2-2

DZ6902_RF SG-WLL-2-2

ESD202-B1-CSP01005

ESD202-B1-CSP01005

SIM

20 17 7

3

IN

CLK

IO 7

J_SIM_RF

SIM1_IO

BI

2 17 6 1

7 17 20

20 5 4

SIM1_RST

IN

1

VDD_SIM1 1 C6900_RF

B

F-RT-SM SIM

SIM1_SWP 2

VCC GND

DZ6901_RF 2

17 3 1

DZ6900_RF

20 17 7

SIM1_RST

20 17 7

OUT

SIM1_CLK

12V-33PF 01005-1

1

SIM

1 C6901_RF

100PF

SIM

1

5% 2 16V NP0-C0G 01005 SIM

1

DZ6903_RF SG-WLL-2-2

DZ6904_RF SG-WLL-2-2

ESD202-B1-CSP01005

ESD202-B1-CSP01005

SIM 2 1

BI

0201

VDD_SIM1

20 5 4

17 20

BI

5.5V-6.2PF

1

2.2UF

20% 2 6.3V X5R-CERM 0201-1 SIM

RESET

5 10 11 12 13 14 15 16

20 17 7

17 6 1

SWP 6

3 1

OUT

6 1

OUT

6 1

1% 1/32W MF 2 01005 SIM

SIM 2

4 1

PP_1V8_LDO6

17 7 6 5 4

AP_TO_BB_RESET_L SWD_AP_TO_MANY_SWCLK SWD_AOP_BI_BB_SWDIO

OUT

R6900_RF

15.00K

PMU_TO_BB_USB_VBUS_DETECT 90_USB_BB_DATA_P 90_USB_BB_DATA_N AP_TO_BBPMU_RADIO_ON_L

17 3 1

RCPT-WIDE-HSG-THICK-PIVOT 2

PP_VDD_MAIN

20 16 4 3 1

SIM

2

SIM1_CLK

41

1

PP_VDD_BOOST

38

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

39

40

VDD_SIM1 SIM1_RST SIM1_CLK SIM1_IO SIM1_SWP SIM1_DETECT

4 5 20

IN IN BI

7 17 20 7 17 20 7 17 20

17 20

OUT

7 17 20

B

BB_JTAG_RST_L UART_BB_TO_WLAN_COEX UART_WLAN_TO_BB_COEX

OUT IN IN

6 17 1 7 17 1 7 17

42

SIM1_IO

20 17 7

37

NOSTUFF

1

R6904_RF 100K

1% 1/32W MF 01005 2 SIM

SIM1_DETECT

7 17 20

A

A

8

7

6

5

4

3

2

1