Laptop Power Sequencing

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Laptop Power sequencing Notebook INTEL Timing (SEQUENCE) Notebook INTEL Timing (SEQUENCE)

Usually the boot process NTEL notebook chipset (the red part is a circuit diagram Chaturvedi use) 1, in the absence of any electrical equipment when the power supply (no battery and power), by 3V button battery to generate VCCRTC supply Southbridge RTC circuitry to Keep running and keep the CMOS internal time information 32D768 RTC circuit measuring points: VCCRTC-DCPRTC / RTCRST # / SRTCRST # / 32.768KHz BATLOW # 3.3V EC to Southbridge 2. After inserting the battery or adapter to produce a common point, then generates EC standby power supply (usually linear supply 3.3V Current 0.08A) isolation protection Circuit common small value resistor 3 to give the standby power supply EC (AVCC / VCC0) and get standby clock, (32.768KHZ 3.3V) and reset (3.3V EC_RST # / ECRST # WRST # VCC_POR #

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VCC1_RST #) after reading (BIOS) configuration itself pin (oscilloscope waveform can be measured) 4, if the EC detected power adapter (generally a good signal from the charging chip ACOK conversion ACIN / AD_IN / AC_IN / RI2 / WUI1 / GPD1 / ACAV_IN), Southbridge will automatically send a signal to open the standby voltage (VCCSUS3_3, V5REF_SUS), then sent Southbridge called "RSMRST #" (3.3V) to be electromechanical Good pressure signaled Southbridge standby voltage normal; if the EC does not detect the adapter (battery mode), EC need to receive the switch trigger, only to open Southbridge standby power supply to save power current 0.020.03 5, press the switch, EC received signal after the switch (connected to the EC names GPIO03 / GPIO06 PWUREQ # / GPC7 / PWR_SW # - Hua Shuo TMRI0 / WUI2 / GPC4 / EC_GPXIOD3 / KBC_PWRBTN #) delay sending a high - low - high power signal to PWRBTN # Southbridge no power is also affected,: //www.wendangwang.com/doc/c1d84f2f00ff6148585c6ed4par Lid switch control (COVER_SW # / LID_SW #) 6, Southbridge received successively pulled after PWRBTN # signal SLP_S5 #, SLP_S4 #, SLP_S3 # signal, SLP_S5 / S4 # memory power supply and control the generation 3.3VSUS (VDIMM) (can directly control, the control can also go through

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EC) (0.05A DDR1 2.5V DDR2 1.8V DDR3 1.5V), SLP_S3 # generates control 3.3V_RUN, 5_RUN, bridge power supply (1. * V) bus-powered, (VCCP) 0.2A-0.3A 1.05V) graphics card power supply (, (0.50.7A 1. * V) VGPU_CORE) (et (can directly control , you can also go through the EC control) 7, signaled EC (1. * V) or other conversion circuit to turn the CPU core voltage (VCORE) alone was no current 0.6A, (there was only a current increase 0.3-0.5A). At this point, the whole voltage has been fully opened. 8, after the normal CPU power, CPU power management chip emits PG eventually served Southbridge VRMPWRGD / SYS_PWROK / MEPWROK foot (3.3V CPU Good power supply signal) 9, the CPU power supply is normal to start the clock circuit chip through the conversion, the brightest generated clock (945 or less, and HM55 series is the CPU power supply CLK_EN # Directly start the clock; 965 and 945 series after VRMPWRGD to Southbridge, Southbridge issue CK_PWRGD start the clock 3.3V) 10, Southbridge received power, clock, VRMPWRGD, and received EC or circuit-switched power supply circuit to PWROK (3.3V), will be issued Southbridge CPUPWRGD / PROCPWRGD / DRAMPWROK 1.05V) (to inform its CPU core voltage has been successfully opened, and also issued PLTRST # 3.3V) (

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And PCIRST # (3.3V) signal 11, North Bridge after receiving PLTRST #, issued CPURST # (1.05V 0.7A) signal to the CPU, CPU started to work hard to complete the start, soft start start http://www.wendangwang.com/doc/c1d84f2f00ff6148585c6ed4 12, CPU start addressing ADS #, read BIOS data 13, initialize the memory 0.7-0.8A 14, initialization graphics 0.9-1.1A 15, a display LOGO 16, the peripheral display Notebook book 110 - timing diagram to explain: system status: G3: power to the entire system are closed S5: shutdown state S4 sleep state S3: sleep state S0: switched on INTEL timing signal explained: VCCRTC: Southbridge RTC circuit power, 3V, to Southbridge internal CMOS chip (RAM) power supply RTCRST #: Reset signal Southbridge RTC circuit, 3.3V ICH9 later added a RTC reset signal. Name is SRTCRST # 32.768KHZ: Southbridge got VCCRTC and RTCRST # after the

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power supply to the crystal, the crystal Shake-vibration. Crystal feet voltage between 0.1-0.5 V5REF_SUS: 5V standby voltage VCCSUS3_3: 3.3V standby voltage S5 state VCCSUS1_05: Southbridge generated internally to its own power supply 1.05V, do not control RSMRST #: Notify Southbridge 3.3V standby voltage normal voltage 3.3V, controlled by an external circuit SUSCLK: Southbridge issued after receiving RSMRST # 32K clock, most machines do not use, can be ignored PWRBTN #: POWER BUTTON, the power button. 3.3V-0-3.3V pulse signal SLP_S5 #: 3.3V, Southbridge exit off the bridge control signal power supply EC has SLP_S4 #: 3.3V, Southbridge exit control signal sleep state. (General S5 # and S4 # using only one power supply is used to control the generation of memory, another empty) SLP_S3 #: 3.3V, Southbridge exit sleep state control signal. (Generally used to control the bridge power supply, bus-powered, single significant power, CPU power supply, etc.) VDIMM: memory power supply VCORE / VCC: power supply means bridge, bus-powered, single significant power, CPU supply http://www.wendangwang.com/doc/c1d84f2f00ff6148585c6ed4 electricity VRMPWRGD: Southbridge inform the CPU power

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supply is normal, 3.3V CLK GEN: clock chip to work, to issue the brightest clock PWROK: Notify Southbridge supply are normal at this time (SLP_S3 # task completion) 3.3V CPUPWRGD: PG Southbridge issued to the CPU. 1.05V PLTRST #: platform reset, first reset Southbridge issued generally to onboard chip, such as Northbridge, EC and other 3.3V PCIRST #: PCI reset, the second reset Southbridge issued generally to MINI slot 3.3V CPURST #: Northbridge after receiving PLTRST #, to the CPU Reset, 1.05V no original platform overhaul reset key measurement point is located number 1, 1.5V main power supply Southbridge measured in _____ 2, 3.3V main power supply Southbridge measured in _____ 3, 1.05V Southbridge bus-powered measurement in _____ 4, Southbridge 33M clock measuring points _____ 1.6V 5, PWROK Southbridge measuring point in _____, _____ V normal voltage 6, VRMPWRGD Southbridge measuring point in _____, _____ V normal voltage

ACPI Advanced Configuration and Power Management Interface

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ACPI power and control signals G3: standby power off state EC S5: G3 electricity there, more power Southbridge S3: G3 S5 have electricity, more memory power S0: G3 S5 S3 S0 all-electric 3VSB-3.3V standby voltage to within the Southbridge controller ACPI / NIC / PCI wake like to provide power 3VSB name three chipset INTEL: VCCSUS3_3 Nvidia: 3.3V_DUALAMD: S5_3.3V / VDDIO_33_S RSMRST # - normal standby voltage signal, voltage 3.3V Intel, AMD: RSMRST Nvidia: PWRGD_SB SLP_S3 # / SUSB # (Asus use), SLP_S4 # http: //www.wendangwang.com/doc/c1d84f2f00ff6148585c6ed4/SUSC #,SLP_S5# Low into the S3, S4, S5 signal state 3 signal S0 state are invalid PWRBTN # - POWER BUTTON voltage button, shutdown, low PWRBTN # signal, ACPI will in turn set high SLP_S5, SLP_S4, SLP_S3 To 3.3V. If PWRBTN # 4 seconds low, the system will be forced into S5 state

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C3 four states STPCLK #: Southbridge distributed CPU, stop CPU internal clock, active low, the host normal working, this signal is high will cause the code does not run STP_CPU #: Southbridge chip distributed clock, external clock down the CPU, low active, The host normal working, this signal is high (no CPU clock) DPRSTP #: Southbridge distributed CPU, it said it is in Deep Sleep mode, active low, the host normal working, this signal is high (cause code does not run) DPRSLPVR: South Bridge to the CPU power supply IC, directed into Deep Sleep mode, active high, is low when the host is working properly (causing no CPU power) ACPI C-state

Notebook power supply is divided into four levels --- important supply Name: Charles schematic convenient Chaturvedi Dell S3 S5 out simultaneously G3 --- EC standby power supply voltage AVCC VCCA just plug in the power generated when the general power supply switch and EC, are usually produced in a linear fashion S5 --- Southbridge standby power supply, VCCSUS3_3 V5REF_SUS supplied under Southbridge VCCSUS3_3 off electricity, usually generated PWM mode

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S3 --- memory power supply VDD S3 sleep state, The main power supply S0 --- bridge core supply VCC1_5_B machine uptime needed electrical power S0 state, including power supply bridge, bus, CPU power supply Bus-powered VCCP by first looking to find CPU power supply bus and bridge CPU power supply VCC Sometimes, you can put PWM mode G3 or S5 state called out 3V 5V system power supply: //www.wendangwang.com/doc/c1d84f2f00ff6148585c6ed4r IBM voltage referred to as: G3 SW S5 M S3 A S0 B INTEL Chipset Series Five different timings Voltage layered G3 S5 S3 S0 VCCRTC "" "" SLP_S3 #

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SLP_M # bridge module ME issued a control signal for turning on the power supply, 3.3V If the motherboard has ME firmware AMT function is turned on, the signal will be generated before the trigger; closed AMT function timing and SLP_S3 # Consistency If the motherboard does not support AMT feature, SLP_M # vacant not used SLP_LAN #: LAN subsystem sleep control, power control card, synchronized with the timing SLP_M # VCCME: 1.05V ME supply units (ie, to achieve power AMT function), controlled by SLP_M #. When SLP_M # vacant (no ME motherboard firmware), Power VCCME directly S0 state VDIMM: refers to the memory power supply, controlled by SLP_S4 # VCC: refers to the main power supply bridge, etc. S0 state voltage controlled SLP_S3 # VCC_CPU: the motherboard to the CPU core power supply, controlled by SLP_S3 #, there is a delay SYS_PWROK: by the power management chip CPU is sent bridge 3.3V high level, equivalent to VRMPWRGD

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PWROK: Board issued 3.3V high level bridge, showing S0 state voltages are OK MEPWROK: ME good power module, 3.3V, when open the AMT function, MEPWROK by the AMT power control, closed AMT function, MEPWROK Synchronized with PWROK LAN_RST #: Motherboard Integrated NIC reset signal sent to the bridge, the card can be understood as power-good signal Clock Chip Outputs: clock chip is turned on, the output clock of each group PROCPWRGD: Bridge issued to the CPU PG, represents OKS CPU's core voltage http://www.wendangwang.com/doc/c1d84f2f00ff6148585c6ed4 DRAMPWROK: bridge to the CPU for PG, notify the CPU, memory, power supply module OK PLTRST #: Bridge issued platform reset 3.3V, converted as the CPU reset INTEL chipset series six different timings VCCRTC: RTCRST # / SRTCRST # VCCDSW3_3: Deep Sleep Board to provide a wake-up bridge power supply (Deep Sleep Well), 3.3V. It does not support deep sleep, this electricity Pressure and connected together VCCSUS3_3

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DPWROK: Board to bridge 3.3V high, indicating that the power VCCDSW3_3 good, 3.3V. Try not support sleep. This signal Even together RSMRST # SLP_SUS #: Deep Sleep mode indication signal can be used to open the S5 state voltage, such as VCCSUS3_3 not support deep sleep. SLP_SUS # vacant VCCSUS3_3: Board to bridge the standby power supply 3.3V RSMRST #: Board to bridge 3.3V high level ACPI a reset signal SUSCLK: Bridge issued 32.768KHz clock, but not necessarily the motherboard uses PWRBTN #: falling bridge receives a trigger signal, 3.3V-0V3.3V, can exit the sleep state notification bridge SLP_S5: rear axle receive PWRBTN #, set high SLP_S5 # to 3.3V, showing off Exit SLP_S4: bridge set high SLP_S4 # to 3.3V, showing out of hibernation "" "" VDIMM: memory power supply VCC: axle main power supply, etc.

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CPU SVID: Serial VID signal CPU issued for adjusting the CPU core voltage and power control set was After the CPU get PROCPWRGD, will be issued SVID VCCCORE_CPU: Motherboard CPU power supply to the core SYS_PWROK: by the power management chip CPU is sent bridge 3.3V high level, equivalent to VRMPWRGhttp: //www.wendangwang.com/doc/c1d84f2f00ff6148585c6ed4D PWROK: APWROK: ME module power is good, open AMT module DRAMPWROK: bridge to the CPU for PG 25MHz Crystal Osc: 6 series chipset no clock chip, increasing the 25M crystal bridge to bridge internal clock module provides the reference frequency PCH Output Clocks: bridge output clock of each group PROCPWRGD: bridge to the CPU for PG, indicates that the CPU core voltage OK PLTRST #: Bridge platform issued reset 3.3V, converted paper consists fast as the CPU reset dimension - Dream struggle - Production

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