Spartan 3e

SPARTAN 3E DEVELOPMENT BOARD Model No : (VPTB - 05) (Specially Designed for Polytechnic Syllabus - Kerala)

User Manual Version 1.0

Technical Clarification /Suggestion : N/F Technical Support Division, Vi Microsystems Pvt. Ltd., Plot No :75, Electronics Estate, Perungudi, Chennai - 600 096, INDIA. Ph: 91- 44-2496 1842, 91-44-2496 1852 Mail : [email protected], Web : www.vimicrosystem.com

CONTENTS CHAPTER - 1

Introduction

1

CHAPTER - 2

Clock Source

4

CHAPTER - 3

Switches & LEDs

7

CHAPTER - 4

Character LCD Screen

8

CHAPTER - 5

RS232 Serial Port

9

CHAPTER - 6

PS/2 Mouse /Keyboard Port

10

CHAPTER - 7

Analog to Digital Converter & Digital To Analog Converter

12

CHAPTER - 8

PWM Generations

14

CHAPTER - 9

Connector Details

16

CHAPTER-10

VHDL Code for VPTB-05

18

CHAPTER-11

Add on Card Programs for VPTB - 05 Using Polytechnic Syllabus Kerala

42

EXPERIMENT - 1A Verilog Code for Basic Logic Gates in Dataflow Style of Modelling

42

EXPERIMENT - 1B Verilog Code for 4 To1 Multiplexer Using Behavioral Style of Modelling

44

EXPERIMENT - 1C Verilog Code for Decoder 3 to 8 Using Behavioral Modelling

46

EXPERIMENT -1D Verilog Code for Full Adder Using Data Flow Style of Modelling 49 EXPERIMENT -1E Verilog Code for 4 Bit Full Adder Using Structural Modelling EXPERIMENT -1F

Verilog Code for 4 Bit Magnitude Comparator Using Dataflow Modelling

51

54

EXPERIMENT -1G Verilog Code for Set Reset(SR)flip-flop in Data Flow Modeling

56

EXPERIMENT -1H Verilog Code for T Flip Flop Using Sync Reset Using Behavioral Modelling for FPGA Kit Implementation

58

EXPERIMENT -1I

EXPERIMENT -1J

Verilog Code for Ripple Counter Using Structural Modelling for FPGA Kit Implementation

61

Verilog Code for Traffic Light Controller Using Behavioral Modelling

65

EXPERIMENT -1K Verilog Code for Bidirectional Switch Using Dataflow Modelling 69 EXPERIMENT -1L Verilog Code for Synchronous Counter with Clear and Count Enable Using Behavioral Modelling

71

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

CHAPTER - 1 INTRODUCTION The Vi Microsystems Spartan-3E Low Cost Kit is a demonstration platform intended for you to become familiar with the new features and availability of the Spartan-3E FPGA family. This Kit provides a low-cost, easy-to-use development and evaluation platform for Spartan-3E FPGA designs. KEY COMPONENTS AND FEATURES Figure 1 shows the Spartan-3E Low Cost board block diagram, which includes the following components and features: *

100,000-gate Xilinx Spartan-3E XC3S100E FPGA in a 144-Thin Quad Flat Pack package (XC3S100E-TQ144) #

2,160 logic cell equivalents

#

Four 18K-bit block RAMs (72K bits)

#

Four 18x18 pipelined hardware multipliers

#

Two Digital Clock Managers (DCMs)

*

32 Mbit Intel Strata Flash

*

3 numbers of 20 pin header to interface VLSI based experiment modules

*

8 input Dip Switches

*

8 output Light Emitting Diodes(LEDs)

*

On Board programmable oscillator (3 to 200 MHz)

*

16x2 Alphanumeric LCD

*

RS232 UART

*

4 Channel 8 Bit I2C based ADC & single Channel DAC

*

PS/2 Keyboard/Mouse

*

Prototyping area for user applications

*

On Board configuration Flash PROM XCF01S

Vi Microsystems Pvt. Ltd.,

[1]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

BLOCK DIAGRAM

Figure -1

Vi Microsystems Pvt. Ltd.,

[2]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

POWERING UP THE BOARD FOR THE FIRST TIME 1. Connect Power to the Board Refer Figure- 2 2. Initialize FPGA a. Press power switch to apply power to the board b. The “Rolling lights”,”Rolling Display”, “Transmitting Spartan-3E Features” Designs is automatically loaded into the FPGA from the Flash PROM and displayed on the LEDs, LCD & Serial Port.

Figure - 2

Vi Microsystems Pvt. Ltd.,

[3]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

CHAPTER - 2 CLOCK SOURCE Spartan3 FPGA works in different Clock frequencies. User can use any frequencies as given below, PLL Oscillator Settings Default Factory settings = 20MHz For PLL, ICS525-01 or ICS525-02 is used. Select the clock settings as per the PLL in the onboard 0 1

= Shorted = Open

ICS525-01 Clock Table Between 1 to 100 MHZ Table -1 1MHz

3.6864 MHZ

4MHz

20MHz

24MHz

25.175 MHz

48MHz

66MHz

80MHz

100MHz

S2 S1 S0 R6 R5 R4 R3 R2 R1 R0

0 0 0 0 1 0 1 1 1 0

0 0 0 0 1 1 0 0 0 1

0 0 0 0 0 0 1 0 1 0

0 1 0 0 0 0 0 0 1 0

1 0 0 0 0 0 0 0 1 0

1 1 1 1 0 0 1 0 1 0

0 0 1 0 0 0 0 0 1 1

0 0 1 0 0 0 1 0 0 0

0 0 1 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1

V8 V7 V6 V5 V4 V3 V2 V1 V0

0 0 0 0 0 0 1 0 0

0 0 0 1 0 0 1 1 1

0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 0 0

1 0 0 0 1 0 1 1 1

0 0 0 0 0 0 1 0 0

0 0 0 0 1 1 0 0 1

0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 1 1

Vi Microsystems Pvt. Ltd.,

[4]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

For any other CLK frequency in between 1MHz to 100MHz use the following formula.

( VDW + 8) CLK frequency = Input frequency

*

2 (RDW + 2)(OD)

Where, Reference Divider Word (RDW) VCO Divider Word (VDW) Output Divider (OD)

= 1 to 127 (0 is not permitted) = 4 to 511 (0,1,2,3 are not permitted) = Values below

EXAMPLE To generate 12 MHz, assume Crystal + frequency or Input frequency is 20MHz. In general, VDW + 8 Clock Frequency

=

Input Frequency x 2

= (RDW + 2) (OD)

4+8 Clock Frequency

=

20 MHz

x 2

= 12 MHz (18 + 2)(2)

ICS525-01 Output Divider and Maximum Output Frequency Table Table:2

* * *

S2

S1

S0

CLK

Pin5

Pin4

Pin3

Output Divider

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

10 2 8 4 5 7 9 6

Max. Output Frequency (MHz) VDD = 5V VDD = 3.3V 0 - 700C -40 to 85 0C 0 - 700C -40 to 85 0C 26 23 18 16 160 140 100 90 40 36 25 22 80 72 50 45 50 45 34 30 40 36 26 23 33.3 30 20 18 53 47 27 24

VCO Divider Word (VDW) = V8 to V0 = 000000100 = 4 (Decimal); Reference Divider Word (RDW) = R6 to R0 = 0010010 = 18 (Decimal); Output Divider (OP) = 2 (from the table given above)

Vi Microsystems Pvt. Ltd.,

[5]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ICS525-02 Clock Table Between 3 MHZ TO 200 MHZ Table : 3

S2 S1 S0 R6 R5 R4 R3 R2 R1 R0

3.6864 MHZ 0 0 0 1 0 1 0 0 1 1

V8 V7 V6 V5 V4 V3 V2 V1 V0

0 0 0 1 0 0 1 1 1

0 0 0 0 0 0 1 1 0 1

20 MHz 0 1 0 0 0 0 0 0 0 0

24 MHz 1 0 0 0 0 0 0 0 0 1

25.175 MHz 0 1 0 0 1 1 0 1 1 1

48 MHz 1 0 0 0 0 0 0 0 0 0

66 MHz 0 0 1 0 0 0 1 0 0 0

80 MHz 0 0 1 0 0 0 0 0 0 0

100 MHz 0 0 1 0 0 0 0 0 0 0

200 MHz 1 1 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1

1 0 0 0 1 0 1 1 1

0 0 0 0 0 0 1 0 0

0 0 0 0 1 1 0 0 1

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 1 0

4MHz

ICS525-02 Output Divider and Maximum Output Frequency Table: Table : 4 S2

S1

S0

CLK

Pin5

Pin4

Pin3

Output Divider

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

6 2 8 4 5 7 1 3

Vi Microsystems Pvt. Ltd.,

Max Output Freqency (MHZ) VDD=5V VDD=3.3V -40 to 85 -40 to 85 0C 0 C 67 40 200 120 50 30 100 60 80 48 57 84 250 200 133 80

[6]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

CHAPTER - 3 SWITCHES & LEDs

Figure - 3 Power Switch The Spartan-3E Low Cost Kit has a slide power switch. Moving the power switch Up for Power On and down for power off. Configuration Switch The Spartan-3E Low Cost Kit has a push button Switch to Configure the FPGA from Xilinx Serial Flash PROM. Input Switches The Spartan-3E Low Cost Kit has 8 way Dip switches for giving inputs to the FPGA i/o lines. Dip Switch connections with FPGA Switch

Sw3(1)

Sw3(2)

Sw3(3)

Sw3(4)

Sw3(5)

Sw3(6)

Sw3(7)

Sw3(8)

FPGA Pin

p6

p18

p24

p36

p38

p41

p69

p78

Output LEDs The Spartan-3E Low Cost Kit has 8 individual surface-mount LEDs. The LEDs are Labeled L3 to L10.The cathode of each LED connects to ground. To light an individual LED, drive the associated FPGA control signal High. LED connections with FPGA LED

L3

L4

L5

L6

L7

L8

L9

L10

FPGA Pin

p33

p34

p35

p39

p43

p44

p2

p50

Vi Microsystems Pvt. Ltd.,

[7]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

CHAPTER - 4 CHARACTER LCD SCREEN The Spartan-3E Low Cost Kit prominently features a 2-line by 16-character liquid crystal display (LCD). The FPGA controls the LCD via the 8-bit data interface.

Figure - 4 Once mastered, the LCD is a practical way to display a variety of information using standard ASCII and custom characters. However, these displays are not fast. Scrolling the display at halfsecond intervals tests the practical limit for clarity. LCD Connections with FPGA LCD

D0

D1

D2

D3

D4

D5

D6

D7

RS

DIO W

CS

FPG A Pin

p54

p58

p67

p68

p70

p74

p75

p76

p51

p52

p53

Voltage Compatibility The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V.However, the FPGA’s output levels are recognized as valid Low or High logic levels by the LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVC MOS outputs provided by the FPGA meet the 5V TTL voltage level requirements. The 390Ù series resistors on the data lines prevent over stressing on the FPGA and Strata Flash I/O pins when the character LCD drives a High logic value. The character LCD drives the data lines when LCD RW is High. Most applications treat the LCD as a write only peripheral and never read from the display.

Vi Microsystems Pvt. Ltd.,

[8]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

CHAPTER - 5 RS232 SERIAL PORT

Figure - 5 The Spartan 3E Low Cost board has one RS-232 serial port. The RS-232 transmit and receive signals appear on the male DB9 connector, labeled as p8, indicated as in Figure -5. The connector is a DTE-style serial port connector available on most personal computers and workstations. Use a standard straight-through serial cable to connect the board to the PC’s serial port. Serial port connections with FPGA Serial signal

TXD

RXD

RTS

CTS

FPGA Pin

p83

p82

p85

p86

Vi Microsystems Pvt. Ltd.,

[9]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

CHAPTER - 6 PS/2 MOUSE/KEYBOARD PORT The Spartan 3E Low Cost board includes a PS/2 mouse/keyboard port and the standard 6-pin mini-DIN connector, labeled p10 on the board. Figure - 6 shows the PS/2 connector, and below table shows the signals on the connector. Only pins 1 and 5 of the connector attach to the FPGA

Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a host device, the Spartan-3 FPGA in this case. The PS/2 bus includes both clock and data. Both a mouse and keyboard drive the bus with identical signal timings and both use 11-bit words that include a start, stop and odd parity bit. However, the data packets are organized differently for a mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard. PS2 Timing Waveform

Vi Microsystems Pvt. Ltd.,

[ 10 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Keyboard Scan Code

PS2 Signals with FPGA PS2 SIGNAL FPGA PIN

Vi Microsystems Pvt. Ltd.,

PS2 CLK p81

PS2 DATA p77

[ 11 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

CHAPTER - 7 ANALOG TO DIGITAL CONVERTER & DIGITAL TO ANALOG CONVERTER The Spartan-3E Low Cost Kit includes a PCF8591, 8 Bit 4 Channel I2C based Analog to Digital Converter(ADC) and Single Channel Digital to Analog Converter(DAC) as shown in Figure-6.

Figure - 6 The PCF8591 is a single-chip, single-supply low power 8-bit CMOS data acquisition device with four analog inputs, one analog output and a serial I2C-bus interface. Three address pins A0, A1 and A2 are used for programming the hardware address, allowing the use of up to eight devices connected to the I2C-bus without additional hardware. Address, control and data to and from the device are transferred serially via the two-line bidirectional I2C-bus. The functions of the device include analog input multiplexing, on-chip track and hold function, 8-bit analog-to-digital conversion and an 8-bit digital-to-analog conversion. The maximum conversion rate is given by the maximum speed of the I2C-bus. Address Byte Each PCF8591 device in an I2C-bus system is activated by sending a valid address to the device. The address consists of a fixed part and a programmable part. The programmable part must be set according to the address pins A0, A1 and A2. MSB 1

LSB 0

0 Fixed Part

Vi Microsystems Pvt. Ltd.,

1

A2

A1

A0

__ R/W

Programmable part

[ 12 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Control Byte The second byte sent to a PCF8591 device will be stored in its control register and is required to control the device function.

PCF8591(ADC/DAC) Connections with FPGA PCF8591 SIGNALS

SCLK

SDA

FPGA PIN

p88

p87

Vi Microsystems Pvt. Ltd.,

[ 13 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

CHAPTER - 8 PWM GENERATIONS Pulse Width Modulation (PWM) is a technique to provide a logic “1" and logic “0" for a controlled period of time. Pulse Width Modulation is used in many applications such as controlling the speed of a motor. This board also used for the same application as user needs. PWM output is terminated in the Box type header. Pin Details PWM Signals

FPGA Pins

PWM1

P93

PWM 2

P94

PWM 3

P96

PWM 4

P97

PWM 5

P98

PWM 6

P103

PWM 7

P104

PWM 8

P105

Figure - 7 Translator Features Translator device is used in-between FPGA I/O lines and Box type Header to translate 3.3V to 5V and Vice-versa. *

Device used: SN74LVCC3245A

*

Bidirectional Voltage Translator

*

2.3 V to 3.6 V on A Port and 3 V to 5.5 V on B Port

*

Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage.

Vi Microsystems Pvt. Ltd.,

[ 14 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

This 8-bit (octal) non inverting bus transceiver contains two separate supply rails. The B port is designed to track VCCB, which accepts voltages from 3 V to 5.5 V, and the A port is designed to track VCCA, which operates at 2.3V to 3.6 V. This allows for translation from a 3.3-V to a 5-V system environment and vice versa, from a 2.5-V to a 3.3-V system environment and vice versa. The SN74LVCC3245A is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. Function Table INPUTS OPERATION

__ OE

DIR

L

L

B data to A bus

L

H

A data to B bus

H

X

Isolation

Translator used in this board to convert 3.3V to 5V or vice-versa. Selection of particular translator is to be achieved by the following signals, Pin Details of Translator Selections Terminations of DIR pins with FPGA DIR SIGNAL

OE1

DIR1

FPGA PINS

P91

P92

Vi Microsystems Pvt. Ltd.,

[ 15 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

CHAPTER - 9 CONNECTOR DETAILS The Spartan-3E Low Cost Kit has three 20-pin connectors labeled as P2, P4 and P9 respectively. Connector P2 is on the top, P4 is on the left top and P9 is on the left bottom of the board. 20 Pin Connectors Pin 20 on each connector is always GND. Similarly, pin 1 is always the output from the DC regulator. Depending upon the jumpers, 3.3V or 5V is selected. For P2 connector, to get 3.3V “JP2" is short and “JP1" is open or to get 5V “JP1" is short and “JP2" is open. For P4 connector, to get 3.3V “JP6" is short and “JP5" is open or to get 5V “JP5" is short and “JP6" is open. For P6 connector, to get 3.3V “JP11" is short and “JP10" is open or to get 5V “JP10" is short and “JP11" is open. Pin Detail for P2 Connector SCHEMATIC NAME

FPGA PIN

FPGA PIN

SCHEMATIC NAME

VCC

-

1

2

P106

IO36

IO37

P10

3

4

P29

IO38

OE-*

P91

5

6

P92

DIR*

SPWM1*

P93

7

8

P94

SPWM2*

SPWM3*

P96

9

10

P97

SPWM4*

SPWM5*

P98

11

12

P103

SPWM6*

SPWM7*

P104

13

14

P105

SPWM8*

M0

P62

15

16

P60

M1

IO39

P59

17

18

P63

DIN

CCLK

P71

19

20

-

GND

CONNECTOR

Note 1. If your are using * these pins, we can not use on board pwm that is P6 connector. 2. If your using M0 & M1 in connector, after downloading the program remove the jumpers M0, M1 & M2.

Vi Microsystems Pvt. Ltd.,

[ 16 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Pin Detail for P4 Connector SCHEMATIC NAME

FPGA PIN

FPGA PIN

SCHEMATIC NAME

VCC

-

1

2

P86

SCTS

IO2

P140

3

4

P139

IO3

IO4

P135

5

6

P134

IO5

IO6

P132

7

8

P131

IO7

IO8

P130

9

10

P142

IO1

IO18

P112

11

12

P126

IO11

IO12

P125

13

14

P124

IO13

IO14

P123

15

16

P117

IO15

IO16

P116

17

18

P113

IO17

SRTS

P85

19

20

-

GND

FPGA PIN

SCHEMATIC NAME

CONNECTOR

Pin Detail for P9 Connector SCHEMATIC NAME

FPGA PIN

VCC

-

1

2

P122

EXCLK

IO19

P32

3

4

P26

IO20

IO21

P25

5

6

P23

IO22

IO23

P22

7

8

P21

IO24

IO25

P20

9

10

P17

IO26

IO27

P16

11

12

P15

IO28

IO29

P14

13

14

P8

IO30

IO31

P7

15

16

P5

IO32

IO33

P4

17

18

P3

IO34

IO35

P2

19

20

-

GND

Vi Microsystems Pvt. Ltd.,

CONNECTOR

[ 17 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

CHAPTER - 10 VHDL CODE FOR VPTB - 05 1. SWITCH & LED AIM: Study of Switch and LED FLOW CHART

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity io is port ( sw:in std_logic_vector(7 downto 0); led:out std_logic_vector(7 downto 0)); end io; architecture Behavioral of io is begin led <= sw; end Behavioral;

Vi Microsystems Pvt. Ltd.,

[ 18 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

UCF: NET NET NET NET NET NET NET NET

"sw<0>" "sw<1>" "sw<2>" "sw<3>" "sw<4>" "sw<5>" "sw<6>" "sw<7>"

LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = =

"p6" "p18" "p24" "p36" "p38" "p41" "p69" "p78"

; ; ; ; ; ; ; ;

NET NET NET NET NET NET NET NET

"led<0>" "led<1>" "led<2>" "led<3>" "led<4>" "led<5>" "led<6>" "led<7>"

LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = =

"p33" "p34" "p35" "p39" "p43" "p44" "p2" "p50"

; ; ; ; ; ; ; ;

Vi Microsystems Pvt. Ltd.,

[ 19 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

2. A/D CONVERTER AIM: Conversion of Analog data to Digital using I2C based ADC(PCF8591) and display the digital data in Led System Clock = 20 MHz FLOW CHART

Vi Microsystems Pvt. Ltd.,

[ 20 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

VHDL Code: --DEFAULT ANALOG INPUT IN CHANNEL 0. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity i2cadch0 is Port ( clk:in std_logic; rst:in std_logic; sda:inout std_logic; data:out std_logic_vector(7 downto 0); sclk:out std_logic ); end i2cadch0; architecture Behavioral of i2cadch0 is type pcf is(set,write,read); signal adc:pcf; signal sig:std_logic_vector(4 downto 0); signal i:integer:=7; constant a_byte_w:std_logic_vector(7 downto 0):="10010000";–Address Byte constant a_byte_r:std_logic_vector(7 downto 0):="10010001"; constant c_byte:std_logic_vector(7 downto 0):="01000000";–Control Byte signal clkdiv:std_logic; signal div:std_logic_vector(15 downto 0); begin --CLOCK DIVIDER PROCESS process(clk) begin if clk'event and clk='1' then div <= div + 1; case div(15 downto 14) is when "00" => clkdiv <= '1'; when "10" => clkdiv <= '0'; when others => end case; end if; end process; process(clkdiv) variable j:std_logic_vector(7 downto 0):="00000000";

Vi Microsystems Pvt. Ltd.,

[ 21 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

begin if clkdiv'event and clkdiv='1' then if rst ='1' then sig <= (others => '0'); adc <= set; data <= x"00"; else case adc is when set => sig<=sig+1; case sig(3 downto 0) is --START CONDITION FOR WRITE CONVERSION when "0000"=> sclk <='1'; when "0010" => sda <= '1'; when "0011"=> sda <='0'; when "0100"=> sclk<='0'; i <= 7; --ADDRESS BYTE FOR WRITE OPERATION when "0101" => sda <=a_byte_w(i); sclk<='1'; when "0110" => sclk<='0'; if i > 0 then i <= i - 1; sig(3 downto 0)<="0101"; else sig(3 downto 0)<="0111"; i <= 7; end if; when "0111"=> --ACKNOWLEDGEMENT sclk<='1'; when "1000" => sclk <='0'; --CONTROL BYTE OPERATION when "1001"=> sda <=c_byte(i); sclk <='1'; when "1010"=> if i > 0 then i <= i - 1;

Vi Microsystems Pvt. Ltd.,

[ 22 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

sig(3 downto 0)<="1001"; else sig(3 downto 0)<="1011"; i <= 7; end if; sclk <='0'; when "1011"=> --ACKNOWLEDGEMENT sclk<='1'; when "1100" => sclk <='0'; when "1101" => adc<=write; sig <= (others => '0'); when others => end case; --START CONDITION FOR A/D CONVERSION when write => sig<=sig+1; case sig(3 downto 0) is when "0000"=> sclk <='1'; when "0010" => sda <= '1'; when "0011"=> sda <='0'; when "0100"=> sclk<='0'; i <= 7; --ADDRESS BYTE FOR READ OPERATION when "0101" => sda <=a_byte_r(i); sclk<='1'; when "0110"=> if i > 0 then i <= i - 1; sig(3 downto 0)<="0101"; else sig(3 downto 0)<="0111"; i <= 7; end if; sclk<='0'; when "0111"=> --ACKNOWLEDGEMENT sda <='Z'; sclk<='1'; when "1000" =>

Vi Microsystems Pvt. Ltd.,

[ 23 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

sclk <='0'; when "1001" => adc<=read; sig <= (others => '0'); when others => end case; --A/D READ OPERATION when read => sig<=sig+1; --FOR EXAMPLE case sig(3 downto 0) is --sda=11110101 when "0000" => sclk<='1'; j:=j(6 downto 0) & sda; when "0001" => if i > 0 then i <= i - 1; sig(3 downto 0)<="0000"; else sig(3 downto 0)<="0010"; i <= 7; end if; sclk <='0'; when "0010" => sda <='0'; when "0011" => sclk <='1'; when "0100" => sclk <='0'; when "0101" => sda <='1'; sda <='Z'; when "0110" => data<=j; adc <=read; sig <= (others => '0'); when others => end case; end case; end if; end if; end process; end Behavioral;

Vi Microsystems Pvt. Ltd.,

[ 24 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

UCF: NET NET NET NET NET NET NET NET NET NET NET NET

"clk" "data<7>" "data<6>" "data<5>" "data<4>" "data<3>" "data<2>" "data<1>" "data<0>" "sclk" "sda" "rst"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = =

Vi Microsystems Pvt. Ltd.,

"p56" "p33" "p34" "p35" "p39" "p43" "p44" "p2" "p50" "p88" "p87" "p6"

; ; ; ; ; ; ; ; ; ; ; ;

[ 25 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

3. D/A CONVERTER AIM: Generation of Square Wave using I2C Based DAC(PCF8591) System Clock = 20 MHz FLOW CHART

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity square is Port ( sclk:out std_logic; rst:in std_logic; clk:in std_logic; sda:out std_logic ); end square;

Vi Microsystems Pvt. Ltd.,

[ 26 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

architecture Behavioral of square is signal sig:std_logic_vector(4 downto 0); signal div:std_logic_vector(15 downto 0); signal data:std_logic_vector(7 downto 0); signal i:integer:=7; signal j:integer:=1; signal clkdiv:std_logic; constant a_byte_w:std_logic_vector(7 downto 0):="10010000"; --(1 0 0 1 A2 A1 A0 R/W) ADDRESS BYTE constant c_byte:std_logic_vector(7 downto 0):="01000000";--CONTROL BYTE constant datah:std_logic_vector(7 downto 0):="11111111"; --DIGITAL DATA constant datal:std_logic_vector(7 downto 0):="00000000"; --DIGITAL DATA begin --CLOCK DIVIDER PROCESS process(clk) begin if clk'event and clk='1' then div <= div + 1; case div(5 downto 4) is when "00" => clkdiv <= '1'; when "10" => clkdiv <= '0'; when others => end case; end if; end process; --MAIN PROCESS process(clkdiv) begin if rst='1' then sig <= (others => '0'); i <= 7; j <= 1; elsif clkdiv'event and clkdiv='1' then sig<=sig+1; case sig(4 downto 0) is --START CONDITION when "00000"=> sclk <='1'; sda <= '1'; when "00001"=> sda<='0'; when "00100"=> sclk<='0';

Vi Microsystems Pvt. Ltd.,

[ 27 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

i <= 7; --ADDRESS BYTE="10010000" FOR WRITE OPERATION when "00101" => sda<=a_byte_w(i); sclk<='1'; when "00110"=> sclk<='0'; if i > 0 then i <= i - 1; sig(4 downto 0) <= "00101"; else sig(4 downto 0) <= "00111"; i <= 7; end if; when "00111"=> --ACKNOWLEDGEMENT sclk<='1'; when "01000" => sclk <='0'; --CONTROL BYTE OPERATION when "01001"=> --CONTROL BYTE=01000000 sda<=c_byte(i); sclk<='1'; when "01010"=> sclk<='0'; if i > 0 then i <= i - 1; sig(4 downto 0) <= "01001"; else sig(4 downto 0) <= "01011"; i <= 7; end if; when "01011"=> --ACKNOWLEDGEMENT sclk <='1'; when "01100" => sclk<='0'; if j=1 then data <= datah; j <= j + 1; else data <= datal; j <= 1; end if; --DIGITAL DATA FOR CONVERSION when "01101"=> sda <=data(i); --DATA BYTE

Vi Microsystems Pvt. Ltd.,

[ 28 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

sclk<='1'; when "01110"=> sclk<='0'; if i > 0 then i <= i - 1; sig(4 downto 0) <= "01101"; else sig(4 downto 0) <= "01111"; i <= 7; end if; when "01111"=> --ACKNOWLEDGEMENT sda <='0'; sclk<='1'; when "10000" => sclk <='0'; --STOP CONDITION when "10001"=> sclk<='1'; sda<='0'; when "10010"=> sda<='1'; sig(4 downto 0)<= "00000"; when others => end case; end if; end process; end Behavioral; UCF: NET NET NET NET

"clk" "sclk" "sda" "rst"

LOC LOC LOC LOC

= = = =

"P56" "P88" "P87" "p6"

Vi Microsystems Pvt. Ltd.,

; ; ; ;

[ 29 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

4. LCD DISPLAY AIM: To Display Characters in LCD System Clock = 20 MHz FLOW CHART

VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity lcd is port(rs,cs,diow : inout std_logic; clk : in std_logic; d : inout std_logic_vector(7 downto 0)); end lcd; architecture arch_lcd of lcd is type main1 is array(1 to 5) of std_logic_vector(7 downto 0); signal state1:main1:=(x"38",x"06",x"01",x"0f",x"80"); type main2 is array(1 to 8) of std_logic_vector(7 downto 0); signal state2:main2:=(x"56",x"49",x"20",x"4d",x"49",x"43",x"52",x"4f"); signal sig : std_logic_vector(29 downto 0) := "000000000000000000000000000000"; signal i,j:integer:=1; begin process begin

Vi Microsystems Pvt. Ltd.,

[ 30 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

wait until clk'event and clk='1'; sig<=sig+1; case sig(25 downto 20) is when "000000" => rs <= '0'; diow <= '0'; when "000001" => d <= state1(i); --38 when "000010" => cs <= '1'; when "000011" => cs <= '0'; i<=i+1; if i<=5 then sig(25 downto 20)<="000001"; else sig(25 downto 20)<="000100"; j<=1; end if; when "000100" => rs <= '1'; when "000101" => d <= state2(j); when "000110" => cs <= '1'; when "000111" => cs <= '0'; j<=j+1; if j<8 then sig(25 downto 20)<="000101"; else sig(25 downto 20)<="000000"; i<=1; end if; when others => null; end case; end process; end architecture; UCF: NET NET NET NET NET NET NET NET NET NET NET NET

"clk" "cs" "d<0>" "d<1>" "d<2>" "d<3>" "d<4>" "d<5>" "d<6>" "d<7>" "diow" "rs"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = =

Vi Microsystems Pvt. Ltd.,

"p56"; "p53"; "p54"; "p58"; "p67"; "p68"; "p70"; "p74"; "p75"; "p76"; "p52"; "p51";

[ 31 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

5. PS/2 KEYBOARD AIM: Read the Scan Code from PS/2 Keyboard and Display in Led System Clock = 20MHz FLOW CHART

VHDL Code: LIBRARY ieee; USE ieee.std_logic_1164.ALL; Entity PS2SIMPL is Port ( Clk : In std_logic; Reset : In std_logic; PS2_Data : In std_logic; PS2_Clk : In std_logic; LEDdis : Out std_logic_vector (7 downto 0)); end PS2SIMPL; Architecture SCHEMATIC of PS2SIMPL is component PS2_CTRL generic (FilterSize : positive := 8); port( Clk : in std_logic; -- System Clock Reset : in std_logic; -- System Reset PS2_Clk : in std_logic; -- Keyboard Clock Line PS2_Data : in std_logic; -- Keyboard Data Line

Vi Microsystems Pvt. Ltd.,

[ 32 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Scan_Code: out std_logic_vector(7 downto 0)-- Eight bits Data Out ); end component; signal gnd,Vcc : std_logic; signal Code : std_logic_vector (7 downto 0); begin Gnd <= '0'; Vcc <= '1'; PS2_CTRL_i : PS2_CTRL Generic Map (FILTERSIZE => 8) Port Map (Clk=>Clk,Reset=>Reset,PS2_Clk=>PS2_Clk, PS2_Data=>PS2_Data,Scan_Code=>leddis); end SCHEMATIC; library IEEE; use IEEE.Std_Logic_1164.all; use IEEE.Numeric_Std.all; Entity PS2_Ctrl is generic (FilterSize : positive := 8); port( Clk : in std_logic; -- System Clock Reset : in std_logic; -- System Reset PS2_Clk : in std_logic; -- Keyboard Clock Line PS2_Data : in std_logic; -- Keyboard Data Line Scan_Code: out std_logic_vector(7 downto 0));-- Eight bits Data Out end PS2_Ctrl; Architecture ALSE_RTL of PS2_Ctrl is signal PS2_Datr : std_logic; subtype Filter_t is std_logic_vector(FilterSize-1 downto 0); signal Filter : Filter_t; signal Fall_Clk : std_logic; signal Bit_Cnt : unsigned (3 downto 0); signal Scan_DAVi : std_logic; signal S_Reg : std_logic_vector(8 downto 0); signal PS2_Clk_f : std_logic; Type State_t is (Idle, Shifting); signal State : State_t; begin process (Clk,Reset) begin if Reset='1' then PS2_Datr <= '0'; PS2_Clk_f <= '0'; Filter <= (others=>'0'); Fall_Clk <= '0'; elsif rising_edge (Clk) then PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'

Vi Microsystems Pvt. Ltd.,

[ 33 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Fall_Clk <= '0'; Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1); if Filter = "11111111" then PS2_Clk_f <= '1'; elsif Filter = "00000000" then PS2_Clk_f <= '0'; if PS2_Clk_f = '1' then Fall_Clk <= '1'; end if; end if; end if; end process; process(Clk,Reset) begin if Reset='1' then State <= Idle; Bit_Cnt <= (others => '0'); S_Reg <= (others => '0'); Scan_Code <= (others => '0'); Scan_Davi <= '0'; elsif rising_edge (Clk) then case State is when Idle => Bit_Cnt <= (others => '0'); if Fall_Clk='1' and PS2_Datr='0' then -- Start bit State <= Shifting; end if; when Shifting => if Bit_Cnt >= 9 then if Fall_Clk='1' then -- Stop Bit Scan_Davi <= '1'; Scan_Code <= S_Reg(7 downto 0); State <= Idle; end if; elsif Fall_Clk='1' then Bit_Cnt <= Bit_Cnt + 1; S_Reg <= PS2_Datr & S_Reg (S_Reg'high downto 1); -- Shift right end if; when others => State <= Idle; end case; end if; end process; end ALSE_RTL;

Vi Microsystems Pvt. Ltd.,

[ 34 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

UCF: NET NET NET NET NET NET NET NET NET NET NET NET

"Clk" "LEDdis<0>" "LEDdis<1>" "LEDdis<2>" "LEDdis<3>" "LEDdis<4>" "LEDdis<5>" "LEDdis<6>" "LEDdis<7>" "PS2_Clk" "PS2_Data" "Reset"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

Vi Microsystems Pvt. Ltd.,

= = = = = = = = = = = =

"p56"; "p50"; "p2"; "p44"; "p43"; "p39"; "p35"; "p34"; "p33"; "p81"; "p77"; "p6";

[ 35 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

6. UART AIM: Implementation of UART and verify by Receving the data through Rx line and Transmitting the data through Tx line System Clock = 20 MHz FLOW CHART

VHDL Code –TOP Unit library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; entity usart is Port ( SysClk : in Std_Logic; -- System Clock TxD : out Std_Logic; -- Tx output (serial data) RxD : in Std_Logic; -- Receiver input (serial data) end usart; architecture Behavioral of usart is signal EnabTx : Std_Logic; -- Enable TX unit signal EnabRx : Std_Logic; -- Enable RX unit signal temp : Std_Logic_vector(7 downto 0); -- Baud rate Generator

Vi Microsystems Pvt. Ltd.,

);

[ 36 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

component ClkUnit port (SysClk : in Std_Logic; -- System Clock clkdiv26 : inout std_logic; -- Control signal used for Rx enable EnableTx : out Std_Logic); -- Control signal used for Tx enable end component; component txasync is port ( Clk : in Std_Logic; -- Clock signal Enable : in Std_Logic; -- Enable input TxD : out Std_Logic; -- RS-232 data output Dataout : in Std_Logic_Vector(7 downto 0)-- parallel input ); end component; component rxasync port ( Clk : in Std_Logic; -- system clock signal Enable : in Std_Logic; -- Enable input RxD : in Std_Logic; -- RS-232 data input DataIn : out Std_Logic_Vector(7 downto 0)-- parallel output ); end component; begin ClkDiv : ClkUnit port map (SysClk,EnabRX,EnabTX); TxDev : txasync port map (Sysclk,EnabTX,TxD,temp); RxDev :rxasync port map (Sysclk,EnabRX,RxD,temp); end Behavioral; --Clk Divider Unit: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; entity ClkUnit is port ( SysClk : in Std_Logic; -- System Clock 4 MHZ clkdiv26 : inout std_logic; -- Control signal for Rx EnableTx : out Std_Logic -- Control signal for Tx ); end entity; architecture Behaviour of ClkUnit is signal CntOne : std_logic_vector(4 downto 0) := "00001"; signal Cnt26 : std_logic_vector(7 downto 0);

Vi Microsystems Pvt. Ltd.,

[ 37 ]

SPARTAN 3E DEVELOPMENT BOARD signal Cnt10 : std_logic_vector(4 downto 0); begin -Divides the system clock of 20 MHz by 26 FOR RX TO GET 155 KHZ DivClk26 : process(SysClk) begin if Rising_Edge(SysClk) then

VPTB - 05

--

Cnt26 <= Cnt26 + CntOne; case Cnt26 is when "10000001"=> -- divide 20 MHZ by 26 to get 155 KHZ ClkDiv26 <= '1'; Cnt26 <= "00000000"; when others => ClkDiv26 <= '0'; end case; end if; end process; ---- Provides the EnableTX signal, DIVIDE 155KHZ BY 16 to get 9.6 KHz DivClk10 : process(SysClk,Clkdiv26) begin if Rising_Edge(SysClk) then if ClkDiv26 = '1' then Cnt10 <= Cnt10 + CntOne; end if; case Cnt10 is when "10000" => EnableTX <= '1'; Cnt10 <= "00000"; when others => EnableTX <= '0'; end case; end if; end process; end Behaviour; --Transmitter Unit library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; entity txasync is port ( Clk : in Std_Logic; -- Clock signal Enable : in Std_Logic; -- Enable input

Vi Microsystems Pvt. Ltd.,

[ 38 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

TxD : out Std_Logic; -- RS-232 data output Dataout : in Std_Logic_Vector(7 downto 0));-- parallel output end entity; architecture Behaviour of txasync is signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register signal BitCnt : std_logic_vector(4 downto 0); -- bit counter signal tmpTRegE : Std_Logic; -- High for Temp Tx register empty signal CntOne : std_logic_vector(4 downto 0):="00010"; type main is (s1,s2); signal state:main; begin process(Clk,Enable,TReg) begin if Rising_Edge(Clk) then case state is when s1 => if Enable = '1' then TReg <= Dataout; tmpTRegE <= '0'; if tmpTRegE = '0' then case BitCnt is when "00000" => TxD <= '0'; BitCnt <= BitCnt + CntOne; when "00010" | "00100" | "00110" | "01000" | "01010" | "01100" | "01110" | "10000" => TxD <= TReg(0); TReg <= '1' & TReg(7 downto 1) ; BitCnt <= BitCnt + CntOne; when "10010" => TxD <= '1'; BitCnt <= "00000"; tmpTRegE <= '1'; state<=s1; when others => end case; end if; end if; when others => end case; end if; end process; end Behaviour;

Vi Microsystems Pvt. Ltd.,

[ 39 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

--Receiver Unit library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; entity rxasync is port (Clk : in Std_Logic; -- system clock signal Enable : in Std_Logic; -- Enable input RxD : in Std_Logic; -- RS-232 data input DataIn : out Std_Logic_Vector(7 downto 0)-- parallel output ); end entity; architecture Behaviour of rxasync is signal Start : Std_Logic; -- Syncro signal signal tmpRxD : Std_Logic; -- RxD buffer signal tmpDRdy : Std_Logic; -- Data ready buffer signal BitCnt : std_logic_vector(3 downto 0); signal SampleCnt : std_logic_vector(3 downto 0); -- samples on one bit counter signal ShtReg : Std_Logic_Vector(7 downto 0); signal DOut : Std_Logic_Vector(7 downto 0); signal tmpBitCnt : Integer range 0 to 15; signal tmpSampleCnt : Integer range 0 to 15; signal CntOne : std_logic_vector(3 downto 0):="0001"; begin RcvProc : process(Clk,RxD,Enable) begin if Rising_Edge(Clk) then tmpBitCnt <= conv_Integer(BitCnt); tmpSampleCnt <= conv_Integer(SampleCnt); if Enable = '1' then if Start = '0' then if RxD = '0' then -- Start bit, SampleCnt <= SampleCnt + CntOne; Start <= '1'; end if; else if tmpSampleCnt = 8 then -- reads the RxD line tmpRxD <= RxD; SampleCnt <= SampleCnt + CntOne; elsif tmpSampleCnt = 15 then case tmpBitCnt is

Vi Microsystems Pvt. Ltd.,

[ 40 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

when 0 => if tmpRxD = '1' then -- Start Bit Start <= '0'; else BitCnt <= BitCnt + CntOne; end if; SampleCnt <= SampleCnt + CntOne; when 1|2|3|4|5|6|7|8 => BitCnt <= BitCnt + CntOne; SampleCnt <= SampleCnt + CntOne; ShtReg <= tmpRxD & ShtReg(7 downto 1); when 9 => tmpDRdy <= '1'; DOut <= ShtReg; BitCnt <= "0000"; Start <= '0'; when others => null; end case; else SampleCnt <= SampleCnt + CntOne; end if; end if; end if; end if; end process; DataIn <= DOut; end Behaviour; UCF: NET NET NET

"RxD" LOC "SysClk" LOC "TxD" LOC

= "p82"; = "p56"; = "p83";

Vi Microsystems Pvt. Ltd.,

[ 41 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

CHAPTER - 11 ADD ON CARD PROGRAMS FOR VPTB - 05 USING POLYTECHNIC SYLLABUS KERALA Exp - 1a Verilog code for basic logic gates in dataflow style of modelling Module basicgates(andgate,orgate,notgate,nandgate,norgate,xorgate,xnorgate,a,b); //module declaration with inpu,output list output and gate, orgate, notgate, nandgate, norgate, xorgate, xnorgate; //output declaration input a, b; //input declaration //expression is evaluvated as soon as one of the operands in the RHS changes(here a , b) and //assigned to the LHS net. //Statements using the assign keyword are executed at the same time. assign andgate = a & b; assign orgate = a | b; assign notgate = ~a; assign nandgate = ~(a & b); assign norgate = ~(a | b); assign xorgate = a ^ b; assign xnorgate = a ~^ b; end module User Constraint File NET "a" LOC = "p6"; NET "b" LOC = "p18"; NET "andgate" LOC = "p33"; NET "orgate" LOC = "p34"; NET "notgate" LOC = "p35"; NET "nandgate" LOC = "p39"; NET "norgate" LOC = "p43"; NET "xorgate" LOC = "p44"; NET "xnorgate" LOC = "p2";

Vi Microsystems Pvt. Ltd.,

[ 42 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ISE Xilinx Test Bench Waveform Result

Vi Microsystems Pvt. Ltd.,

[ 43 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Exp - 1b) Verilog code for 4 to1 multiplexer using behavioral style of modelling module mux4x1(muxout,i0,i1,i2,i3,sel1,sel0);//module declaration with list of input,outputs output muxout; //output declaration input i0,i1,i2,i3;//input declaration input sel1,sel0;//input declaration reg muxout;//register declaration //All variables on the LHS of the always block must be declared as register using keyword reg //In verilog register represents data storage elements. //Statements within always block are executed sequentially. always @ (sel1 or sel0 or i0 or i1 or i2 or i3) begin case({sel1,sel0}) 2'b00 : muxout = i0; // 1 input assigned to muxout for select value "00" 2'b01 : muxout = i1; // 2 input assigned to muxout for select value "01" 2'b10 : muxout = i2; // 3 input assigned to muxout for select value "10" 2'b11 : muxout = i3; // 4 input assigned to muxout for select value "11" endcase end end module User Constraint File #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "i3" LOC = "p41" ; NET "i2" LOC = "p38" ; NET "i1" LOC = "p36" ; NET "i0" LOC = "p24" ; NET "muxout" LOC = "p33" ; NET "sel0" LOC = "p18" ; NET "sel1" LOC = "p6" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE

Vi Microsystems Pvt. Ltd.,

[ 44 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ISE Xilinx Test Bench Waveform Result

Vi Microsystems Pvt. Ltd.,

[ 45 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Exp - 1c) Verilog code for decoder 3 to 8 using behavioral modelling // decoder has n inputs 2 power n outputs module decoder3to8(oup,inp,en); output [7:0] oup; input [2:0] inp; input en; reg [7:0] oup;

//module declaration with i/p ,o/p list //output declaration //input declaration ////input declaration //register declaration

always @ (inp or en) //when any one of the inputs in sensitivity list changes always //block is executed begin if (en)

//enable is equal to 1 statements within begin end block is executed.hence enable //acts as control signal

begin case (inp)

// output value is assigned with respect to the input as per truth table //of the decoder 3'b000 : oup = 8'b00000001; 3'b001 : oup = 8'b00000010; 3'b010 : oup = 8'b00000100; 3'b011 : oup = 8'b00001000; 3'b100 : oup = 8'b00010000; 3'b101 : oup = 8'b00100000; 3'b110 : oup = 8'b01000000; 3'b111 : oup = 8'b10000000; default: oup = 8'b00000000; //default statement is optional endcase end else oup = 8'b00000000; // when enable is 0 output is 0.hence decoder is disabled end end module

Vi Microsystems Pvt. Ltd.,

[ 46 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

User Constraint File #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "en" LOC = "p6" ; NET "inp<0>" LOC = "p36" ; NET "inp<1>" LOC = "p24" ; NET "inp<2>" LOC = "p18" ; NET"oup<0>" LOC = "p50"; NET "oup<1>" LOC = "p2" ; NET "oup<2>" LOC = "p44" ; NET "oup<3>" LOC = "p43" ; NET "oup<4>" LOC = "p39" ; NET "oup<5>" LOC = "p35" ; NET "oup<6>" LOC = "p34" ; NET "oup<7>" LOC = "p33" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE

Vi Microsystems Pvt. Ltd.,

[ 47 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ISE Xilinx Test Bench Waveform Result

Vi Microsystems Pvt. Ltd.,

[ 48 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Exp - 1d) Verilog code for full adder using data flow style of modelling Module fulladder(sum,carry,a,b,cin); //module declaration with i/p ,o/p list output sum,carry; //output declaration input a,b,cin; //input declaration //expression is evaluvated as soon as one of the operands in the RHS changes(here a , b) and //assigned to the LHS net.Statements using the assign keyword are executed at the same time. assign sum = a ^ b ^ cin; //sum output is evaluvated based on a xor b xor cin assign carry = (a & b)|(b & cin)|(a & cin); //carry output based on a.b + b.cin+a.cin end module User Constraint File #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a" LOC = "p6" ; NET "b" LOC = "p18" ; NET "carry" LOC = "p35" ; NET "cin" LOC = "p24" ; NET "sum" LOC = "p33" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE

Vi Microsystems Pvt. Ltd.,

[ 49 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ISE Xilinx Test Bench Waveform Result

Vi Microsystems Pvt. Ltd.,

[ 50 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Exp -1 e) Verilog code for 4 bit full adder using structural modelling //structral modelling is the gate level modelling using primitive gates such as // and,or,not,nand ... module fulladder4b(sum,cout,a,b); //module declaration with input,output list output [3 :0]sum; //output declaration for sum output output cout; //output declaration for carry output input [3 :0]a,b; //input declaration for a,b inputs wire c1,c2,c3;

//wire declaration for internal connections in a logic circuit which do //not store values but pass the values from one end to other end.

//here the value of cin input to the 4 bit full adder is given at the instantiation itself as //1'b0 at fa0.the user can change the value of carry in ie,cin by replacing 1'b0 as 1'b1 in //fa0 fulladd fulladd fulladd fulladd

fa0(sum[0],c1,a[0],b[0],1'b0); //full adder instantiation fa1(sum[1],c2,a[1],b[1],c1); fa2(sum[2],c3,a[2],b[2],c2); fa3(sum[3],cout,a[3],b[3],c3);

endmodule module fulladd(sum,carry,a,b,c); output sum,carry; input a,b,c; wire axorb,aandb,bandc,aandc; xor halfsum(axorb,a,b); xor fullsum(sum,axorb,c); and a1(aandb,a,b); and a2(bandc,b,c); and a3(aandc,a,c); or o1(carry,aandb,bandc,aandc); endmodule

Vi Microsystems Pvt. Ltd.,

[ 51 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

User Constraint File NET "a<3>" LOC = "p6"; NET "a<2>" LOC = "p18"; NET "a<1>" LOC = "p24"; NET "a<0>" LOC = "p36"; NET "b<3>" LOC = "p38"; NET "b<2>" LOC = "p41"; NET "b<1>" LOC = "p69"; NET "b<0>" LOC = "p78"; NET "sum<3>" LOC = "p33"; NET "sum<2>" LOC = "p34"; NET "sum<1>" LOC = "p35"; NET "sum<0>" LOC = "p39"; NET "cout" LOC = "p44";

Vi Microsystems Pvt. Ltd.,

[ 52 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ISE Xilinx Test Bench Waveform Result

Vi Microsystems Pvt. Ltd.,

[ 53 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Exp -1 f) Verilog code for 4 bit magnitude comparator using dataflow modelling module magcomp(a,b,equal,greater,lesser); //module declaration with i/p,o/p list input [3:0]a; //comparator input declaration input [3:0] b; //comparator input declaration output equal; output greater; output lesser;

//comparator output declaration for a equal to b //comparator output declaration for a greater than b //comparator output declaration for a less than b

// for checking equality for the two inputs all inputs of a have to be exnor'ed with b input. // since xnor output is high when i/ps are same and low when they differ. assign x3 = a[3] ~^ b[3]; assign x2 = a[2] ~^ b[2]; assign x1 = a[1] ~^ b[1]; assign x0 = a[0] ~^ b[0]; // for equality condition: assign equal = (x3 & x2 & x1 & x0 ); // 1 led glows for a = b condition. // when x3,x2,x1,x0 are given to an and gate the output is high when all(ie,x3,x2,x1,x0 are // equal to 1 which means a equal to b.and gate output is low when any one of x3,x2,x1,x0 is low (ie,'0') which means a not equal to b). //for greater than condition : // the boolean expression given below has to be verified assign greater = ((a[3] & (~b[3])) | (x3 & a[2] & (~b[2])) | (x3 & x2 & a[1] & (~b[1])) | (x3 & x2 & x1 & a[0] & (~b[0]))); // the above exp is continued here //2 led glows for a > b //for lesser than condition : // the boolean expression given below has to be verified assign lesser = ((b[3] & (~a[3])) | (x3 & b[2] & (~a[2])) | (x3 & x2 & b[1] & (~a[1])) | (x3 & x2 & x1 & b[0] & (~a[0]))); // the above exp is continued here //3 led glows for a < b end module

Vi Microsystems Pvt. Ltd.,

[ 54 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

User Constraint File #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "a[0]" LOC = "p36" ; NET "a[1]" LOC = "p24" ; NET "a[2]" LOC = "p18" ; NET "a[3]" LOC = "p6" ; NET "b[0]" LOC = "p78" ; NET "b[1]" LOC = "p69" ; NET "b[2]" LOC = "p41" ; NET "b[3]" LOC = "p38" ; NET "equal" LOC = "p33" ; NET "greater" LOC = "p34" ; NET "lesser" LOC = "p35" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE

Vi Microsystems Pvt. Ltd.,

[ 55 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ISE Xilinx Test Bench Waveform Result

Vi Microsystems Pvt. Ltd.,

[ 56 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Exp -1 g) Verilog code for Set Reset(SR)flip-flop in data flow modeling module srff(q,qbar,clk,s,r); //module declaration output q,qbar; //srff outputs declaration input clk,s,r; //srff inputs declaration wire nand1,nand2,nand3,nand4,nand5,nand6,notclk; //declare internal connections as wire //expression is evaluvated as soon as one of the operands in the RHS changes(here a , b) and //assigned to the LHS net. //Statements using the assign keyword are executed at the same time. assign nand1 = ~(s & clk); assign nand2 = ~(r & clk); assign nand3 = ~(nand1 & nand4); assign nand4 = ~(nand3 & nand2); assign notclk = ~clk; assign nand5 = ~(nand3 & notclk); assign nand6 = ~(nand4 & notclk); assign q = ~(nand5 & qbar); assign qbar = ~(nand6 & q);

//nand operation of s ,clk //nand operation of r ,clk //nand operation of nand1,nand4 //nand operation of nand3,nand2 // not operation of clk //nand operation of nand3,notclk //nand operation of nand4,notclk //nand operation of nand5,q //nand operation of nand6,qbar

end module User Constraint File #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "p56" ; NET "q" LOC = "p33" ; NET "qbar" LOC = "p34" ; NET "r" LOC = "p18" ; NET "s" LOC = "p6" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE

Vi Microsystems Pvt. Ltd.,

[ 57 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ISE Xilinx Test Bench Waveform Result

Vi Microsystems Pvt. Ltd.,

[ 58 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Exp 1h) Verilog code for T FLIP FLOP using sync reset using behavioral modelling for FPGA kit implementation module tff(t,clk,reset,out,out1); //Input Ports input t, clk, reset ; output out,out1; //Output Ports //All variables on the LHS of the always block must be declared as register using keyword reg //In verilog register represents data storage elements. //Statements within always block are executed sequentially. reg q,qbar,clkslw; reg [28 : 0] count1; //slow clock generation with count block always @ (posedge clk) if (count1 !== 8388608) count1 <= count1 + 1; else count1 <= 1; // slow clock generation block always @ (posedge clk) if (count1 == 4194304) clkslw <= 1; else if (count1 ==8388608) clkslw <= 0; else clkslw <= clkslw; //Code for TFF Starts Here always @ (posedge clkslw) if (~reset) //means when reset is zero ie, active low q <= 1'b0; // flip-flop is reset else case (t) 0 : q <= q; //when t is 0 q output is same as previous and does not change 1 : q <= ~q; //when t is 1 q output is toggled with the previous value endcase assign out = q; // value of q is assigned to first led ie, output of tff assign out1 = ~q; //inverted value of q is assigned to second led ie, output complement of tff endmodule

//End Of Module tff_sync_reset

Vi Microsystems Pvt. Ltd.,

[ 59 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

User Constraint File #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "p56" ; NET "out" LOC = "p33" ; NET "out1" LOC = "p34"; NET "reset" LOC = "p6" ; NET "t" LOC = "p18" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE Exp 1h) Verilog code for T FLIP FLOP using sync reset using behavioral modelling without slow clock for test bench module tff(t,clk,reset,out,out1); input t, clk, reset ; //Input Ports output out,out1; //Output Ports //All variables on the LHS of the always block must be declared as register using keyword reg //In verilog register represents data storage elements. //Statements within always block are executed sequentially. reg q; //Code for TFF Starts Here always @ (posedge clk) if (~reset) //means when reset is zero ie,active low q <= 1'b0; // flip-flop is reset else case (t) 0 : q <= q; 1 : q <= ~q; endcase

//when t is 0 q output is same as previous and does not change //when t is 1 q output is toggled with the previous value

assign out = q; // value of q is assigned to first led ie, output of tff assign out1 = ~q; //inverted value of q is assigned to second led ie, output complement of tff // when t is 0 the previous output values of tff is retained which is shown in the first two leds // when t is 1 the previous output values of tff is toggled which is shown by the alternate // blinking first two leds

endmodule //End Of Module tff_sync_reset

Vi Microsystems Pvt. Ltd.,

[ 60 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ISE Xilinx Test Bench Waveform Result

Vi Microsystems Pvt. Ltd.,

[ 61 ]

SPARTAN 3E DEVELOPMENT BOARD Exp 1 i) Verilog code for ripple counter using structural modelling implementation module ripple(clk, count, clear); input clk, clear; output [3:0] count; wire [3:0] count, countbar; reg [28 : 0] count1; reg clkslw; wire clk1; //slow clock generation // count block always @ (posedge clk) if (count1 !== 8388608) count1 <= count1 + 1; else count1 <= 1;

VPTB - 05 for FPGA kit

// slow clock generation block always @ (posedge clk) if (count1 == 4194304) clkslw <= 1; else if (count1 ==8388608) clkslw <= 0; else clkslw <= clkslw; assign clk1 = clkslw; // dreg_async_reset bit0(clk1, clear, countbar[0],count[0], countbar[0]); dreg_async_reset bit1(countbar[0], clear,countbar[1],count[1],countbar[1]); dreg_async_reset bit2(countbar[1], clear,countbar[2],count[2],countbar[2]); dreg_async_reset bit3(countbar[2], clear,countbar[3],count[3],countbar[3]); endmodule

Vi Microsystems Pvt. Ltd.,

[ 62 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

module dreg_async_reset (clk, clear, d, q, qbar); input d, clk, clear; output q, qbar; reg q; always @ (posedge clk or negedge clear) begin if (!clear) q <= 1'b0; else q <= d; end assign qbar = ~q; endmodule User Constraint File NET "clk" LOC = "p56"; NET "clear" LOC = "p6"; NET "count<3>" LOC = "p33"; NET "count<2>" LOC = "p34"; NET "count<1>" LOC = "p35"; NET "count<0>" LOC = "p39"; Exp 1i) Verilog code for ripple counter using structural modelling without slow clock for test bench module ripple(clk, count, clear); input clk, clear; output [3:0] count; wire [3:0] count, countbar; // instantiation dreg_async_reset bit0(clk, clear, countbar[0],count[0], countbar[0]); dreg_async_reset bit1(countbar[0], clear,countbar[1],count[1],countbar[1]); dreg_async_reset bit2(countbar[1], clear,countbar[2],count[2],countbar[2]); dreg_async_reset bit3(countbar[2], clear,countbar[3],count[3],countbar[3]);

endmodule

Vi Microsystems Pvt. Ltd.,

[ 63 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

module dreg_async_reset (clk, clear, d, q, qbar); input d, clk, clear; output q, qbar; reg q; always @ (posedge clk or negedge clear) begin if (!clear) q <= 1'b0; else q <= d; end assign qbar = ~q; endmodule

Vi Microsystems Pvt. Ltd.,

[ 64 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ISE Xilinx Test Bench Waveform Result

Vi Microsystems Pvt. Ltd.,

[ 65 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Exp 1 j) Verilog code for traffic light controller using behavioral modelling `timescale 1ns / 1ps // SYSTEM CLOCK FREQUENCY IS 20 MHZ //Connect P3 (TLC) TO P4 (VPTB-05) //Connect P2 (TLC) TO P9 (VPTB-05) //Connect 20 core parallel port cable from PC's parallel port to the JTAG connector of VPTB-05 //Close JP5 & JP10 in VPTB-05 module traffic(clk, reset, p1, p2, p3, p4, pl); //module declaration input clk; // input clock declaration input reset; // input reset declaration output [4:0] p1; // output declaration for road1 output [4:0] p2; // output declaration for road2 output [4:0] p3; // output declaration for road3 output [4:0] p4; // output declaration for road4 output [3:0] pl; // output declaration for pedestrian crossing // constant declarations parameter green = 8'h47; // for displaying the character G the ascii value is 47 in hex parameter red = 8'h52; // for displaying the character R the ascii value is 52 in hex parameter yellow = 8'h59;// for displaying the character Y the ascii value is 59 in hex reg [7:0] path1; reg [7:0] path2; reg [7:0] path3; reg [7:0] path4; reg [7:0] ped;

//register declaration for road1 //register declaration for road2 //register declaration for road3 //register declaration for road4 //register declaration for pedestrian crossing

reg [30:0]sig; always @ (posedge clk ) if (reset == 1'b0) //at reset condition begin path1 <= red; //road1 is red path2 <= red; //road2 is red path3 <= red; //road3 is red path4 <= red; //road4 is red ped <= red; //pedestrian crossing is red sig <= 0; end // when reset is high ie,1 the traffic light controller controls the traffic for roads 1,2,3,4 and // for the pedestrian crossing else begin

Vi Microsystems Pvt. Ltd.,

[ 66 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

sig <= sig + 1; case (sig) // for simulation purpose //for hardware o/p verification comment line 49 and uncomment line 51 //case (sig[29:24]) 6'b000000 : begin path1 <= green ; //road1 is green path2 <= red; //road2 is red path3 <= red; //road3 is red path4 <= red; //road4 is red ped <= red; //pedestrian crossing is red end 6'b000100 : begin path1 <= yellow ; path2 <= red; path3 <= red; path4 <= red; ped <= red; end 6'b001000 : begin path1 <= red ; path2 <= green; path3 <= red; path4 <= red; ped <= red; end 6'b001100 : begin path1 <= red ; path2 <= yellow; path3 <= red; path4 <= red; ped <= red; end 6'b010000 : begin path1 <= red ; path2 <= red; path3 <= green; path4 <= red; ped <= red; end 6'b010100 : begin path1 <= red ;

//road1 is yellow //road2 is red //road3 is red //road4 is red //pedestrian crossing is red

//road1 is red //road2 is green //road3 is red //road4 is red //pedestrian crossing is red

//road1 is red //road2 is yellow //road3 is red //road4 is red //pedestrian crossing is red

//road1 is red //road2 is red //road3 is green //road4is red //pedestrian crossing is red

//road1 is red

Vi Microsystems Pvt. Ltd.,

[ 67 ]

SPARTAN 3E DEVELOPMENT BOARD path2 <= red; path3 <= yellow; path4 <= red; ped <= red; end 6'b011000 : begin path1 <= red ; path2 <= red; path3 <= red; path4 <= green; ped <= red; end 6'b011100 : begin path1 <= red ; path2 <= red; path3 <= red; path4 <= yellow; ped <= red;

VPTB - 05

//road2 is red //road3 is yellow //road4 is red //pedestrian crossing is red

//road1 is red //road2 is red //road3 is red //road4 is green //pedestrian crossing is red

//road1 is red //road2 is red //road3 is red //road4 is yellow //pedestrian crossing is red

end 6'b100000 : begin path1 <= red ; //road1 is red path2 <= red; //road2 is red path3 <= red; //road3 is red path4 <= red; //road4 is red ped <= green; //pedestrian crossing is green which means the pedestrian can cross within the // roads 1,2,3,4 respectively since no vehicles will pass over for this duration //of time. end 6'b101111 : sig <= 8'h00000000; endcase end assign p1 = (path1 == green) ? 5'b10011 : ( (path1 == red) ? 5'b00100 : 5'b01000) ; assign p2 = (path2 == green) ? 5'b10011 : ( (path2 == red) ? 5'b00100 : 5'b01000) ; assign p3 = (path3 == green) ? 5'b10011 : ( (path3== red) ? 5'b00100 : 5'b01000) ; assign p4 = (path4 == green) ? 5'b10011 : ( (path4 == red) ? 5'b00100 : 5'b01000) ; assign pl = (path1 ==red && path2==red && path3 == red && path4 == red && ped == green) ? 4'b0000 : 4'b1111 ; endmodule

Vi Microsystems Pvt. Ltd.,

[ 68 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

User Constraint File NET "clk" NET "reset" NET "p1<0>" NET "p1<1>" NET "p1<2>" NET "p1<3>" NET "p1<4>" NET "p2<0>" NET "p2<1>" NET "p2<2>" NET "p2<3>" NET "p2<4>" NET "p3<0>" NET "p3<1>" NET "p3<2>" NET "p3<3>" NET "p3<4>" NET "p4<0>" NET "p4<1>" NET "p4<2>" NET "p4<3>" NET "p4<4>" NET "pl<0>" NET "pl<1>" NET "pl<2>" NET "pl<3>"

LOC = "p56"; LOC = "p6"; LOC = "p32"; # 1 p9-3 LOC = "p25"; # 2 p9-5 LOC = "p22"; # 3 p9-7 LOC = "p20"; # 4 p9-9 LOC = "p16"; # 5 p9-11 LOC = "p14"; # 6 p9-13 LOC = "p7"; # 7 p9-15 LOC = "p4"; # 8 p9-17 LOC = "p17"; # 17 p9-10 LOC = "p15"; # 18 p9-12 LOC = "p8"; # 19 p9-14 LOC = "p5"; # 20 p9-16 LOC = "p3"; # 21 p9-18 LOC = "p139";# 22 p4-4 LOC = "p134";# 23 p4-6 LOC = "p131";# 24 p4-8 LOC = "p112";# 13 p4-11 LOC = "p26"; # 14 p9-4 LOC = "p23"; # 15 p9-6 LOC = "p21"; # 16 p9-8 LOC = "p140";# 9 p4-3 LOC = "p135";# 10 p4-5 LOC = "p132";# 11 p4-7 LOC = "p130";# 12 p4-9

Vi Microsystems Pvt. Ltd.,

[ 69 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ISE Xilinx Test Bench Waveform Result

Vi Microsystems Pvt. Ltd.,

[ 70 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Exp 1k) Verilog code for bidirectional switch using dataflow modelling module bidir(bidi,en,sw,led); inout bidi; input en; input sw; output led;

// inout ie, input as well as output(bidirectional) // input declaration for enable // input declaration for switch //output declaration for led

//expression is evaluvated as soon as one of the operands in the RHS changes(here a , b) and //assigned to the LHS net. //Statements using the assign keyword are executed at the same time.

assign bidi = en ? sw : 1'bz; //when enable input ie en is 1 bidi acts as output and // when en is 0 the bidi is tristated which means it is ready to receive // input from external environment.

assign led = bidi;

// the value at bidi is always displayed in led. i.e when it // acts as a output the value at bidi is displayed in led // similarly when bidi acts as input , the value at input is displayed in led L3

endmodule

User Constraint File #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "bidi" LOC = "p59" ; NET "en" loc = "p6"; NET "sw" LOC = "p18" ; NET "led" LOC = "p33" ;

#PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE

Vi Microsystems Pvt. Ltd.,

[ 71 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ISE Xilinx Test Bench Waveform Result

Vi Microsystems Pvt. Ltd.,

[ 72 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

Exp 1 l) Verilog code for synchronous counter with clear and count enable using behavioral modelling module syncntr4bit(out,enable,clk,reset); //module declaration //Output Ports output [3:0] out; // Output of the counter //Input Ports input enable, clk, reset; // enable input, clock input, reset input for counter //Internal Variables reg clkslw; reg [28 : 0] count1; reg [3 : 0] out; //slow clock generation - count block always @ (posedge clk) if (count1 !== 8388608) count1 <= count1 + 1; else count1 <= 1; // slow clock generation block always @ (posedge clk) if (count1 == 4194304) clkslw <= 1; else if (count1 ==8388608) clkslw <= 0; else clkslw <= clkslw; //Code Starts Here always @(posedge clkslw) if (reset) out <= 4'b0000 ; else if (enable) out <= out + 1; else out <= 4'b0000; endmodule

Vi Microsystems Pvt. Ltd.,

[ 73 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

User Constraint File NET "clk" LOC = "p56"; NET "enable" LOC = "p18"; NET "out<3>" LOC = "p33"; NET "out<2>" LOC = "p34"; NET "out<1>" LOC = "p35"; NET "out<0>" LOC = "p39"; NET "reset" LOC = "p6";

Vi Microsystems Pvt. Ltd.,

[ 74 ]

SPARTAN 3E DEVELOPMENT BOARD

VPTB - 05

ISE Xilinx Test Bench Waveform Result

Vi Microsystems Pvt. Ltd.,

[ 75 ]