Winsem2015-16_cp1436_tb01_ece301_vlsi_system_design_lab_new.pdf

VIT UNIVERSITY (Estd. u/s 3 of UGC Act 1956)

SCHOOL OF ELECTRONICS ENGINEERING B.Tech Electronics and Communication Engineering

ECE301 VLSI System Design Lab Laboratory Reference Material

Compiled By Prof. Jagannadha Naidu K Asst. Prof.(Sr.) SENSE VIT University.

List of Tasks: Sl. No

Name of the Task

Reference

V - I Characteristics of PMOS and NMOS

T1

Short Channel and Body effect of a N-MOSFET

T1

2

Analysis of switching characteristics and power consumption of a CMOS inverter

T1

3

Analysis and design of CMOS NAND and NOR gates (Complex CMOS gates)

T1

CMOS implementation of a Boolean Expression (optional)

T1

4

Design an inverter chain to drive off-chip loads

T1

5

Physical design and verification of Digital cells

T1

6

D flip-flop setup and hold timing analysis

T1

1

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--List files

ls –la -- List files with properties pwd

--Show the name of the current working directory

Task No:1

Date: VI Characteristics of PMOS and NMOS

Aim: To plot the V-I characteristics of NMOS and PMOS transistors. Determine the region of operation for the MOSFET. Calculate its threshold voltage and pinch-off voltage. Tool: Cadence Virtuoso , ADE Schematic diagram: NMOS:

Fig1. PMOS

Fig2.

Procedure: 1. 2. 3. 4.

Invoke the Cadence Virtuoso Draw the schematic as shown in the Fig1 for NMOS and Fig2 for PMOS. Invoke ADE XL for device simulation. Perform DC analysis and plot the transfer characteristics and output characteristics.

Model graph: NMOS Ids Vs Vds

NMOS Ids Vs Vgs

PMOS Ids Vs Vds

PMOS Ids Vs Vgs

Calculation: (NMOS & PMOS) Threshold Voltage =

(measured from the graph)

Pinch-off Voltage=

(measured from the graph)

Result and Inference

Task No.:1(a) Short Channel and Body effect of a N-MOSFET

Date:

Aim: To find the channel length modulation co-efficient (λ) and observe body bias effect of N-Channel MOSFET. Tool: Cadence Virtuoso, ADE Schematic diagram: Channel length modulation:

Fig.1

Procedure: Channel length modulation co-efficient: 1. 2. 3. 4.

Invoke Virtuoso Draw the schematic of the Fig1. Invoke ADE for device simulation. Perform DC analysis, sweep the source drain voltage (Vds) from 0-1.8V and plot the output current (ID). 5. Note down two values of ID1 and ID2 for two arbitrary values (Vds1 and Vds2) of Vds in saturation region. 6. Calculate the Channel length modulation co-efficient (λ) using the formula

ID1 1  VDS1 = ID2 1  VDS 2 7. Plot the output characteristics Ids Vs Vgs, for different body bias voltage. Model Graph: Channel Length Modulation ID2 ID1

VDS1

Calculation: Calculate channel length modulation co efficient λ Different Vth values for different VSB Result and Inference:

VDS2

Task No:2

Date:

Analysis of Switching Characteristics and power consumption of a CMOS Inverter Aim: To determine the Voltage Transfer Characteristics (VTC) of CMOS inverter and measure noise margin, propagation delay and power consumption. Tool: Cadence Virtuoso, ADE Voltage Transfer Characteristics: Circuit Diagram:

Fig.1

Model Graph: Voltage Transfer Characteristics:

Fig.2a Gain Plot: (dvout/dvin)

Fig.2b Procedure: 1) Invoke the Cadence Virtuoso 2) Draw the schematic of the CMOS inverter. 3) Invoke ADE XL for device simulation.

4) Perform DC analysis, plot Voltage Transfer Characteristics. 5) Observe the voltage transfer characteristics of the inverter, for different aspect ratio(W/L) Calculation of Noise Margin: 1) From Fig2.b, find out VIL and VIH (these are the operational points of the inverter where dVout/dVin = -1). 2) Noise Margin High (NMH) = VOH(min) - VIH(min) where VOH is the minimum output voltage for logic high. 3) Noise Margin Low (NML) = VIL(max) – VOL(max) where VOL is the maximum output voltage for logic low. Transient Analysis: Circuit Diagram:

Model Graph:

Procedure: 1) Perform Transient analysis and plot the output. 2) Plot .pwr signals at required nodes . Calculation of Propagation Delay and Power Dissipation: 1)

TP = ( TPLH + TPHL) / 2

Where TPHL: Time delay between 50% transition of the raising input voltage and 50% transition of falling output voltage. TPLH: Time delay between 50% transition of the falling input voltage and 50% transition of raising output voltage. 2) Calculate total power consumption. Result and Inference:

Task No:3

Date:

Analysis and design of CMOS NAND and NOR gates Aim: To examine the transient and DC Characteristics of CMOS NAND & NOR Gates for different input transitions. Determine the propagation delays and power dissipation associated with different input transitions. Tool: Cadence Virtuoso, ADE. Schematic Diagram : NAND Gate: Output F  A.B

Inputs A 0 0 1 1

B 0 1 0 1

Output F 1 1 1 0

Circuit Diagram

NOR Gate: Output F  A  B Inputs A 0 0 1 1

B 0 1 0 1

Outputs F 1 0 0 0

Circuit Diagram

Procedure: 1. 2. 3. 4.

Invoke the cadence Virtuoso Draw the schematic of the CMOS NAND and NOR circuits Invoke ADE for device simulation. Perform DC analysis and plot the transfer characteristics for different input transitions as shown in model graph. 5. Perform the Transient analysis and calculate propagation delay of the circuit

Model Graph DC Characteristics: NAND Gate:

NOR Gate:

Transient Analysis:

Timing Diagram for NAND Gate:

Timing Diagram for NOR Gate:

Tabulation: NAND Gate:

NOR Gate:

Result and Inference:

Task No:3(a)

Date:

CMOS implementation of a Boolean Expression Aim: To implement a CMOS circuit for the given expression Y   A.B  C  . A  B  and verify its functionality. Tool: Cadence Virtuoso, ADE. Truth Table: Input A

B

Output C

Y

0 0 0

0 0 1

0 1 0

1 1 1

0

1

1

0

1

0

0

1

1 1

0 1

1 0

0 0

1

1

1

0

Circuit Diagram:

Fig.1 Procedure: 1. 2. 3. 4. 5.

Invoke the Cadence Virtuoso. Draw the schematic of the Circuit shown in Fig.1. Invoke the Cadence ADE for device simulation. Perform Transient analysis. Verify the functionality of the circuit for the different input combinations.

Model Graph:

V(A)

V(B)

V(C)

V(Y)

Result and Inference:

Task No:4

Date: Designing an inverter chain to drive off-chip loads

AIM: To minimize the delay through an inverter chain Tool: Cadence Virtuoso, ADE. Circuit Diagram:

Fig.1 Procedure: 1. 2. 3. 4. 5.

Invoke the Cadence Virtuoso. Draw the schematic of the Circuit shown in Fig.1. Invoke the Cadence ADE for device simulation. Perform Transient analysis. Verify the functionality and calculate the delay.

Calculation: If CL is given How should the inverters be sized? How many stages are needed to minimize the delay? Design Challenges  Keep signal rise times < gate propagation delays. good for performance and power consumption

 Keeping rise and fall times of the signals of approximately equal values Determine the min. propagation delay. Determine the number of inverters N. What are the gate widths of each inverter in the chain? Results and Inference:

Task No:5

Date: Physical Design of Digital Cells

AIM: To use Cadence Virtuoso to create a CMOS layout for inverter, NAND and NOR. a) Do pre-layout simulations using Spectre. b) Layout a circuit using Cadence Virtuoso. c) Use the Design Rule Checker to check for errors in the layout. d) Perform extraction on the layout and use the Layout Vs. Schematic tool to verify that the layout matches the circuit schematic. e) Use the extracted netlist of the layout to perform post-layout simulation. Tool: Cadence Virtuoso, ADE.

Circuit Diagram Inverter Schematic

Fig.1

Inverter Layout

Fig.2 Procedure: 1. 2. 3. 4.

Invoke the Cadence Virtuoso. Draw the schematic of the Circuit shown in Fig.1. Invoke the Cadence ADE for device simulation. Perform Transient analysis.

5. 6. 7. 8.

Verify the functionality and calculate the delay. Invoke the Cadence Virtuoso Layout editor. Draw the layout of the circuit shown in Fig.1. Run the Design Rule Checker and make sure that you are not violating any process design rules 9. Check Layout Vs. Schematic (LVS) 10. Extract the design, that generates a netlist based layout, including any parasitic capacitances, and resistances. 11. Post-Layout Simulation With Spectre Calculation of Propagation Delay and Power Dissipation: 1)TP = ( TPLH + TPHL) / 2 2) Calculate total power consumption. Result and Inference:

Task No:6

Date: D flip-flop setup and hold timing analysis

Aim: To implement a CMOS circuit for D-flip flop and perform the timing analysis and calculate setup time and hold time. Tool: Cadence Virtuoso, ADE. Circuit Diagram:

Model Graph:

Procedure: 1) 2) 3) 4) 5)

Invoke the Cadence Virtuoso. Draw the schematic of the D-flip flop. Invoke the Cadence ADE for device simulation. Perform Transient analysis. Plot the waveforms for input CLK (clock), D (input), Q (output) and observe the waveforms and calculate the setup time and hold time.

Result and Inference: 1. Setup time of D flip flop = _________ 2. Hold Time of D flip flop = _________ 3. Clock to Q delay of D flip flop = ____ Output of the flip flop will be metastable state if setup and hold time of flip flop is not met.