Documentation

MULTI LEVEL INVERTER WITH DIFFERENT PULSE WIDTH MODULATION TECHNIQUES

A Project Report Submitted To JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY KAKINADA In partial fulfillment of the requirement for the award of Degree of BACHELOR OF TECHNOLOGY IN ELECTRICAL AND ELECTRONICS ENGINEERING Submitted by T.VENKATESH G.HARINI G.SARANYA G.SRINIVAS

(16AJ5A0221) (15AJ1A0206) (16AJ5A0208) (15AJ1A0209)

Under the Esteemed Guidance of

Mr. CH.CHINNA VEERAIAH M.Tech,LMISTE Assistant Professor DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

AMRITASAI INSTITUTE OF SCIENCE AND TECHNOLOGY Accredited by NAAC with “A” Grade Approved By AICTE, NEW DELHI; PERMANENTLY AFFLIATED TO JNTU, KAKINADA

(AN ISO 9000 – 2008 CERTIFIED INSTITUTION) PARITALA, KRISHNA DISTRICT – 521 180 (A.P)

APRIL, 2019

AMRITASAI INSTITUTE OF SCIENCE AND TECHNOLOGY Accredited by NAAC with “A” Grade Approved By AICTE, NEW DELHI; PERMANENTLY AFFLIATED TO JNTU, KAKINADA

(AN ISO 9000 – 2008 CERTIFIED INSTITUTION) PARITALA, KRISHNA DISTRICT – 521 180 (A.P)

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

CERTIFICATE This is to certify that the project entitled “MULTILEVEL INVERTER WITH DIFFERENT PULSE WIDTH MODULATION TECHNIQUES” was successfully carried out by T.VENKATESH, G.HARINI, G.SARANYA and P.GOPI in partial fulfillment for the award of the Bachelor of Technology in ELECTRICAL AND ELECTRONICS ENGINEERING by JNTU KAKINADA during the academic year 2015-2019.

PROJECT GUIDE Mr. CH.CHINNA VEERAIAH M.Tech,LMISTE. Assistant Professor

HEAD OF THE DEPARTMENT Mr.CH.CHINNA VEERAIAH M.Tech,LMISTE Associate Professor

EXTERNAL EXAMINER

ACKNOWLEDGMENT We would like to express our sincere gratitude to Mr. CH.CHINNA VEERAIAH M.Tech,LMISTE,Assistant Professor, and Department of Electrical Engineering for her excellent and expert guidance and motivation which led to the successful completion of this project. She was very helpful in extending all the necessary facilities of the department. We express our profound gratitude to Sri. CH.CHINNA VEERAIAH M.Tech,LMISTES,Associate Professor and Head of Department for his indispensable encouragement with his salience with his guidelines and suggestions throughout the work. We thank Dr.M.SASIDHAR, Principal of Amrita Sai Institute of Science and Technology, for providing excellent academic environment in the college. We are obliged to Dr.K.SAI MANOJ,CEO of Amrita Sai Institute of Science and Technology,Who provide us with this work on project in R&D lab and helped making successfully. We are also indebted to all the faculty members of the department of Electrical Engineering for their direct or indirect suggestion throughout the period of our study. But, for their kind help and expertise in their respective fields, it would have been difficult to complete this project. We gratefully acknowledge their contributions. We would also wish to thank all my well-wishers, friends and others who have directly or indirectly helped me to complete this project.Last but not the least We should extend our sincere thanks to all those who contributed directly or indirectly in these success of this project. Our acknowledgements are in concluded with expressing our gratefulness to our parents who have given a great support.

Project Associates: T.VENKATESH G.HARINI G.SARANYA G.SRINIVAS

(16AJ5A0221) (15AJ1A0206) (16AJ5A0208) (15AJ1A0209)

ABSTRACT Multilevel inverter has a capability of handling high voltage, high power with less harmonic distortion .The main objective of this topology is to increase number of voltage levels with a low number of switches and sources output without adding any complexity to the power circuit . the main merit of the new topology is to reduce the lower harmonic distortions ,low electromagnetic interference and high output voltage .A multilevel inverter not only achieves high power ratings but also improves the performance of the whole system in terms of harmonics dv/dt stresses and stresses in bearings of motors. This paper present a novel multi-level inverter topology using one bidirectional switch with other unidirectional switches and which is implemented in single-phase 7- level voltage level. Simulation result of and 7- level can be obtained by MATLAB/ SIMULINK software multi-level inverter using different PWM technique. This topology has less count of power switches and less complexity as compare to other multi-level inverter. For 7-level multilevel inverter multicarrier PWM technique is used to generate different output.

CHAPTER-1

INTRODUCTION The concept of multilevel converters has been introduced since 1975. In recent years, multi-level inverter has drawn a great attention in industry, due to use in high power and high voltage application [1-3]. The word ‗multi-level inverter‘ was first introduced in year 1970s and 1980s [4-6]. Multi-level inverter basically start with three voltage levels [6] that can used in high power medium voltage application due to its advantage over the two levels inverter such as, low switching frequency hence reduction in switching losses, lower harmonic, low common mode voltage. Output voltage of multilevel inverter produces a staircase waveform, in other word multiple step voltage waveform which appears like a sinusoidal waveform. Multilevel inverter has some drawback that by increasing the number of voltage levels, higher numbers of semiconductor switches required with separate gate driver circuit. Due to this it increase the size and complexity of the circuits, different pulse - width modulation (PWM) techniques are used to control [7] the output voltage within multi-level inverter. The conventional multi-level inverters topology can be classified as Diode clamped multilevel inverter (DCMLI) [8, 10], Flying capacitor inverter (FCMLI) [1], cascaded H-bridge multilevel inverter (CHBMLI) [9,12]. Diode clamped multilevel inverter are also called as neutral point clamped multilevel inverter proposed by nabae [6] and they use clamped diode, dc capacitor for the generation of Ac voltage. The flying capacitor inverter uses extra capacitor to clamp the connecting point of semiconductor devices which are connected in series. Cascaded h-bridge multilevel inverter consists of separate dc links for each h-bridge cell so it is easily controllable. Cascaded h-bridge multilevel inverter has some drawback that by increasing the number of voltage levels numbers of switching devices given by 2(N+1) also increase. Where N= number of voltage levels. Due to increase in number of voltage levels circuit become complex, efficiency and reliability may be reduced. This paper present a new multilevel inverter topology using H-bridge which is implemented in single -phase . This paper present 7-level multilevel inverter with different PWM technique which is used for controlling the output voltage within inverter. Multicarrier PWM technique is used to generate different output voltage level for 7-level. This new multilevel inverter topology as less number of switches.

1.2 MOTIVATION Around the world more than 1.2 billion people lack access to basic electricity service .Standalone photovoltaic is an off grid mode can also be used by billions of people living in remote areas with no access to utility grid .Disruption of electricity can last for weeks on end as transmission lines are repaired .Generating electricity from solar energy through the process of photovoltaic can used to light our homes.

CHAPTER-2

LITERATURE REVIEW The main components of standalone systems are PV array, dc-dc converters and battery energy storage element ,switching devices,voltage source inverter and load.

Fig 2.1 block diagram of standalone photovoltaic system The proposed system consists of cascaded boost converter in first stage and Seven-level inverter at second stage which provides AC voltage of required magnitude and frequency.

INVERTER

An inverter is an electrical device which converts DC voltage, almost always from batteries, into standard household AC voltage so that it is able to be used by common appliances. In short, an inverter converts direct current into alternating current. Direct current is used in many of the small electrical equipment such as solar power systems, since solar cells is only able to produce DC. They are also used in places where a small amount of voltage is to be used or produced such as power batteries which produce only DC. Other than these fuel cells and other power sources also produce DC.

But then the question which arises here is that why there is a need to covert direct Current to an alternating Current? The answer to this question is the simplest one. We all know that the main electricity supplied to our homes from the power stations is Alternating current at 220 Volts. That’s one main reason that the electrical equipment which require high voltages and currents are manufactured such that they work on AC since it is supplied to our homes. Other than this, AC power is widely used and since most of the appliances require a relatively higher amount of power than DC can supply, since DC power is designed to work on low voltages. So due to the reason that the power produced by DC producing devices has to be made available to our regular appliances, we need inverters now a days.

Most inverters are of the variable voltage, variable frequency design. They consist of a converter section, a bus capacitor section and an inverting section. The converter section uses semiconductor devices to rectify (convert) the incoming fixed voltage, fixed frequency 3-phase AC power to DC voltage which is stored in the bus capacitor bank. There it becomes a steady source of current for the power devices which are located in what is known as the inverting section. The inverting section absorbs power from the DC bus cap bank, inverts it back to simulated 3-Phase AC sinewaves of varying voltage and varying frequency that are typically used to vary the speed of a 3-phase induction motor.

Applications: Inverters are used for a variety of applications that range from small car adapters to household or office applications, and large grid systems. 

Uninterruptible power supplies



As standalone inverters



In solar power systems



As a building block of a switched mode power supply.

CHAPTER-3

3.1 Seven level inverter structure It uses three level PV string of same rating with two stage conversion for extraction of energy .The output voltage of boot converter forms the dc bus with magnitude E and 2E volts respectively .Seven level inverter converts the regulated dc to seven level ac voltage of required magnitude and frequency.

The quality of distinct levels in the output voltage of asymmetrical multilevel inverter is well defined by m=2N+1.when the number of dc sources is three (i.e. .N=3), the number of levels would be ,m=2N+1=2 (3) +1=7.hence when the quality of dc sources is three ,a seven level output is obtained. In seven level inverter there are seven switches namely Sa,Sb,Sc,S1,S2,S3,S4 as show in fig3.1 the multilevel output voltage can be obtained by closing the appropriate switches mentioned in the switching sequence table 1.proper switching will produce voltage levels of 0,E,2E,3E,-E,-2E and -3E at the inverter output.

Table 1 switching pattern for 7 level inverter The quality of voltage depends on the modulation strategy adopted. Various modulation schemes with unique features have been reported in literature [5],[6]. Unipolar level shifted pulse width modulation is used as the switching scheme Seven level inverter.

LS-PWM with switching signals generation is shown in fig3.1 comparison of lower, middle and upper carrier with rectified sinusoidal signal will generate signals A,B and C respectively as shown figure.Signal D is generated the detection of zero crossing of fundamental frequency signals.

Ga=B.C`.D+A.B`.D` Gb=D.(C+B) Gc=A.B`.D+B.C`.D` G1=A`+D.(C+B`) G2=B.C`+D.(A+C) G3=A`+A.B`.D`+C.D` G4=D`.(B+C)

It is possible to control the inverter output voltage by adjusting the modulation index (Ma).modulation index for the seven level inverter can be defined as

Ma=Am/3Ac Where Ac is the peak to peak value of triangular carrier signals, Am is the peak value of the rectified sinusoidal reference signal[4].

CHAPTER-4 CONVENTIONAL TWO LEVEL AND THREE LEVEL VOLTAGE SOURCE INVERTERS

CONVENTIONAL TWO LEVEL AND THREE LEVEL VOLTAGE SOURCE INVERTERS Switched mode DC to AC inverters produce a sinusoidal AC output voltage whose magnitude and frequency can be controlled (Kajaer et al 2005). They are widely used in the area of AC induction motor drives. Half bridge inverter is the simplest topology which produces the two level square wave output voltage waveform. Circuit configuration of half bridge topology is given in Figure 4.1. To avoid shoot through fault, either switch S1 or S2 is turned ON at a time to give a load voltage, VAO of +VS/2 as shown in Figure 4.1. To complete one cycle, S1 is turned OFF and S2 is turned ON to give a load voltage, VAO of -VS/2.

Figure 4.1 Two level voltage source inverter

Figure 4.2 Three level voltage source inverter

Circuit configuration of full bridge topology is given in Figure 3.2. This topology is used to synthesize a three level square wave output voltage waveform. The three possible levels are given in Table 3.1. Neither S1, S3 nor S2 and S4 should be closed at the same time. If so, a short circuit will occur across the DC source. Table 4.1 Load voltage with corresponding conducting switches

Some of the problems of classical inverters are summarized as follows:

1.The entire DC voltage appears across each switch when it is OFF. This will be greater than the voltage rating of the OFF. This will be greater than the voltage rating of the OFF. 2.The devices will not automatically share the voltage in the to overcome this OFF state because of the differences in their leakage currents. High value of parallel resistors can be used static sharing problem. 3. More seriously, the devices will not share the voltage during switching due to variations in switching speed. Special gate drive techniques and special snubber is required for dynamic sharing. 4. Two level output causes very large voltage steps on the load which will create a problem for motor insulation. 5. Harmonic content of the output voltage is larger for high switching frequency. On the flip side, classical inverters too have finite advantages. They are, 6. Standard PWM techniques can be used. 7. Number of power circuit components is less as compared to other inverter circuit 8. Redundancy can be incorporated to improve reliability by using more series devices than actually required. From the above discussion, it is clear that the conventional inverter have many drawbacks than merits. So alternative solution to meet the high power demand is through multilevel inverter concept.

CHAPTER-5 MULTILEVEL INVERTER

5.1 MULTILEVEL INVERTER Numerous industrial applications have begun to use high power apparatus in recent years. Some medium voltage motor drives and utility applications require medium voltage and megawatt power levels. For a medium voltage grid, it is troublesome to connect only one power semiconductor switch directly. As a result, a multilevel inverter structure has been introduced as an alternative in medium and high power applications (Jose Rodriguez et al 2007). With this type of inverters, improvements in the harmonic quality of the output voltage can be achieved. Multilevel inverter not only achieves high power ratings, but also enables the use of renewable fuel cells can be easily interfaced to a multilevel inverter system for medium and high power applications (Venkatachalam Kumar Chinnaiyan et al 2013).

Multilevel inverter produces a desired AC voltage waveform from several levels of DC voltages. These DC voltages may be or may not be equal. AC voltage produced from these DC voltages is of stepped waveform. One drawback of using multilevel inverter is to approximate sinusoidal waveforms from stepped waveform. The staircase waveform produced by the multilevel inverter contains sharp transitions. Fourier series theory makes clear that this phenomenon results in harmonics, in addition to the fundamental frequency of the sinusoidal waveform (John Chiasson et al 2003).

The power quality of the power system is affected by the harmonics generated on the AC side. The power quality of the multilevel inverter is improved by performing the power conversion in small voltage steps. Multilevel inverter widely replaces the conventional two level three phase Voltage Source Inverter (VSI) by its performance such as lower switching stress (dv/dt) and lower THD on output voltage (Jose Rodriguez et al 2007).

The multilevel inverters start from three levels. As the number of levels reach infinity, the output THD approaches zero. The number of the achievable voltage levels is limited by voltage unbalance problems, voltage achievable voltage levels is limited by voltage unbalance problems, voltage clamping requirement, circuit layout and packaging constraints (Nabae et al level inverter that uses high switching frequency PWM. The attractive features of a multilevel converter can be briefly summarized as follows:

1. Multilevel inverters not only can generate the output voltages with very low distortion, but also can reduce the dv/dt with very low stresses. Therefore electromagnetic compatibility problems can be reduced. 2. Multilevel inverters produce smaller CM voltage; Therefore, the stress in the bearings of a motor connected to a multilevel inverter drive can be reduced. Furthermore, CM voltage can be eliminated by using advanced modulation techniques. 3. Multilevel inverters will draw input current with low distortion.

4. Multilevel inverters can operate at both fundamental switching frequency and high switching frequency PWM. It should be noted that lower switching frequency usually means lower switching loss and higher efficiency.

The main drawback of multilevel inverters is that the number of switches increases with the number of levels. In early stages of multilevel inverters, development of control circuitry for large number of power inverters, development of control circuitry for large number of power and FPGA devices easily solved this inconvenience. Other drawback of this inverter is the requirement of multiple numbers of DC voltage sources, mainly provided by capacitors. Balancing the voltage sources during operation under different load conditions is an important challenge.

In spite of these drawbacks, introducing multilevel inverters will decrease switching losses occurred in the power device. By comparing with two level inverters, smaller size filter is required for the elimination of harmonics. This reduces the inverter weight, dimension and cost. Many multilevel inverter topologies have been proposed during the last two decades. Contemporary research has evolved novel inverter topologies and unique modulation schemes. Moreover, three different major multilevel inverter structures have been reported in the literature.

MULTILEVEL CONCEPT

The concept of multilevel inverters has been introduced since 1975. However, the elementary concept of a multilevel inverter to achieve high power is to use a series of power semiconductor switches with several low voltage DC sources to perform power conversion by synthesizing a staircase voltage waveform. One phase leg of multilevel inverter is shown in Figure5.1. In this schematic diagram, operations of semiconductors are shown by an ideal switch with several states. The switching algorithms of switches and commutation of them allow the addition of the capacitor voltages as temporary DC voltage sources, whereas the semiconductors should withstand limited voltages of capacitors.

Figure 5.1 One phase leg of a multilevel inverter

Nearly for the three decades, multilevel inverters are being used in the world of power electronics. They are named by the number of voltage levels they generate and the different topologies they have. Usually the number of output voltage levels is odd instead of even. It means that the definition of a zero voltage level in the output of inverter, like in three level or in five level inverters, makes it more sinusoidal with less harmonics.

5.2 Diode Clamped Multilevel Inverter Three phase eleven level diode clamped inverter is shown in Figure 3.4. Each phase of the inverter shares a common DC bus, which has been subdivided by five capacitors into six levels. The voltage across each capacitor is Vdc and the voltage stress across each switching device is limited to Vdc through the clamping diodes. Switching states of diode clamped multilevel inverter is given in Table 5.1

Figure 5.2 Three phase eleven level structure of a diode clamped inverter

Table 5.1 Diode clamped eleven level inverter voltage levels and corresponding switch states

Table 3.2 lists the output voltage levels possible for one phase of the inverter with the negative DC rail voltage V0 as a reference. Switch state condition one (1) means the switch is ON, and zero (0) means the switch is OFF. Each phase has five complementary switch pairs such that turning ON one of the switches of the pair requires that the other complementary switch be turned OFF(Alireza Nami et al 2011). The complementary switch pairs for phase leg-A are (Sa1, Sa’1), (Sa2, Sa’2), (Sa3, Sa’3), (Sa4, Sa’4) and (Sa5, Sa’5). The switches that are ON for a particular phase leg is always adjacent and in series. For an eleven level inverter, a set of five switches are ON at any given time. The resulting line voltage is an eleven level staircase waveform as shown in Figure 3.5. The line voltage Va-b consists of a phase leg-A voltage and phase leg-B voltage. This means that NL level diode clamped inverter has NL level output phase voltages and a (2NL -1) level output line voltages.

Figure 5.2 Line voltage waveform of eleven level diode clamped inverter

ADVANTAGES OF DIODE CLAMPED MULTILEVEL INVERTER: Major advantages of diode clamped multilevel inverter are listed as follows: 1. When the number of levels is high enough, the harmonic content is low enough to avoid the need for filters. 2. Inverter efficiency is high because all devices are switched at the fundamental frequency. 3. The control method is simple.

DISADVANTAGES OF DIODE CLAMPED MULTILEVEL INVERTER: Disadvantages of the diode clamped multilevel inverter can be listed as follows: 1. Excessive clamping diodes are required when the number of levels is high. 2. It is difficult to control the real power flow of the individual converter.

5.3 Flying Capacitor Multilevel Inverter The structure of this inverter is similar to that of the diode clamped inverter. Instead of using clamping diodes, the inverter uses capacitors in their place. The circuit topology of the flying capacitor multilevel inverter is shown in Figure 3.6. This topology has a ladder structure of DC side capacitors. The voltage on each capacitor differs from that of the next capacitor (Anshuman Shukla et al 2008).

The voltage increment between two adjacent capacitor legs gives the size of the voltage steps in the output waveform. One advantage of the flying capacitor based inverter is that it has redundancies for inner voltage levels. Unlike the diode clamped inverter, the flying capacitor inverter does not require all of the switches that are ON (conducting) in a consecutive series (Chunmei Feng et al 2007). Moreover, the flying capacitor inverter has phase redundancies, whereas the diode clamped inverter has only line-line redundancies. These redundancies allow a choice of charging and discharging specific capacitors and can be incorporated in the control system for balancing the voltages across the various levels.

Figure 5.3 Three phase eleven level structure of a flying capacitor inverter In addition to the (NL-1) DC link capacitors, the NL-level flying capacitor multilevel inverter will require (NL -1) × (NL -2)/2 auxiliary capacitors per phase if the voltage rating of the capacitors is identical to that of the main switches. One application proposed in the literature for the multilevel flying capacitor is static var generation.

ADVANTAGES: Advantages of the flying capacitor multilevel inverter are summarized as follows: 1. Provides switch combination redundancy for balancing different voltage levels. 2. Real and reactive power flow can be controlled. 3. The large number of capacitors enables the inverter to ride through short duration outages and deep voltage sags.

DISADVANTEGES: On the flip side, flying capacitor multilevel has some disadvantages. They are, 1. Control is complicated to track the voltage levels of all the capacitors. 2. Also, pre-charging of all the capacitors to the same voltage level and startup are complex. 3. Switching utilization and efficiency are poor for real power transmission. 4. The large numbers of capacitors are both more expensive and bulky than clamping diodes in multilevel diode clamped converters. 5. Packaging is also more difficult in inverters with a large number of levels.

5.4 Cascaded H-bridge Multilevel Inverter: Each Separate DC Source (SDCS) is connected to a single phase full bridge or H-bridge inverter (Anup Kumar Panda & Yellasiri Suresh 2012). A single phase structure of eleven level cascaded inverter is illustrated in Figure 3.7.Each inverter level can generate three different voltage outputs, +Vdc, 0 and –Vdc by connecting the DC source to the AC output by different combinations of the four switches, S1, S2, S3 and S4. To obtain +Vdc, switches S1 and S4 are turned ON, wherea– Vdc can be obtained by turning ON switches S2 and S3. By turning ON S1 and S2 or S3 and S4, the output voltage of zero obtained. The AC outputs of different full bridge inverter levels are connected in series such that the synthesized voltage waveform is the sum of the inverter outputs (Krishna Kumar Gupta & Shailendra Jain 2013).

Figure 5.4 Cascaded H-bridge eleven level inverter Phase voltage waveform for eleven level cascaded H-bridge inverter is shown in Figure 3.8. The number of output phase voltage levels (NL) in a cascaded inverter is defined by NL = 2s+1, where s is the number of separate DC sources. Output phase voltage Van is given in Equation 3.1.

van = va1 + va2 + va3 + va4 + va5 (3.1)

Figure 5.5 Output phase voltage waveform of eleven level cascaded inverter

ADVANTAGES: Major advantages of the cascaded inverter can be summarized as follows: 1. The number of possible output voltage levels is more than twice the number of DC sources (NL = 2s + 1). 2. The series of H-bridges makes for modularized layout and packaging. This will make the manufacturing process to be done more quick and cheap.

DISADVANTAGES: Major disadvantage of the cascaded inverter is given below: 1. It needs separate DC sources for real power conversions, thereby limiting its applications.

5.5 Component Requirements Component requirements of diode clamped, flying capacitor and cascaded H-bridge multilevel inverters for number of levels is given in Table 5.6. From the Table 5.6, cascaded inverter requires the least number of components and has the potential for utility interface applications because of its capabilities for applying modulation and soft-switching techniques.

Table 5.6 Components required for different MLI topologies

The switching devices do not encounter any voltage-sharing problems. For this reason, multilevel inverters can easily be applied for high power applications. The system kV rating can be extended beyond the limits of an individual device through the voltage clamping techniques. So, diode clamped inverters are used more in high power motor drive applications (Dietmar Krug et al 2007). The intriguing feature of the multilevel inverter structures is their ability to scale up the kVA rating and also to improve the harmonic performance in the output voltage. By considering the cost of semiconductor switches and passive components, converter losses and simplicity of modulation schemes, cascaded H-bridge inverter is also a best choice for medium and high power applications (Shuai Lu & Keith Corzine 2007).

CHAPTER-6 MODES OF OPERATION

The block diagram of multi-level inverter using optimization topology is shown in Fig. 2.1. In this figure, the right side h-bridge is connected which is used to generates the required positive level is called positive level generator and generate negative level is called negative level generator.

Figure6.1: single phase7-Level Multilevel Inverter with Converting Its Optimal Structure The main purpose of this paper is to control the EMI, minimize the total harmonic distortion with different PWM techniques using Optimization topology and it also minimizes power semiconductor switches than conventional multilevel inverter. For a conventional single-phase 7-level inverter model, it uses 12 switches, whereas the proposed model uses only 9 switches in which one switch is bidirectional [12]. This optimization multilevel inverter easily extends to higher voltage levels by increasing the middle section as shown in Fig. 2.1 fixed dc voltage values. In comparison with a cascade topology, it requires just one-third of isolated power supplies used in a cascade-type inverter. The operation of the proposed topology has been discussed in detail and has been verified with the help of simulations. The proposed topology is a symmetrical topology since all the values of all voltage sources are same. This MLI topology has been proposed which reduces the overall number of switching devices from conventional MLI topology. They has less count of power devices as compare to cascaded h-bridge MLI as shown in Fig.1. It has three separate dc source as 7-level MLI. The new proposed topology can be easily extended to any required number of voltage levels by increasing the middle part of circuit. This proposed topology is symmetrical topology with all voltage sources have equal value and same to be used for threephase MLI. The proposed 7-level MLI can operates in different modes which are as given. Operation of the singlephase 7-level MLI with reversing Voltage topology can be easily explained with the help of fig. 1and table 1. When switches T1 T2, T4, T7 and T10 are turned ―on‖ the output voltage will be ―Vdc‖ (i.e., level 1). The output voltage will be ―2Vdc‖ (i.e., level 2) when switches T3, T4, T7 and T10 are turned ―on‖. When T3, T5, T7 and T10 switches are turned ―on‖ the output voltage will be ―3Vdc‖ (i.e., level 3). When switches T6, T7 and T10 are turned ―on‖ the output voltage is zero (i.e., level 0). Switches T7, T8, T9 and T10 are used for a complementary pair. When T7 and T10 are turned ―on‖ together, positive half cycle (level +1, level +2, level +3) can be generated and when T8 and T9 are turned ―on‖ together, negative half cycle (level -1, level 2, level -3) .The operation of this topology can also be easily understood by mode of operation of single-phase 7-level MLI shown in figure 2. Each voltage source ―Vdc‖ is required 100V. There are seven sufficient switching modes in generating the multistep level for a 7-level MLI.

TABLE 6.1: Switching modes of Different Switches Used in 7-level MLI.

6.1 OPERATING MODE 6.1.1 MODES OF OPERATION FOR POSITIVE LEVEL GENERATORS: MODE-0:  When switches T6, T7 and T10 are turned ON.  Then the output voltage is 0.

Fig .a : 0 Level , Vo=0v

MODE-1:  When switches T1,T2,T4,T7 and T10 are turned ON  Then the output voltage is “Vdc”.

Fig. b : 1 Level , Vo=1v

MODE-2:  When switches T3,T4,T7 and T10 are turned ON.  Then the output voltage is “2Vdc”.

Fig .c : 2 Level , Vo=2v

MODE-3:  When switches T3,T5,T7 and T10 are turned ON.  Then the output voltage is “3Vdc”.

Fig.d : 3 Level , Vo=3v

6.1.2 MODES OF OPERATION FOR NEGATIVE LEVEL GENERATORS: MODE-4:  When switches T1,T2,T4,T9 are turned ON.  Then the output voltage is “-Vdc”.

Fig. e : -1 Level , Vo=-1v

MODE-5:  When switches T3,T4,T8,T9 are turned ON.  Then the output voltage is “-2Vdc”.

Fig.f : -2 Level , Vo=-2v

MODE-6:  When switches T3,T5,T7,T9 are turned ON.  Then the output voltage is “-3Vdc”.

CHAPTER-7 MODULATION TECHNIQUES

7.1MODULATION TECHNIQUES: Modulation is the process of switching the power electronic device in a power converter from one state to another. All modulations are aimed at generating a stepped waveform that best approximates an arbitrary reference signal with adjustable amplitude, frequency and phase fundamental component that is usually sinusoidal in steady state. Each topology has different switching configuration to achieve commanded output voltage. Modulation strategies are responsible for synthesizing reference control signals and for keeping all voltage sources balanced. The requirements of multilevel modulation algorithm are as follows.       

Voltage quality should be good Modular design Simultaneous switching of multiple voltage levels is not allowed. Switching frequency of power devices should be minimized. Power modules should share the load equally. Control algorithm should be simple. Implementation cost should be low.

In many industrial applications, the output voltage of inverters should be controlled to overcome the changes in input voltage and to meet the need of voltage/frequency control. It is obvious that harmonics in the output voltage depend on the selected modulation technique. Using more number of semiconductor devices and switching redundancies, bring a higher level of complexity in multilevel topologies, when compared with a two level inverter.

Figure 7.1 Classification of modulation techniques

However, this complexity can be used to improve the modulation technique, such as, minimizing the switching frequency, reducing the common-mode voltage or balancing the DC link voltages (Poh Chiang et al 2005). The modulation methods used in multilevel inverters can be classified according to switching frequency (Jose Rodriguez et al 2002) as shown in Figure 3.9. Methods that work with high switching frequencies have many commutations for the power semiconductors in one cycle of the fundamental output voltage. A very popular method in industrial applications is the classic carrier-based Sinusoidal PWM that uses the phase shifting technique to reduce the harmonics in the load voltage (Ilhami Colak & Ersan Kabalci 2013). Another interesting alternative is the SVM strategy, which has beenused in three level inverters (Amit Kumar Gupta & Ashwin Khambadkone 2007). Table 7.1 Applicability of modulation techniques for different multilevel inverter topologies

Methods that work with low switching frequencies generally perform one or two commutations of the power semiconductors during one cycle of the output voltages, generating a staircase waveform. Based on the switching frequency and modulation techniques, their applicability for different type of multilevel inverters are given in Table 3.4. It must be noted that lower switching frequency usually means lower switching loss and higher efficiency. Representatives of this family are the multilevel selective harmonic elimination and the Space Vector Control (SVC). It is found that SVM and SHE are the most widely used modulation techniques for all the types of multilevel inverters (Damoun Ahmadi et al 2011). In continuation of the work done in the past few decades on switching frequency applied to these multilevel inverters, Table 3.5 is formulated. By comparing the switching frequency for the medium and high power applications, fundamental switching frequency is selected to be best suited one.

Table 7.2 Comparison between fundamental switching frequency and high switching frequency

7.2 Space Vector PWM Each multilevel inverter has several switching states which generate different voltage vectors and can be used to modulate the reference (Govindaraju & Baskaran 2010). In SVM, the reference signal is generated from its closest signals. Some vectors have redundant switching states, meaning that they can be generated by more than one switching state. This feature is used to balance the capacitor voltages (Govindaraju & Baskaran 2010, Amit Kumar Gupta & Ashwin Khambadkone 2007). Multilevel SVM must manage this behavior to optimize the search for the modulating vectors and apply an appropriate switching sequence (Wenxi Yao et al 2008). A conceptually different control method for multilevel converters, based on the space-vector theory, has been introduced, which is called space vector control.

7.3 Selective Harmonic Elimination The popular selective harmonic elimination method is also called fundamental switching frequency method which is based on the harmonic elimination theory. The multilevel fundamental switching scheme inherently provides the opportunity to eliminate certain lower order harmonics by varying the times at which certain switches are turned ON and turned OFF. A staircase output voltage waveform is generated by switching ON and OFF the switching devices in the multilevel inverters once during one fundamental cycle. This diminishes the switching losses in the devices. In this method, each switch is turned ON and turned OFF once in a

switching cycle and switching angles are usually chosen based on specific harmonic elimination or minimization of THD in the output voltage. Two ways to eliminate lower order harmonics are; i) By increasing the switching frequency of SPWM and SVM in case of two level inverters or in multicarrier based phase shift modulation for multilevel inverters. ii) By computing the switching angles using SHE techniques. The first method of eliminating low frequency harmonics is limited by the switching losses and the availability of the voltage steps (Govindaraju & Baskaran 2010). SHE techniques comprises the mathematical modelling of output waveform and solving them for switching angles based on the amplitude of the fundamental wave of the output voltage, the order and number of the eliminated harmonics (Vassilios Agelidis et al 2008). Thus, the lower order harmonics are either eliminated or minimised while the higher order harmonics are filtered out in selective harmonic elimination method. Multilevel inverter can produce a quarter wave symmetric stepped voltage waveform synthesized from several DC voltages as shown in Figure 7.2

Figure 7.2 Stepped voltage waveform of multilevel inverter By applying Fourier series analysis, the output voltage can be expressed as

where, n = 1, 3, 5… ‘h’ is the number of DC sources and V1, V2… Vh are the level of DC voltages. The switching angles must satisfy the condition 0< 1< 2 <......< s< ( /2). However, if the switching angles do not satisfy the condition, this method no longer exists. To minimize harmonic distortion and to achieve adjustable amplitude of the fundamental component, upto h-1 harmonic contents can be removed from the voltage waveform. In general, the most significant low frequency harmonics are chosen

for elimination by properly selecting the triggering or switching angles and high frequency harmonic components can be readily removed by using additional filter circuits. The switching angles of the inverter are computed by solving the transcendental equations reflecting each harmonics. A proper starting value of modulation index and initial guess is necessary to solve these equations. Solving these transcendental equations with n number of unknowns is a tedious job. But the switching angles can be calculated offline to eliminate the specific low order harmonics and also switching takes place at the fundamental frequency and hence minimizes the switching losses (Jason et al 2007). In other words, only a few commutations take place in one cycle increasing efficiency and enabling air cooling. The computation of the switching angle increases with the increase in the voltage levels. With a limitation for the switching angles to be within ( /2), it provides a narrow range of modulation index. This method is limited to open-loop applications and low dynamic performance demanding applications (Cheng et al 2006). The main challenge associated with SHE-PWM technique is to obtain the analytical solution of the system of nonlinear transcendental equations that contain trigonometric terms which in turn provide multiple sets of solutions (Krikor et al 2008). This has been reported in numerous research papers (Faete Filho et al 2011). Several algorithms have been reported in the technical literature, concerning methods of solving the resultant nonlinear transcendental equations, which describe the SHE-PWM problem (Surin Khomfoi & Leon Tolbert 2007, Ayoub Kavousi et al 2012). A sequential homotopy based computation and ant colony algorithm has been done to solve for the switching angles (Sundareswaran et al 2007). The theory of symmetric polynomial, theory of resultant polynomials and the resultant theory have been proposed to solve the polynomial equations obtained from the transcendental equations (John Chiasson et al 2003). With an increase in the number of H-bridges connected in series, the computation increases as the order of the polynomials become very high. In Newton Raphson method of solving these transcendental equations, the switching angles can be computedwith negligible computation effort for any initial guess. This method is derivative dependent and may end in local optima. Further, a judicious choice of the initial values alone will guarantee convergence.

7.4 Sinusoidal Pulse Width Modulation Sinusoidal PWM method is also known as the triangulation,sub harmonic, sub oscillation method, Carrier Based Pulse Width Modulation (CB-PWM) is very popular in industrial applications (Mohamed Dahidah &Vassilios Agelidis 2008). The SPWM scheme is illustrated in Figure 3.11.

Figure 7.3 Sinusoidal pulse width modulation

In this, Vc is the peak value of the triangular carrier wave and Vr is the reference, or modulating signal. For realizing SPWM, a high frequency triangular carrier wave is compared with a sinusoidal reference of the desired frequency. The intersection of sinusoidal reference and triangular waves determines the switching instants and commutation of the modulated pulse. Operating with constant frequency of carrier signal concentrates on voltage harmonics around switching frequency (which is of double the carrierfrequency) and multiples of switching frequency. Carrier based modulation for more than two level inverters require more carrier signals. For NL -level inverter, minimum (NL -1) carrier signals are needed. Each carrier signal is responsible for a pair of switches. Every leg has two switches, one switch is controlled directly by the comparator signal and the other is controlled by its inverting signal. Multiple carrier signals in multilevel inverters create various possibilities of mutual locations of those signals. Typical combinations for multi-carrier systems are,  

Phase Shifted Carriers (PSC) Level Shifted Carriers (LSC) o Phase Disposition (PD) o Phase Opposite Disposition (POD) o Alternative Phase Opposite Disposition (APOD)

7.4.1 Phase shifted carriers This method of carrier signals placement is usually used in H-bridge and FLC converters. It can also be applied in all kinds of multilevel inverters. As in other types of sinusoidal modulation, PSC modulation requires (NL-1) carriers shifted in phase by 360°/ (NL -1), where NL is the number of levels. Each carrier is responsible for a pair of switches in all legs of the converter (Samir Kouro et al 2008). In three phase system, two other phase voltages by comparison with the carriers are generating four more rectangular sequences for the remaining switches. Figure 3.12 presents carrier placement for three level inverter and one of the commanded voltages.

Figure 7.4 Phase shifted carrier modulation

7.4.2 Level shifted carriers Second type of sinusoidal modulation is PWM with level shifted carriers. Difference between those methods is rather small and gathered around the output voltage spectrum. In PD-PWM modulation technique, the major feature of the phase voltage spectrum is the significant first carrier harmonic. This carrier harmonic is a common-mode component across the phase voltages of a three phase inverter, and therefore gets cancelled in the output line voltage. This feature gives the PD-PWM to produce excellent line voltage performance. Consequently, with concentration of harmonics in the first carrier, the harmonic sidebands which of course do not fully get cancelled between the three phase legs have less energy. In POD-PWM control technique, the carrier signals which are above the zero level are in phase and the carrier signals which are below the zero level are in phase of each other and out of phase by 180 to the above signals.

Figure 7.5 Level shifted PWM For APOD, all carriers are in phase opposition by 180 from their respective adjacent carriers. Variants of this type of modulation take the names from mutual locations of the carrier signals as it is shown in Figure 7.5.

CHAPTER-8 MATLAB DIAGRAM AND PROGRAM

8.1MATLAB CIRCIUT

8.2 MATLAB PROGRAM Function [s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12]=fcn(r,c1,c2,c3,c4,c5,c6) s1=0; s2=0; s3=0; s4=0; s5=0; s6=0; s7=0; s8=0; s9=0; s10=0; s11=0; s12=0; If(r>=c1) s1=1; s4=1; s5=1; s8=1; s9=1; s12=1; elseif(rc3) s1=1; s4=1; s5=1;

s8=1; s9=1; s12=1; elseif(r=c2) s1=1; s4=1; s5=1; s8=1; s9=1; s11=1; elseif(r=c3) s1=1; s4=1; s5=1 s7=1; s9=1; s11=1; elseif(r=c4) s1=1; s3=1; s5=1; s7=1; s9=1; s11=1; elseif(r=c5)

s2=1; s3=1; s6=1; s8=1; s10=1; s12=1; elseif(r=c6) s2=1; s3=1; s6=1; s7=1; s10=1; s12=1; else s2=1; s3=1; s6=1; s7=1; s10=1; s11=1; end

CHAPTER-9 MATLAB STRATEGIES

9.1 Carrier arrangement for PDPWM strategy There are different pulse width modulation strategies with different phase relationships. Phase disposition pulse width modulation (PD PWM):- In phase disposition pulse width modulation strategy, where all carrier waveforms are in same phase shown in fig 3.1 for 5-level MLI For 7-level MLI, 8 triangle carriers are required. For 7-level MLI, 8 triangle carriers are required[1-5].

Fig. 9.1: Carrier arrangement for PDPWM strategy (ma=0.9 and mf=20)

9.2 Carrier arrangement for PODPWM strategy Phase opposition disposition pulse width modulation (POD PWM):- In phase opposition disposition pulse width modulation strategy, where all carrier waveforms above zero reference are in phase and below zero reference are 1800 out of phase. Shown in fig3.2[911].

Fig. 9.2: Carrier arrangement for PODPWM strategy (ma=0.9 and mf=20)

9.3 Carrier arrangement for APODP strategy Alternate phase opposition disposition pulse width modulation (APOD PWM):- In alternate phase opposition disposition PWM scheme where every carrier waveform is in out of phase with its neighbor carrier by 1800. Shown in fig 3.3[9-11].

Fig. 9.3: Carrier arrangement for APODP strategy (ma=0.9 and mf=20)

9.4 Sine Phase Opposition Disposition pulse width modulation (SPOD PWM) Fig.3.4 shows the carrier invert sine wave pulse width modulation strategy. A carrier phase shifted PWM for multi-level inverter is used to generate the stepped multi-level output voltage waveform with lower % THD. Multilevel inverter with N levels requires (N1) triangular carriers. In phase shifted PWM, all the triangular carriers have same frequency and same peak to peak amplitude.

Fig. 9.4: Carrier arrangement for PSPWM strategy (ma=0.9 and mf=20)

9.5 Sine Phase Disposition width modulation (SPD PWM) In invert sine wave pulse width modulation strategy, where all carrier waveforms above zero reference are in phase and below zero reference are in phase. Shown in fig 3.5.

Fig. 9.5: Carrier arrangement for ISPWM strategy (ma=0.9 and mf=20)

9.6 OUTPUT WAVEFORM

Fig. 9.6:Output voltage waveform of 7-Level Multilevel Inverter with converting Its Optimal Structure

CHAPTER-10 SIMULATION RESULTS

10.1 FFT analysis by PDPWM for R-L load Table 10.1 shows THD comparison between different PWM techniques. The simulation parameters are as following : dc source voltage is 100V; Frequency of carrier signal is 1 kHz. In this paper, four PWM techniques are used PD, POD, APOD, and PS with different modulation index (Ma). For Ma = 0.9, and Mf = 20, corresponding (%) THD are PS = 19.64, PD = 23.61, POD = 23.61, APOD = 19.74,SPD = 14.76 , SPOD = 15.87 shown in Fig. 4.3 – 4.6. Based on the PWM techniques, the harmonic spectrum was analysed using the FFT harmonic spectrum was analysed using the FFT Window in MATLAB/Simulink.

Fig.10.1: FFT analysis by PDPWM for R-L load (Ma=0.9, Mf=40)

10.2 FFT analysis by PODPWM for R- load

Fig.10.2: FFT analysis by PODPWM for R- load (Ma=0.9, Mf=40

10.3 FFT analysis by APODPWM for R-L load

Fig. 10.3: FFT analysis by APODPWM for R-L load (Ma=0.9, Mf=40).

10.4 FFT analysis by SPDWM for R-L load

Fig. 10.4: FFT analysis by SPDWM for R-L load (Ma=0.9, Mf=40).

10.5 FFT analysis by SPODWM for R-L load

Fig. 10.5: FFT analysis by SPODWM for R-L load (Ma=0.9, Mf=40).

TABLE-10.1 Comparison between different multilevel inverter topologies

TABLE-10.3 Comparison between different multilevel inverter topologies

ADVANTAGES 

Reduced harmonic distortion:



Common-mode (CM) voltage:



Input current: Multilevel converters can draw input current with low distortion. Switching frequency: Multilevel converters can operate at both fundamental switching frequency and high switching



Multilevel inverters not only can generate the output voltages with very low distortion , but also can reduce the dv/dt stresses. Therefore , electromagnetic compatibility(EMC) problems can be reduced. Multilevel converters produce smaller CM voltage. Therefore, the stress in the bearings of a motor connected to a multilevel motor drive can be reduced.

frequency PWM. It should be noted that lower switching frequency usually means lower switching loss and higher efficiency.

APPILICATIONS      

High voltage and Medium voltage motor drives. High voltage dc transmission. Flexible AC transmission system(FACTS). Traction. Active filtering. Utility interface for renewable systems.

CONCLUSION In this paper, a 7-level multi-level inverter using optimal topology is proposed with different PWM techniques and proposed MLI topology with different PWM techniques is used to generate 7-level output phase voltage .This topology has been discussed with presented topology. It is proved that the proposed work of Single phase 7-level MLI output voltage total harmonics distortion is reduced and improve the efficiency of system compare with different conventional topologies of single phase 7-level MLI.Table-3 shows the number of power switches [IGBTs] and output voltage steps in the proposed topology. This proposed MLI topology requires less number of components as compared to conventional MLI inverters.

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