Fabless Design: Report Of The Niti Aayog Working Committee Towards Creating A Revolution In Fabless Design

Fabless Design Report of the NITI Aayog Working Committee towards creating a revolution in Fabless design

Table of Contents I.

Message from Committee

the

Chairman

of

the

II.

Glossary ................................................................................... 2

III.

Introduction ............................................................................ 5

IV.

Semiconductor Fabless Design - The Need for Transformation .......................................................... 6

V.

“Design” in India- An integral part of “Make in India” ........................................................................ 6 Accelerating Innovation ......................................................................... 6

VI.

Semiconductor Industry - Value Chain and Current state ..................................................................... 9 IC/SOC design - Design Flow and requirement .................................................9

VII. Design-

The essential element for a thriving Fabless Ecosystem .................................................... 10 Infrastructure ...................................................................................... 10 Tools, Flows and Methodology.............................................................. 12 Architecture......................................................................................... 14 Logic Design ........................................................................................ 15 Logic Verification ................................................................................. 15 IP Design and Sourcing........................................................................ 17 Physical Design ................................................................................... 18 Performance Validation ........................................................................ 20 Tape-In & Tape-out activities ............................................................... 21 Post-Silicon Validation ......................................................................... 22 Multi Product Test Shuttle (MPTS) Service ........................................... 24 Current status of Indian Fabless Design ecosystem .......................................................................................................................25

VIII. Recommendation - Fabless Design.......................................... 26 IX.

References ............................................................................. 29

X.

Next Steps ....................................... Error! Bookmark not defined.

FABLESS DESIGN

1

Glossary

IoT SOC IC CPU FPGA CAD EDA HDL IP BOM

FABLESS DESIGN

Internet of Things System on Chip Integrated Circuit Central Processing Unit Field Programmable Gate Array Computer Aided Design Electronic Design Automation High Level Descriptive Language Intellectual Property Bill of Material

2

Message from the Chairman of the Committee at NITI Aayog DRAFT for Prof Desai’s edits and inputs India is the global hub chosen by large MNCs for their R&D. This is mainly because of the talent available in the country. How do we scale this to the local ecosystem and talent available in the country? A round table was held in NITI Aayog on April 6th, 2016, and on the instruction of Dr. V.K. Saraswat, Member, NITI Aayog, it was decided to form a working group to develop a white paper for creating a 'Design revolution' in India, for Fabless Chip Design. A culture for VLSI design has to be created as per global standards and create entrepreneurship as per the Prime Minister’s directions. The Committee had active participation from MeitY, IESA, DIPP, Intel, Qualcomm, NID and members from various other organization. The first Committee meeting was held on June 13th 2016at NITI Aayog, where we drew out the main objectives 

Promote a Fabless Chip Design revolution in India to realize the objectives of Make in India.



Develop a detailed white paper covering all the aspects for implementation of a Fabless Semiconductor Chip Design ecosystem in India with recommendations to make it viable and sustainable. The paper must developed to the level of actually establishing the details and requirements of a design center that would do high quality chip design. Focus on designing for local and global requirements and inculcate world class skills in local companies. The focus must be on commercially viable designs. It was decided to focus on 4-5 sunrise areas. The objective is to keep it evolutionary and flexible in line with global demand. Include future requirements/ designs like 5G chips, sensors, etc. The recommendation should be for 4 or 5 Fabless Chip Design centers and create an ecosystem and not just a singularity. Centers should be autonomous and flexible. All resources and benefits should go from Govt. direct to Centre. A governing Council should be established to monitor progress of the Centers. The Centers should meet 3 to 4 times a year with the Governing Council and share the work they are doing. The importance of skilling, education and training. This has to go hand in hand. Each center – Hub, should have at least 3 spokes. The funds given to the Center should be shared with the spokes, for example, a 70 - 30 model -- 70% of the funds with the Center and 30% to be shared by the 3 spokes. By having 5 centers and 15 spokes, 20 institutions will evolve with fabless chip design expertise and this is the only way we will be able to start a Fabless Chip Design revolution.







FABLESS DESIGN

3

We had four well attended Committee meetings during the year to finalize the above requirements and we are pleased to present you with the paper. We hope that this paper will be adopted for a successful Design Revolution in India. This will lead to a vibrant design ecosystem for a high value design model for high value manufacturing. As mentioned in the report, India’s core strength is in design and this report emphasizes the urgent need to develop a huge fabless chip design ecosystem.

Prof. U B Desai Director IIT Hyderabad Chairman NITI Aayog Working group for Design revolution for Fabless Chip design.

FABLESS DESIGN

4

Introduction

Electronics today is at the heart of ‘everything’ from medical equipment, educational devices, to Internet of Things and much more.. With the demand for electronic hardware expected to rise rapidly to US$400 billion by 2020, India has the potential to become a global electronic manufacturing hub. Design in India is an essential component of Make in India. There is an acute need for a semiconductor design revolution in the country – what we refer to in this report at Fabless Chip Design. This will lead to a high value design led model for high value manufacturing The semiconductor chip is the brain of all electronics. VLSI (very large-scale integration) is the current level of computer microchip miniaturization and refers to microchips containing billions of transistors. India has high potential for designing semiconductor chips, this white paper looks at the current state of industry and provides recommendations to enable country to become a leader in fabless design.

FABLESS DESIGN

5

Semiconductor Fabless Design - The Need for Transformation “Design” in India- An integral part of “Make in India” The government is looking to boost development through investment in infrastructure, transport, smart cities, manufacturing and IT to boost growth in India. The prime Ministers mission of Make in India and Digital India are major initiatives towards these objective. If these programs are executed to their full potential, they will bring about unprecedented growth in new businesses and help increase opportunities in electronics and semiconductor design. Make in India, which implicitly includes Design in India provides an ideal opportunity for the country to grow its design capabilities. Make in India mission will be a platform to bring ‘design’ and ‘innovation’ into the forefront of the offerings that India has for the world. This strategy plays perfectly to India’s strengths as a country with a uniquely skilled workforce and an education system that produces high quality math and science graduates that are sought after the world over. The momentum here is already building but in order to have design contribute to these ambitious goals, we need to understand the dynamics of the industry and its market forces. Accelerating Innovation Innovation is driven by research and development which is the backbone of a globally competitive, knowledge-driven economy. R&D investment helps develop new innovations in the form of products and services that drive growth, create jobs, and improve the national welfare. The chart below shows the relationship between national scores in global competitiveness and innovation. The mapping of these two characteristics provides another indication of why indigenous design capabilities are not developing to their potential.

FABLESS DESIGN

6

India lags far behind in terms of innovation and competitiveness to all other countries mentioned

Global Innovation Index

65 60

Singapore

Ireland South Korea Israel

55 50

China

45 40

Malaysia

Thailand

Mexico

35 India

30 25 4

4.2

4.4

4.6

4.8

5

5.2

5.4

5.6

5.8

Global Competitive Index

Source: Global Competitiveness Report 2015-2016, World Economic Forum, The Global Innovation Index 2015, Cornell University, INSEAD, et. al.

The countries that India has been compared with are those that have heavily invested in ESDM (Electronic System Design and Manufacturing). These are countries that are involved in the manufacture of critical electronic components such as semiconductors but have since moved up the value chain into areas that include the design of those products. To explain this further, Appendix A provides a comparative view of the tax and incentives available in several countries whereas Appendix B includes case studies of how the countries listed were able to successfully develop and incentivize their high tech sectors. We need to ensure that India remains a very competitive place for next generation product design and development and additionally remains viable and sustainable for the ecosystem thus developed Besides the tax and incentives available, one of the key success factor are the ease by which companies are able to import and export unfinished, Engineering and R&D samples of hardware components from various overseas locations to perform its research. Further testing the design, for which products/prototypes may have to go back to overseas countries. In this paper we have recommended a MOSIS like program in the country. Special schemes and recognition of the Fabless Chip Design Ecosystem partners is required to facilitate this.

FABLESS DESIGN

7

Other measures, based on new technologies that enable better process design, can also improve the productivity of the manufacturing industry. Rapid prototyping equipment can help speed the flow of designs from “file to factory,” and collaborative communications tools can allow teams in different countries to co-design and peer produce products and assemblies. Co-design and peer production refer to the idea of distributing these activities across a distributed network of specialists who combine their expertise to create, develop and refine products more quickly and efficiently. Critically, all these tools and capabilities can be shared across broadband networks so that they are accessible to both SMEs and large corporations. Of the many challenges we see in this field there is one common theme that sets apart successful companies and business environments, and that is the ability to embed a culture of innovation into the way of doing business. This culture thrives in niche businesses in India. One area where it is alive and flourishing is in software and services and here we have yet another potential lever to grow manufacturing. Several Indian software companies are already providing critical services to the major hardware companies- suggesting that a transition is underway from the low end outsourcing model to creating more value. The government has a role to play in encouraging Indian software companies to invest in research and development and to develop a culture of innovation that will allow them to add value to and complement hardware systems development. The software and services sector has the potential to become the backbone of manufacturing but some changes will be required as we list out in the IP “Recommendations” section. Software and hardware are no longer two different segments independent of each other- in fact they complement each other. Worldwide, hardware companies are partnering with companies providing security services so that security can be incorporated in the hardware, and this is by no means limited to the ICT industry. From cars to refrigerators to electric grids, everything around us is getting ‘smart’ and ‘connected’ because cutting edge software modules are integrated into hardware form factors and networks connect them using telecommunications technology. By the same token, software giants like Google, Facebook, Amazon are investing in hard – often termed as IoT solutions. India’s core strength is in design and this report emphasizes the urgent need to develop a huge fabless chip design ecosystem. FABLESS DESIGN

8

Semiconductor Industry - Value Chain and Current state

IC/SOC design - Design Flow and requirement Shrinking IC process technology has enabled smaller transistors which in turn has led to higher functional integration and ability to design and manufacture large and complex SOCs. At the same time, this has led to several challenges to the IC/SOC design teams ([1], [2]). These are:      

Designs with multiple design styles (Analog, Mixed-Signal, Standard Cell Based and Full Custom) Functionality coded in multiple hardware description languages (HDL) (Verilog, VHDL, SystemVerilog etc.) Functionality verified using diverse set of hardware verification languages (HVL) like C/C++, Specman ‘e’, SystemVerilog etc. Increased logic and physical verification time Complex process design rules Individual blocks design using proprietary or vendor specific flows leading to full chip integration challenges

Thus having a robust and well defined design flow is critical for designing a complex state of the art SOC. This section explains the various components that are part of a complex SOC design flow.

FABLESS DESIGN

9

Design- The essential element for a thriving Fabless Ecosystem Infrastructure

In order to design and verify complex SOC a robust design infrastructure is required. This infrastructure aids the designer to develop and verify IP blocks, assemble and validate them at the full chip level. The infrastructure needs can be classified under two broad categories  

Hardware Infrastructure Software Licenses

Hardware Infrastructure Hardware infrastructure comprises of the following    

Compute elements (like servers) Storage elements (like hard disk drives) Hardware accelerators (like emulation boxes) Rapid Prototyping Systems (like FPGA boards)

Almost all the SOCs designed today use computer aided design (CAD) methodology. This implies that design and verification is done using a set of tools. The tools that are used to design a SOC are described in a future section. Making sure that the design implemented actually meets the specification requires exhaustive verification to be done in the logic and physical domains. Traditionally logic verification involves simulating a RTL or circuit model using a set of test vectors. Depending to the size of the SOC, these models could become quite big and may require special servers with the right memory foot print to fit them. Current test sequences used to verify designs can be quite complex and lengthy. To be able run a sufficient number of such test sequences in a reasonable time will require computing machines which run at high speed. Physical design flows which verify that the layout are drawn as per the process rules are also highly compute intensive. Present day designs use a compute farm which typically comprise of several thousands of CPUs running at very high speeds and having as high as 64GB local memory. These compute farms could

FABLESS DESIGN

10

be local or remote to run logic and physical verification tests. Hence, having a robust compute infrastructure is very critical in the complex SOC design process. It is very common for any verification or design process to have failures due to bugs in the design, the verification test bench or the verification flow. To be able to debug these failures, designers use a variety of techniques. Most commonly used techniques are detailed log files and waveform database. Depending on the size and the point of failure, these log files and waveform databases could be very huge in size. These files need to be stored for further debug which necessities the need for storage space. At any given point of time there are multiple versions and type of designs being debugged and multiple test failures being debugged. The size of the SOC which in turn determines the size of the model also needs to be stored. It is very common for RTL models to be of terabytes (TB) size and regression debug log files to be in several gigabytes (GB) size. Hence, availability and management of storage is very critical for the design process. Given the increasing size of SOCs over generations, simulation has been found to be very time consuming as well as inadequate for tape-in decision making. Hardware accelerators like big emulation boxes which could comprise of FPGAs or traditional CPUs are being commonly deployed for functional verification. These emulation boxes are very expensive as compared to traditional logic simulators. To overcome the cost barriers these boxes are time multiplexed and shared across multiple projects. Housing these boxes and setting up the ability for multiple projects to share them is a critical infrastructural requirement. Once a SOC is tape-in, it may take several months for it to be manufactured and packaged. If a basic defect (functional or physical) is discovered, the design team needs to go through another tape-in which is cost and time to market expensive. To avoid this, it is very common for the design teams to use rapid prototyping systems. RPS allows the design to be mapped onto a generic hardware like FPGA and run post silicon test content including operating systems and other applications before the tape-in. However, RPS requires appropriate infrastructure like choosing the right FPGA, sister components, designing and manufacturing the PCB and testing it with the appropriate software.

FABLESS DESIGN

11

Software Infrastructure Specialized CAD tools are deployed by SOC teams for design and verification. These include     

RTL Quality Checking (like linters, clock domain crossing etc) Functional Verification (like simulators, emulators, formal property verification) Functional Debug (Waveform viewers, Coverage analysis) Physical Design (Logic Synthesis, Timing Analysis, Place and Route) Physical Verification (formal equivalence verification, design rule checks, electrical rule checks, layout to schematic checks etc)

These CAD tools are developed by EDA vendors and are licensed by the SOC design teams. Identifying and procuring the right set of tools plays a key role in the SOC design team success. Each of these tools (and sometimes some features within a tool) are licensed separately. Determining adequate licensing for each of the tools is critical for design to complete on time. For e.g., if there are 100 computers and each could run 2 functional simulation jobs, then at least 200 simulation licenses need to be procured. Anything less will lend some of the hardware to be idle. At the same time buying more than 200 licenses would result in wasted money since only 200 jobs could be executed at any given point of time. For multi-site teams, these licenses need to be distributed and configured appropriately.

Tools, Flows and Methodology

Moore’s law has been driving the growth of silicon industry for multiple decades. All complex integrated circuits are being able to be manufactured on silicon with every generation till date, do follow Moore’s law. The availability of advanced silicon capabilities has led to the need for robust design flows which can exploited for adhereing to Moore’s law.. Not having robust design flows leads to productivity gap. For eg. chip modeling has moved from schematic entry in the 1980s to hardware description language (HDL like Verilog and VHDL) in the 1990s to architectural language modeling like SystemC/SpecC. FABLESS DESIGN

12

To take advantage of advanced silicon capabilities, a number of electronic design automation (EDA) companies provide tools to design and verify IP and SOCs. Following are the prominent list of vendors along with the tools that they provide for accomplishing a variety of design and verification tasks (list is not exhaustive) Need to insert the list of vendors Have tools available to solve point issues is a necessary but not sufficient to design complex SOCs. These tools needs to interact and work with each other to create an efficient design flow. An example virtual silicon prototype flow is depicted below [3]

Source: T. Moxon / EEDesign, 2.1.2002 [3]

FABLESS DESIGN

13

As seen from the above diagram, the design, verification and physical design (layout team) are involved in the SOC design cycle from the beginning. This flow allows faster physical design and verification feedback to design teams.

Architecture The role of system architecture team is to convert the customer requirements identified by the marketing team into functional specification that is understood by the design team. Architecture team breaks down the customer asks into different blocks (IPs) on a SOC or enhance the existing IPs with new features. The end result of an architecture team is a high level SOC block diagram depicting the various IP blocks, defining or enhancing interconnect between the various IPs and documenting the features within each of the IP blocks. A typical SOC block diagram is shown below [4].

A Typical SOC Architecture, Source: Hsiung

FABLESS DESIGN

14

Logic Design

Once an IP block is identified and its features are defined, the next step is to further partition these blocks into smaller blocks and implement the features in hardware. If the features are primarily going to be implemented using digital logic circuits, then the process is known as logic design. For modern complex designs, logic design is accomplished using hardware description language (HDL) like Verilog, SystemVerilog or VHDL. Using a HDL to capture the formal description of an electronic circuit accomplishes two purposes. First, it allows automated analysis and simulation and second, synthesis of HDL to a low level netlist.

Logic Verification

With designers adding more functionality into the IPs and more IPs getting integrated into SOC, verifying the functionality is fast become one of the critical challenges in the SOC design process. Functional verification ensures that the design performs the tasks as intended by the overall system architecture. With increasing SOC complexity, functional verification is done at the Register Transfer Logic (RTL) level than at the netlist (or gate) level. Following are some of the approaches to functional verification    

Logic Simulation Analog and Mixed Signal (AMS) simulation Formal Verification Emulation

In the logic simulation approach, the device under test is placed under a verification testbench environment and then applying test vectors to the inputs of the DUT and verifying the outputs against a pre-determined pattern. The testbench and test vectors are written using a HDL like System Verilog or in a traditional programming like C/C++. Approaches to verifying blocks can be classified as

FABLESS DESIGN

15

  

Black Box Approach: DUT is verified without knowing the design details. This approach is suitable to verify pre-validated IP blocks at the SOC level. White Box Approach: DUT is verified with detailed knowledge of the design. This approach is suitable to verify new IP blocks. Gray Box Approach: DUT is verified with some knowledge of the design. It is a midpoint approach and is suitable for modified IP blocks.

The test vectors that are written to verify the DUT can be either directed or constrained random. Directed testing involves targeting the test vectors towards a particular feature or functionality. In constrained random testing, legal combination of test vectors are fed into the design. Constrained random testing needs to be combined with some form of verification coverage methodology to ensure that the needed design space is covered. While simulation is the most common verification method used by IP and SOC designers, it suffers from speed limitations. Simulation also cannot exhaustive cover all possible cases. Modern SOCs have both digital and analog blocks on the same chip. For example the IO controller and the physical layer are both integrated on the same SOC. The IO controller primarily comprises of digital logic while the physical layer comprises of predominantly analog logic. To ensure the flow validation between the digital and the analog blocks, AMS simulation is carried out. In this methodology, the digital logic is represented as RTL using HDL while the analog blocks are represented as netlist at the transistor level. AMS simulation is very slow and hard to debug.One of the biggest limitation of simulation is the inability to cover the entire design state space. The verification is as good as the test vectors that are applied. If these test vectors miss any legal cases, there could be bugs left in the design. This limitation is partially overcome by deploying constrained random verification but even that approach is not exhaustive. Formal property verification (FPV) tries to overcome this limitation. In formal verification, a property capturing the legal or illegal state of a design is written by the designer. Legal input sequences are modelled as input constraints. The formal verification tool uses exhaustive mathematical approach to either prove that the property cannot be violated or provide a counter example to demonstrate the path to violate the property. FPV traditionally has suffered from state space explosion. But, with advent of new algorithms and availability of compute with large memory foot print FPV is gaining acceptance with a lot of design teams.

FABLESS DESIGN

16

Hardware emulation is the process of emulating one or more pieces of hardware with another piece of hardware. Emulation addresses the performance shortcoming of simulation. At 10,000 to 100,000 times the speed of simulation, emulation makes it possible to test application software while still providing a comprehensive hardware debug environment. However, emulation has the following short comings 

Emulation hardware is very expensive



Limited observability and controllability

In spite of the above limitations, emulation is being very widely employed to validate the SOC.

IP Design and Sourcing

An IP block comprises of a specific functionality, for eg. USB controller or PCI express Physical layer. This IP block can be designed in house or can be sourced from an external vendor. External vendors including independent design companies and EDA vendors provide IPs for standard functionality blocks like memory controller, IO interfaces like UART, SPI, PCIe, USB etc. Many vendors also provide analog IP blocks like PLLs, Register files, SRAMs, Physical layer IPs etc. that are specifically targeted to a specific foundry. CPU cores are yet another IPs that are available from external vendors as soft or hard IPs. SOC teams need to identify the IP that are required for their product. Once the IP blocks are identified, they need to decide whether to make or buy the IP. There are various parameter that needs to be considered in the make vs. buy decision. Following are some of them.     

Does the IP contain any company specific proprietary information? Does the IP provide any competitive edge to the company? Is the IP a standard functionality and available in the market? Time to develop the IP vs. the cost to acquire it Whether IP will be sourced as a soft IP (RTL code) or hard IP (layout)

FABLESS DESIGN

17

Once the decision is made, the IP needs to be procured from the vendor. A list of IP providers is available as a catalog in various web sites. One such site is identified below: http://www.design-reuse.com/sip/provider.php

Physical Design Physical design refers to all synthesis steps that convert a circuit representation (gates, transistors) into a geometric representation (polygons and theirs shapes). For a complex SOC, physical design comprises of the following steps 

Floor planning



Partitioning



Power planning



Placement



Clock Tree Synthesis (CTS)



Timing Analysis



Design for Manufacturing (DFM)



Physical Verification

Floor planning is a very essential step for hierarchical, building-block design methodology. It helps estimate the block shape and size, chip size, delay and routing congestion. To cope with the increasing design complexity, IP blocks are widely reused for large-scale designs. Therefore, efficient and effective design methodology and tools capable of placing and optimizing large-scale blocks are essential for modern chip designs [5]. There are multiple EDA tools available that can do SOC floor planning. A suitable compromise needs to be arrived at in the SOC floor planning between the CPU core, SRAM/Cache, IOs and peripherals like DDR, MIPI, USB, HDMI, PCI express etc. Partitioning defines the use of local and global interconnect and can have significant impact on the SOC performance. Hence, partitioning plays a very key role in physical design. Unless properly planned. Power integrity issues like IR drop, ground bounce and electro-migration can lead to chip failures. Power planning includes FABLESS DESIGN

18

power pads that supply power to the chip, power rings that carry power around the periphery of the die and power rails & straps that supply power across the die. Placement is the process of assigning the circuit components into a chip region. It can be considered as a restricted floor planning problem for hard blocks with some dimension similarity. Placement in addition to defining the shape of the block also fixes the block pin position. The traditional placement problem seeks to minimize wire length under the constraint that cells/macros do not overlap with each other. Three types of most popular techniques are used in the state-of-the-art placers: (1) the partitioning based approach, (2) the simulated annealing based approach, and (3) the analytical approach. The process to get the clock distributed to all the sequentials in the design known as clock tree synthesis (CTS). The goal of CTS is to minimize clock skew and latency. CTS has two steps; clock tree building and clock tree balancing. Some of the common structures deployed for CTS are H-Tree, X-Tree, multi-level clock tree, Fish bone etc. Negative effects of CTS are increase in congestion, cross talk noise, cross talk delays etc. Static Timing Analysis (STA) is one of the techniques to verify design in terms of timing. This kind of analysis does not depend on any data or logic inputs, applied at the input pins. The input to an STA tool is the routed netlist, clock definitions (or clock frequency) and external environment definitions. The STA will validate whether the design could operate at the rated clock frequency, without any timing violations. Some of the basic timing violations are setup violation and hold violation. Design for manufacturing (DFM) is a systems approach to improving the competitiveness of a manufacturing enterprise by developing products that are easier, faster, and less expensive to make, while maintaining required standards of functionality, quality, and marketability. With sub-micron process technologies, yield drop out has been increasing. Yield drop outs happen due to the following reasons 

Random defects: Due to form of impurities in the silicon itself, or the introduction of a dust particle that lands on the wafer during processing leading to opens and shorts.

FABLESS DESIGN

19



Systematic defects: Related to process technology due to limitation of lithography process which increased the variation in desired and printed patterns.



Parametric defects: Due to improper modeling of interconnects parasitic.

DFM consist a set of different methodologies trying to enforce some soft (recommended/Mandatory) design rules regarding the shapes and polygons of the physical layout which improve the yield. Some of the DFM guidelines are: 

Filler cell insertion and shielding



Via optimization



Wire spreading



Power/ground connected fill



Dummy metal/via/FEOL



Hotspot detection

Physical verification involves making sure that the layout matches the schematic and the process design rules are met. There are a number of industry standard tools available to carry out the physical verification tasks. Physical verification is very critical to make sure that the process design rules are not violated as well as the layout matches the circuit. Performance Validation To be a competitive product in the market, every SOC has to meet the specified performance. Performance is very critical in certain segments like servers. For performance sensitive market segments, products beating the specified performance can fetch higher selling price. For many standard interfaces, bandwidth is specified by the specification and SOCs are expected to comply to it. There are different performance parameters of interest within an SOC. For eg. for the CPU core, instructions per cycle (IPC) is a typical measure of performance while for the interconnect or memory interface, latency and bandwidth are crucial from a performance standpoint. Typically there are 3 metrics used to measure performance; instruction per cycle (IPC), latency and bandwidth. IPC is defined as the average number of instructions executed by the CPU core in a clock cycle. Latency is defined as the FABLESS DESIGN

20

delay (usually measured by the number of clock cycles) from the input to the output. Bandwidth is defined as the amount of data that can be transmitted in a specified amount of time. Superior SOCs are expected to have high bandwidth and low latencies. SOC performance validation is done at multiple levels of abstraction. In the early stages where the SOC definition is in progress, performance models are developed using specialized language like Aspen. Once the RTL model is available, the RTL verification infrastructure is reused to measure IPC, bandwidth and latency. Special test scenarios are created which stress the IP or SOC and performance measurements are done under the stress conditions. As the RTL matures, performance validation is done using emulation or on FPGRA prototype boards. This allows measuring performance parameters by running the actual work load software. Performance validation can yield true RTL bugs which are usually related to Q-sizes or insufficient credits, credit latencies or credit leakages. Tape-In & Tape-out activities Once the SOC lay out is assembled and final verification checks like DRC, ERC and LVS are run on the final database, the design database is converted to Graphics Database System (GDSII database). GDSII, is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork. It is a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form. The data can be used to reconstruct all or part of the artwork to be used in sharing layouts, transferring artwork between different tools, or creating photomasks [6]. This database is then electronically transferred to the photomask shop for further processing. Tapeout, also known as pattern generation or PG, is the final result of the design process for integrated circuits or printed circuit boards before they are sent for manufacture. The tape-out is specifically the point at which the artwork for the photomask of the circuit is sent to the fabrication facility [7]. The foundry performs additional checks on the GDSII database received from the design team, and make modifications to the mask design specific to the manufacturing process before actual tapeout. Optical proximity correction is an example of such an advanced mask modification; it corrects for the wave-like

FABLESS DESIGN

21

behavior of light when etching the nano scale features of the most modern integrated circuits. Tape-in/out are the important milestone for SOC designers since it indicates the culmination of the design activities and handing over the baton to the mask shop and foundry. However, tape-in is usually not the end of any design activity since a SOC could have multiple tape-ins to address any manufacturing or functional defects. Post-Silicon Validation Once the SOC is manufactured it needs to be validated to make sure it conforms to the specification. This is accomplished using post-silicon validation. Purpose of post-silicon validation is to make sure that the silicon meets all the aspects of specification. This includes   

Functional specification: Meets intended functionality Performance specification: Meets the bandwidth and latency requirements Quality specification: Work under the range of specified temperature, meets lifetime specification of the product etc.

Post-silicon validation can be classified under various categories      

System validation (functionality) Component validation (manufacturability) Performance validation Compatibility validation Electrical validation (physical layer requirements meeting specs like PCIe, DDR, USB etc) Quality and Reliability validation

System validation ensures that the SOC meets the functional requirement of the design. In this process, the SOC is plugged into a system validation board which has other components, debug hooks and associated software to carry out the validation activities. A number of applications and performance workloads are run to make sure the SOC meets the functional requirement. System validation makes use of the design for debug hooks put in the design for debug and root cause of failures.

FABLESS DESIGN

22

Component validation ensures that there are no manufacturing defects that have occurred during the fabrication process. Manufacturing defects could lead to opens or shorts or reliability issues due to electro migration. Special testers are deployed along with test programs to make sure that the parts can be manufactured without defects consistently. Component validation uses the design for test/manufacturing hooks put in the design for debug and root cause. Performance validation is carried out to ensure that the SOC meets the specified performance in terms of latency and bandwidth. Usually the system validation setup is reused along with specialized performance workloads to stress the SOC. Compatibility validation ensures that the SOC can work with existing software including OS. SOC is run with the various legacy software stacks as well as wide variety of OS like Windows, Linux, iOS etc. Electrical validation ensures that the physical layer of the IO conforms to the interface specification (like DDR, PCIe, USB, SATA etc.). It also ensures that data is being sent and received across the PCB channels without distortion or errors. Special electrical bench setup is usually used to conduct electrical validation. Quality and Reliability validation ensures that the part can be used without having defects over the life time of the product.

FABLESS DESIGN

23

Necessary requirements for creating a successful Fabless Chip Design ecosystem a. Access to cutting edge design tools and flows from EDA vendor such as Synopsys, Cadence, Mentor Graphics, etc. b. Access to process technology and Fab for production c. Access to process collaterals such as process file, Libraries, Runsets, foundational IP, Design Kit d. Access to Fabs/Foundry for Test Chips in early days e. Access to diverse IP ECO system f. Access to Architecture and Micro-Architecture g. Access to Software design and software h. Access to tester and testing facility i. Access to packaging and board design capability j. Access to working reference designs for HW/SW/FW k. Access to tested, validated & qualified catalog of components for building BOM l. Access to rapid prototyping facilities: Electronic, Physical, Product ID, etc m. Availability of mentors – design choices, product ideas, community n. Funding – for Test Chips, Test equipment, simulation o. Access to Market domestic as well as global Multi Product Test Shuttle (MPTS) Service While the design community in India has become mature in some key areas and continues to improve in other areas, the pace should be accelerated significantly. Engineers graduating from Indian engineering colleges take VLSI design courses, but they do not get any real world experience of designing a chip. Even after they join a company, it might take 2-3 years before they complete a design, tape out, get silicon and test it to get real world exposure of designing a product that gets deployed in production volume. This cycle can be reduced considerably by getting the engineers exposed to the real world fab experience as early as possible. One good example worth emulating in this aspect is the MOSIS program that is run by University of Southern California's Information Sciences Institute. Majority of MOSIS’ customers are students from universities all over the United States. MOSIS combines customers' orders onto shared multi-project FABLESS DESIGN

24

wafers (supported by multiple fabs) that speed production and reduce costs compared with underutilized single-project wafers. Running a similar program (under the aegis of MeitY or an IIT) would help improve the skillsets of the students tremendously and they would be able contribute from Day 1 after they graduate and join a fabless company. Startups in the Fabless space would be able to take advantage of this program as well to defray the costs of doing test chips before taking up full-fledged designs. This would also alleviate to a large extent the issue of not having a fab india as educational institutes/starts up would have access to multiple fabs through such a program.

Current status of Indian Fabless Design ecosystem Area Infrastructure Tools, Flow Methodology

Assistance Needed Startups will need help with business model

Mature

None Activity low in this area as companies are focused on services & not products. None None A few companies doing Design, but Startups will need help with upfront license cost on sourcing None

&

Architecture Logic Design Logic Verification IP Design & Sourcing Physical Design Performance Validation Tape In/Tape Out Post Silicon Validation

FABLESS DESIGN

Status Mature

Low Mature Mature Medium Mature Mature Mature Medium

None None Encourage companies in test/post silicon Infra

25

Recommendation - Fabless Design Area

Background

Recommendation

1 Market Opportunity/ Seed Funding

Total semi consumption in India is ~$4B and companies will be able to address a part of this only in specific segments. So, companies need to target both Indian and global market (~$400B) in target market segments to get to critical mass of volume shipments and be globally competitive.

Go beyond the current open ended funds (EDF etc.), identify 3-4 segments where there is enough local consumption (ex. STB, Phone, Energy meter, GNSS, IOT) and provide seed funding to get 3-4 companies to kick-start the eco-system.

2 Market Assurance

It is very difficult for startups in the Fabless Space to break into the market as established companies (especially from China) enjoy cost advantages either due to huge volumes from the domestic china market and/or support provided by the Chinese govt.

The govt needs to devise policy so that startups that take the risk of designing a product targeted at a big enough domestic market segments (ex. STB, Smart Card, GNSS/Navic, IOT etc.) do not get impacted due to competitors whose costs are lower due to non-mkt reasons.

3 People/Skills

Skill set in Academia is hampered by not having access to any fabs to do test chips.

FABLESS DESIGN

Fund a MOSIS like program to give first hand experience to students so that they can be productive from day one when they start working. Skill set in Industry has Startups/companies can use matured over the past decade this program as well. and there are enough engineers in India now proficient in all domains, albeit focused only on services.

26

4 EDA Tools

EDA Tool cost is one the Designate an IIT to be the biggest cost for a fabless single point of negotiator startup. with EDA tool companies and host the tools in cloud to be accessible for all startups. Govt to fund this upfront until production and companies will pay royalty to the EDA companies after they start production.

5 Emulation / This is also a significant Govt to fund this as a Rapid Proto upfront CAPEX cost for common Infra at one or two Infra fabless startups. locations that is accessible to any startup from anywhere in the country. 6 CPU IP

Indian govt has already funded open source royalty free RISC V implementations (IIT Chennai, CDAC). There are implementations by private companies as well. All these are completely Designed in India.

Govt to continue the development of this effort and also pay for porting of these cores to major fabs so that startups can readily use this for production.

7 Non-CPU IP

Startups have to negotiate Two points. with each IP company Designate an IIT to be separately and that does 1. the demand aggregator and optimize time or money. be the single point of negotiator with IP companies

2. Govt to fund commonly used IP (create an IP bank) that will reduce the cost of development. Similar to the EDA tool model, companies can start paying royalties after production starts. 8 OSAT OSAT (Outsourced Assembly Govt should have a focused (Assembly & & Test) companies handles effort to engage the major Test) assembly and testing for OSAT companies and bring FABLESS DESIGN

27

9 Packaging

FABLESS DESIGN

fabless companies across the world. Having these companies setup facilities in India will help fabless companies offer end-to-end services to customers and maintain parity with their global peers.

them to India. As Phone vendors are already doing system level assembly, this will be next level of value addition for the industry and does not need heavy lifting.

Similar status as above.

Similar recommendation as above. In fact, couple of clusters can be promoted for the combination of Assembly, test and packaging capabilities together.

28

References [1] “Streamlining the SoC Design Flow | EE Times,” EETimes. [Online]. Available: http://www.eetimes.com/document.asp?doc_id=1275820. [Accessed: 01Nov-2016]. [2] J. Ferguson, “The glue in a confident SoC flow,” in The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings, 2003, pp. 316–319. [3] T. Moxon, “Exploring new design flows | EE Times.” [Online]. Available: http://www.eetimes.com/document.asp?doc_id=1216162. [Accessed: 06Nov-2016]. [4] P.-A. Hsiung, “SoC Design Flow & Tools.” [Online]. Available: https://www.cs.ccu.edu.tw/~pahsiung/courses/soc/notes/soc01.pdf. [Accessed: 06-Nov-2016]. [5] Y.-W. Chang, T.-C. Chen, and H.-Y. Chen, “Physical Design for System-Ona-Chip,” in Essential Issues in SOC Design, Springer Netherlands, 2006, pp. 311–403. [6] “GDSII,” Wikipedia. 01-Nov-2016. [7] “Tape-out,” Wikipedia. 04-Aug-2016. [8] S. Mohammadi, “Hardware Software Codesign - Overview.”

FABLESS DESIGN

29

Appendix A

International Comparison of Tax Provisions and Incentives

Cash Grant Country Australia

China

No

No

Tax Holiday/ Exemption No

Tax Credit expenditure

on

R&D Other subsidies

power, A refundable tax credit Lower water and telecom equal to 45% of the eligible R&D expenditures (such as tariff Payroll cost, Training cost, certain Capital cost etc.) where the eligible entity has gross receipts of less than $20M and is not controlled by exempt entities, or ·

A 40% non-refundable tax credit for all other eligible entities. Exemption in Tax deduction equal to Reduction from Business 150% of the qualifying corporate tax rate Tax R&D expenses. · First 5M RMB Short term tax Exempt from holiday (3 corporate tax Years) for new software Carry forward of company set losses for 5 years. up Exemption from Import duty and VAT (Is this for all the Companies and forever?)

Malaysia

FABLESS DESIGN

Investment Allowance of 50% of eligible capital expenditure.

Tax holiday of No. 5 years for the Pioneer status companies

Additional 200% super deduction on non-capital expenditures. 30

Netherlands No

Israel

Tax holiday is Payroll tax credit from 35% only for the to 50% on pay roll expenses company operating under Free Trade Zone

Reduction in 5% corporate tax rate for the Innovation Box scheme

R&D expenses incurred shall generally be deducted over two tax years. The deductible expenses shall allowed to a participant in R&D costs of another developer generally may not exceed 40% of the taxable income of the investor in the year which expenses were incurred.

Trade and labor tax exemption.

Yes. Based on Tax holiday is the quantum only for the of investment company operating under Free Trade Zone Tax loss generated from R&D deductions can be carried forward indefinitely

Ireland

Yes

Mexico

Yes

FABLESS DESIGN

Excess credits may be refunded or carried forward indefinitely

Additional deduction in the profits for the small scale investment

Lower tax rates based on the zone or area. It is ranging from 7% to 12.5% against the corporate tax of 25%.

Various Government Grants /incentives for establishing or expanding R&D activities in Ireland e.g., Capital, employment, training, feasibility, pilot projects, etc.

For accounting periods commencing from 1st January 2012, companies, which are in receipt of an R&D tax credit will now in certain instances have the option to reward key employees Tax holiday is Yes: local capital, Certain only for the employment, training, municipal taxes are company (stamp feasibility, pilot exempt operating duty, license fee projects under Free etc.) Trade Zone

31

Appendix B: Case Study

Singapore Case Study: High number of STEM (Science, Technology, Engineering and Management) graduates attract R&D investments in Singapore1

Since independence, Singapore has constantly adapted its investment strategy to ensure global competitiveness and continued prosperity. For instance, the country moved from labour and skill intensive industries in the early 60s until the end of 70s towards its next wave of growth that focused on capital and technology intensive fields in the 80s and 90s. More recently, the country has pivoted towards a knowledge and digital innovation based economy which started in the early 2000s and still continues today. Part of Singapore’s success story is due to a series of governmental direct incentives which have maintained focus on building an innovation economy. Some of these incentives included the early 90s National Technology Plan followed by the National Science and Technology Plan. The current plan; research, innovation and enterprise plan, started to be effective in 2011 and an S$16.1 billion fund was allocated to the development of a knowledge/innovation economy. More recently, Government has made bold decisions to ensure that the country remains globally competitive. An example of this is manufacturing, which is one of Singapore’s largest sectors, where the Government is investing in the next wave of technology development to remain at the forefront of digital innovation. The ‘Future of Manufacturing’ is a specific national strategy applying an innovative focus to this sector. In 2013, the Singapore Government announced an investment of $500m over five years to boost the country’s skills in advanced manufacturing with key focus on 3D printing and robotics. Education is also a priority for the country in building important STEM skills to fuel future digital innovation. In 2012, more than half (52%) of higher education students graduated from STEM related courses. Globally at high school level, Singapore ranks second in

FABLESS DESIGN

32

Mathematics

and

third

in

Science

related

fields.

The rich supply of highly educated scientists contributes to placing Singapore at the top of the list of the most attractive business environments and scientific research hubs in the world and attract significant R&D investment from global organisations.

Israel Case Study: Israel Yozma ProgramError! Bookmark not defined. During the 1990s, Israel was facing a challenge to develop new enterprises, especially in the country’s high-tech sector. The Government of Israel addressed the difficulty in raising funds for projects or companies at their infancy stages through the Yozma and Technological Incubators (TI) programs. As a part of the Yozma program, the Government established wholly owned Yozma Venture Capital Company, with a total capital of US$100 million, in 1993. The aim of the company was to enter partnerships with VC companies and investors from the private sector to invest in Start-up high-tech companies. Government participation helped to reduce risks for VC players. The Government also offered lucrative incentives to private investors to encourage them to enter this partnership by giving them the option to buy its shares under predetermined and favorable conditions. The program was hugely successful and led to the formation of nine VC companies with a total capital of US$200 million during three years of operation (1993–1995). These VC companies invested in 130 Start-up organizations. The Technological Incubators (TI) program was launched in 1990, and within three years of its operation, 28 incubator organizations were established throughout the country. In order to translate innovative ideas into commercial products, these incubators supported the early stages of technological entrepreneurship that were not ready for VC funding. The program offers R&D grants that provide 85% of approved R&D expenditure (up to US$300,000– US$500,000 for two years), with the remainder to be raised by the entrepreneurs. In return, the businesses are under an obligation to pay back the amounts in the form of royalty, but FABLESS DESIGN

33

only if they are commercially successful. Both these programs were setup and run under the guidance and support of the Office of Chief Scientist (OCS) of Ministry of Industry and Trade of Israel and have helped to develop Israel as a major hi-tech entrepreneurship center.

Taiwan Case Study: Hsinchu Science Industrial Park (Taiwan) Hsinchu Science Industrial Park (HSIP) was the first government planned industrial park in Taiwan focused on production of high-technology goods. Modelled on the Stanford Industrial Park in Palo Alto, California and nicknamed as Taiwan’s “Silicon Valley”, the park was established in 1980 to stimulate indigenous technological advancement and reduce dependence on foreign technology suppliers. The government convinced expats working in the US to come back and build companies in Taiwan just as had been done in the Silicon Valley. The HSIP has since then become a major base for the development of high-tech electronics industry in Taiwan. Incentives offered to the companies A series of special investment incentives was launched to ensure successful development of HSIP including:        

Five-year tax holiday A maximum income tax rate of 22% Duty-free imports of machinery, equipment, raw material and semi-finished products Venture capital from the state Low interest loans Reduced land rent No limits on foreign equity Capitalization of investors’ patents and know-how as equity shares

These incentives contributed around 26% of an individual investor's outlay. In addition to these incentives, the government also directly entered into industrial production, establishing joint venture companies with private capital. As a result of this major boost, Taiwan's electronics companies were able to promote their own brand names and conduct their own R&D, while maintaining strong strategic alliances with foreign corporations. The HSIP houses many Taiwanese heavyweights such as Taiwan Semiconductor Manufacturing Company (TSMC) and United Microelectronics Corp. (UMC) — the world's two largest contract chip-makers. The industries run in HSIP consist of:  

Integrated circuits (IC) Computers and peripherals

FABLESS DESIGN

34

   

Telecommunications Optoelectronics Precision machinery and materials Bio-technology

These industry groups form a self-sufficient, closely integrated value chain — from R&D to mass production. Among these, the IC or semiconductor industry accounts for more than 50% of the park’s total revenue. These IC companies focus on producing Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) chips and on the development of foundry services for application-specific electronic modules and systems-in-package. Firms involved in related sectors such as materials, design, testing and packaging provide support for IC manufacturers, forming a complete upstream and downstream production system. Location advantage The park was set-up close to the primary public R&D facility in Taiwan – the Industrial Technology Research Institute (ITRI) – as well as the campuses of the two leading technology-focused universities, National Chiaotung University and National Tsinghua University. This was a major positive for the companies as they could leverage R&D facilities and innovations emanating from ITRI as well as were assured of supplies of skilled professional staff from these universities. In addition to these, the government also established a number of national labs at the Hsinchu Science Park including National Center for High-performance Computing, National Space Organization, National Chip Implementation Center, National Nano Device Laboratories, Instrument Technology Research Center and National Synchrotron Radiation Research Center. These research Centers and labs cooperate closely with industries inside the park in technology innovation and talent cultivation. Evolution of the ecosystem In the first decade of its existence, IT and PC assembly firms were the primary occupants of the park. While these companies enjoyed advantages of a shared labor pool, shared utilities and shared infrastructure, they were lacking opportunities in terms of economies of scope through inter-dependence. But in the 1990s, Taiwan government took active steps to promote the creation of a semiconductor industry (including large fabricators plus upstream IC design firms and suppliers) in Hsinchu. Also during the second decade, a related industry of flat panel display fabrication came up in Hsinchu. Following these, the solar photovoltaic industry emerged as a ‘third pillar’ of Taiwan’s high-tech industrialization efforts in 2000s. The success of these industries is primarily attributed to their clustering in Hsinchu, closeness to ITRI and to the universities. Development of other science parks FABLESS DESIGN

35

Following the success of the first park in Hsinchu, the government established the Southern Taiwan Science Park, consisting of the Tainan Science Park and the Kaohsiung Science Park in 1996. In addition to companies, several research institutes and universities have set up branches within the park. The Central Taiwan Science Park was established more recently in 2003. The companies in these parks focus on ICs, biotechnology, food and health sciences, TFT-LCD flat panel displays and optoelectronics.

Korea Case Study: Korean design excellence1 There has been a design boom in Korea since the beginning of the 1990s. The term "design" has become one of the most frequently used words in daily life, as a result of the rapid industrialization during the last couple of decades. The mass media, including TV, newspapers, and magazines, have increasingly featured design issues. These television programs were very successful and helped to convince the government and the management of Korean corporations of the need to create a national design agenda that would promote the establishment of Korea as a world class design nation. Accordingly, design has become a matter of discussion even in everyday life. Design is regarded as one of the most important criteria for buying products in Korea. According to a survey in Korea brand image (44.7%) and design (29.1%) were ranked the most important factors in the selection of consumer electronic goods. Interestingly, price, which used to be the most important criteria, ranked third with (2.3%). The survey also revealed that design (43.2%) was the most sensitive selecting criteria for teenagers, brand image (36.1%) ranked second, and price (21.7%) was third in that age category. Although public awareness of the importance of design has increased rapidly, the standard of Korean design has been relatively low compared to that of advanced nations. Due to a strong preference for Original Equipment Manufacturer (OEM) products, many Korean companies did not pay much attention to the development of original designs until the end of the 1980s. Their primary interest was to manufacture products with price competitiveness in conjunction with the lower production costs, based mainly on low wages. They relied heavily on the modification and/or imitation of well-designed foreign products, rather than developing their own original ones. However, they were able to maintain their competitiveness by that practice both at home and abroad for many years. The situation significantly changed at the beginning of 1990s due to the inauguration of World Trade Organization (WTO). Korean manufacturers now are faced with the problem of developing original designs in order to meet the changing market situation caused by the socalled "Design Round" (DR). It is not easy to copy or imitate someone else's designs with the growing awareness of design protection as a part of Intellectual Property. Korean manufacturers had to develop their own designs to compete with rivals, even in the domestic

FABLESS DESIGN

36

market. For these reasons, they realized the immediate need for cultivating world class design ability in order to expand their sphere of influence in the global market. Full-scale government support for design started at the beginning of 1990s when Korean products started to lose their price competitiveness. As the importance of design for enhancing competitiveness in both price and non-price factors was increasingly recognized, design promotion became a cabinet-level issue. In this environment, the government's Committee for Globalization Policy (CGP) has planned the development of a national design agenda. The committee, which is co-chaired by the Prime Minister of Korea, consists of more than 20 members from various fields, and is supported officially by the Coordination Bureau, Office of the Prime Minister. At the beginning of March 1996 the committee established a task force to prepare globalization strategies for the Korean design industry. The task force comprised eight regular members and several advisors from various design disciplines including visual communication design, industrial design, and others. The regular participants included two members from the Committee for Globalization Policy, four government officials from the Prime Minister’s Office and others, and two design experts. The main responsibility of the task force was preparation of a comprehensive blueprint for promoting design in Korea, as a result of the in-depth studies which had been completed. The results of the research were prepared by the middle of June 1996, and screened for feasibility at the regular monthly meeting of the Committee for Globalization Policy. The final version of the paper was reported to the President of Korea for approval at the beginning of July 1997. Eventually, a strategic scenario was prepared for transforming Korea into a world class design nation by the year 2005, by enhancing national competitiveness through the cultivation of the design industry. Developing a National Design Agenda For developing countries such as Korea, a close rapport between government and the civilian sector can be the most important factor for success of design promotion. For example, the government can initiate design promotion procedures at the start of industrialization, when the need for full-scale design investment is relatively less. A government-funded design organization can be established to play a central role in preparation of the pre-conditions for design promotion, including infrastructure. When design promotion accelerates as time goes on, the role of civilian design sector expands, while the governmental role decreases. The basic concept of government-pull and civilian-push model has provided philosophical basis for preparing the strategic scenario for transforming Korea into a world class design nation by the year 2005. The strategic scenario comprised of two steps: Step 1, preparing basic conditions for globalizing the design industry by year 2000; and Step 2, cultivating world class design abilities through promoting design industry by year 2005. FABLESS DESIGN

37

The scenario includes "declaring the 'Year of Design' in Korea," and holding a "World-Class Design Event" in the year 2001. Five major strategies for promoting the Korean design industry were formulated as follows: 1. Proclaiming a government desire to cultivate design industry as one of the national key industries in the 21st century; 2. Preparing an infrastructure for the design industry; 3. Reinforcing design abilities of both corporate in-house design groups as well as design consulting firms; 4. Reforming the design education system for cultivating well-educated designers, with various skills and experiences; 5. Consolidating design-related regulations for protecting original design and prohibiting design plagiarism. After deciding on the five strategies, intensive brainstorming sessions were organized in order to identify detailed strategic tasks needed to accomplish the objectives. Representatives of relevant government offices were invited to the brainstorming sessions, as well as to meetings for a feasibility study where ideas were carefully evaluated. As a result, ten strategic tasks were established: a) Organizing a "Committee for Design Korea" (Chairman: Minister of Trade, Industry and Energy) for implementing the national agenda for the design industry; b) Declaring a "Year of Design in Korea in 2001," and holding a world class design event; for example, the ICSID Congress and General Assembly; c) Establishing the Korea Institute of Industrial Design Promotion (KIDP) as the operational body for the above-mentioned committee; d) Constructing a Korea Design Center Complex Building for accommodating design-related organizations, including K1DP and others; e) Establishing a Basic Design Research Center for undertaking a variety of research on design and related issues, and a Design Information Center for operating a worldwide design information network through cyberspace; f) Encouraging the development of world-famous, well-designed products:  

Strengthening the Good Design Mark Award Scheme, in conjunction with tax incentives for investment in design and other indirect supports; Creating a new design award scheme for managers and designers;

g) Supporting the design consulting industry to nurture inter-national competitiveness; 

Establishing a tax incentive scheme for design services and others.

h) Setting up a new design education system for primary and secondary schools; FABLESS DESIGN

38



Providing fine art teachers involved in design education With re-education in design;

i) Upgrading the quality of higher design education;  

Encouraging the differentiation of curriculum and content of education at the university level; Operating the International Graduate School of Industrial Design in affiliation with the Korea Institute of industrial Design Promotion;

j) Enacting design-related regulations; 

Revising the existing Design Promotion Act to provide the legal basis for supporting the design industry; and -Formulating a Design Protection Act to prohibit design plagiarism

There have been remarkable changes in design promotion in Korea, mainly due to the strategic scenario prepared by the Committee for Globalization Policy. The new Design Promotion Act was formulated to take effect at the beginning of 1997. Several important structural changes in the Act will establish a strong basis for design promotion in Korea. For example, a new design promotion organization, the Korea Institute of Industrial Design Promotion (KIDP), was established at the beginning of January 1997 on the basis of the Act. Another remarkable change is that the civilian design association is now more active. The Korea Association of Industrial Designers (KAID) has initiated a variety of activities including the Korea Industrial Design Award scheme, which is to select the best designs from among the various Korean products every year. Furthermore, mutual collaboration between KIDP and KAID has grown recently and become more concrete. Indications for a strong rapport between the two organizations have appeared. The Republic of Korea is a classic example of the government-pull and civilian-push model in design promotion. The role of government has been most apparent in the first stage of design promotion in Korea since the end of 1950s. However, the role is less direct in relation to the ever-increasing role of design professional organizations. In conclusion, the rapport between the governmental and civilian sector will be the driving force for Korea to transform itself to a world class design nation early in the twenty-first century.

FABLESS DESIGN

39

Appendix C – Policy Considerations Developing SMEs and Start-ups In the course of our research for this whitepaper we spoke with many SMEs and evaluated their input in light of Intel India experiences internally and in working with our vendors. The input was consistent: 1. An insufficient supply of engineers with the requisite design skills. There is a need to increase the number of engineering graduates from the tier 1 institutions and a need to strengthen the curriculum in tier 2 and 3 institutions to produce higher quality graduates. Companies of all sizes are struggling to hire the talent they need to grow their design capabilities and India’s natural strength in software is regarded by many engineering graduates as providing wider career options. 2. The most lucrative design work is in “turnkey” projects where a complete project is outsourced to a professional design house which manages the project from start to finish. To obtain this type of work, design houses need to have a strong professional team and a track record of execution. For most companies, and particularly for SMEs, their work comes in the form of service support where they are outsourced certain elements of a larger design project to augment the work of an MNC design team or larger design house. Moving up the value chain requires scale (including having a sufficient number of qualified engineers) and trust in the quality of the ultimate work product. Even captive MNC design teams in India face this challenge as they also need to prove to their international headquarters that they offer better, cheaper and faster solutions than other sites within their corporate network. 3. In addition to these reasons, obtaining turnkey project work often requires the commissioner of the work to make full disclosure of proprietary information of considerable value. One of the most important considerations in evaluating this risk is the law and culture of the environment where work is being carried out. In India, we have sound contract law but no specific provisions protecting trade secrets. This can be a key differentiator that causes contracts to be lost and high value work sent to countries where there is stronger legal protection including a specific trade secret law with criminal provisions for the intentional theft of trade secrets. We discuss this more specifically in the ‘Recommendations’ section. 4. The “culture of innovation” mentioned earlier, also involves an understanding of techniques of break-through innovation and risk-taking. The leading academic institutions teach some of these techniques but most of it is learnt on the job and skills are developed over the time. The same also applies to engineers who are evaluating job options. Companies we spoke to noted that engineers were reluctant to move to an SME environment because larger companies offered greater job security. This was FABLESS DESIGN

40

particularly evident at the hiring window of four to five years’ experience, where candidates seem much more focussed on maintaining the quality of their resume. The perception here is that a stint in an SME or Start-up which ended prematurely could be career-limiting. This contrasts with many other countries where a Start-up experience is often seen as an indication of an aggressive mind-set and willingness to except responsibility beyond their years. 5. A common complaint we heard from SMEs was the burden of regulatory filings required for import and use of goods within the country. Particularly, the documentation process involved in ‘clearing’ goods from the ports can be very cumbersome, time consuming and is often perceived as a source of corruption. Movement of goods inside India is subject to regulations which confer wide discretionary powers on officials. With so many reforms already underway in India to expedite ease of doing business it is hoped that these issues will also be addressed and that Central and State Governments will work together to reduce the documentation and processes required to move goods. These reforms are addressed more specifically in the ‘Recommendations’ sections. 6. A more generic but nonetheless uniform complaint we heard was in relation to the complexity of the tax laws where some SMEs told us that the only safe strategy was to overpay because the consequences of coming up short were too time consuming to contemplate.

Resource Recommendations for Start-ups & SMEs (a) The Government’s new “Action Plan; Start-up India” 1 , program appears to be a promising platform to encourage entrepreneurship and to address some of the issues we have identified above. This could be tapped to establish fully equipped centres with VLSI design tools, prototype development facilities, testing facilities, compliance and certifications labs. (b) Student and graduate training could also be addressed through the same program with components specifically focussed on allowing engineers to develop skills to start a career in electronics design and to look for opportunities with SMEs in India. This could tap into several components of the plan including; “Building Innovation Centres at National Institutes” (Section 15), “Setting up 7 New Research Parks” (Section 16) and “Harnessing Private Sector Expertise for Incubator Setup” (Section 14). [Note: A good example of an innovation centre is the Hsinchu Science Industrial Park (HSIP) in Taiwan which is described in a case study in Exhibit B]. (c) More opportunities need to be created for engineers looking to work in VLSI design to get practical experience. Intel is willing to work with the relevant trade associations and the MNC community to develop a scheme to provide intern 1

http://www.thehindu.com/business/top-10-takeaways-from-modis-speech-at-startup-india-

launch/article8114318.ece FABLESS DESIGN

41

opportunities for engineers and to map out ways to link this scheme to those projects identified by the government as being critical to the country.

Improving the IP Environment: The Indian Intellectual Property (“IP”) regime has improved considerably in recent years but there are still many areas where additional reform and simplification would make a substantial difference. In the ‘simplification’ category, there is scope for leveraging some of the reforms outlined above in the ‘Start-up program’ which could be of benefit to companies of all sizes such as expediting patent prosecution. However, there are also more substantive reforms needed that will require more time and study to put in place. These issues (which we have listed below), would not only resolve lingering problem areas in Indian IP law, but would encourage local innovation and greatly enhance India’s ‘brand’ as a destination for high tech investment. Grant of Injunctions in Patent Infringement cases Background: There is a relentless effort among public and private companies to build high technology and complex products and these products may embody several patented inventions/technologies. Thus, such products are generally Patent Rigorous (PR) products. It is not uncommon to see such patent rigorous products embodying multiples of thousands of patents. For example, a mobile device such as a smartphone2 is estimated to embody 2.5 lakh patents and a laptop3 is estimated to embody more 250 standards and each standard may include thousands of patents. These high technology products are very different compared to other Non-Patent Intensive (NPI) products such as an electric bulb or a medical drug, which may embody one (or very few) patents. The existence of such NPI products may be substantially equated to practice of a patent (or very few patents). For example, Edison’s electric bulb embodied only few patents and predominantly a single patented (US 223898, Jan 1880) invention could be equated to Edison’s electric bulb. These products (PR and NPI) are very different from each other from the perspective of patents embodied in such products. However, the legal remedies available for patent infringement for these products (PR and NPI) are the same. A patent embodied in a PR type product contributes to a fraction of the total value of the PR product and a patent embodied in a NPI product contributes to a substantial value of the NPI product. An injunction granted in case of PR product, which 2

https://www.techdirt.com/blog/innovation/articles/20121017/10480520734/there-are-250000-active-patents-that-impact-smartphonesrepresenting-one-six-active-patents-today.shtml 3 http://www.standardslaw.org/How_Many_Standards.pdf FABLESS DESIGN

42

allegedly infringes one or few patents affects the total value of the PR product. Thus, applying the same legal principles to grant injunctions to PR and NPI products, which are alleged to infringe patents may result in highly undesirable effects on innovation and business. Issues related to grant of injunctions in a patent infringement suit are very important to India as we are moving up the innovation value chain and embarking on initiatives such as “Make in India”, “Design in India”, “Skill India” and “Start-up India”

Recommendation: Government should consider amending laws related to injunctions and include judicial discretion and “proportionality” in the injunction decisions, which may include the FRANDencumbered standard-essential patent context. Government should start a consultative process with large, medium, SMEs, private, public, Indian, and MNCs to develop these positions. Government should consider instituting research on these key areas and focus on passing legislative amendments to Indian law on injunctions while adjudicating patent infringement cases related to these PR products.

As key stake holders we will be happy to provide support by providing position papers and our learnings from different countries, which would help amend Indian laws in the above matter. We would be willing to support discussion forums such as roundtables to explain the need for amending corresponding laws. These discussion forums may include honorable members of the judiciary, enforcement agencies, legal fraternity, and academics.

Filing of annual Working Statements: Background: As per Section 83 of Indian Patents Act 1970, patents are not granted ‘merely to enable patentees to enjoy a monopoly on a patented article’, but ‘to secure that inventions are worked in India on a commercial scale and to the fullest extent that is reasonably practicable without undue delay”. The mandatory requirement to furnish details of working of Patents: Section 146(2) of the Patent’s Act, 1970 requires patentees and licensees to submit a statement of commercial working of invention (Form 27) to the Controller every year. Such statements can be published by the Controller General for public viewing. Failure to submit information on statement of working is punishable and attracts a hefty fine which may extend up to Rs.10 FABLESS DESIGN

43

lakh. Further according to Section 122, providing false information regarding working of an invention is considered as an offence and is punishable with imprisonment up to six months and a fine, or both. Details required in Form 27: The relevant information to be submitted by patentees and licensees in a Statement Regarding the Working of the Patented Invention, as per Form 27 are as follows: I.

Whether the patented invention has been worked or not worked; If not worked, the reasons for not working and the steps being taken for working of the invention.

If worked, the quantum and value (in rupees) of patented product; a) Manufactured in India b) Imported from other countries along with the details of each country; II. The licenses and sub-licenses granted during the year III. Whether the public requirement has been met, at a reasonable price either partly, adequately or to the fullest extent.

Filing of such Working Statements, annually, is hugely cumbersome on the patent holders as it requires analysis of each patent granted in India. The details sought in Form-27 are often impractical to provide. For example, in a PR type of product it is practically impossible to attribute a revenue value per patent.

Recommendation: Government should consider amending patent rules to drop this requirement of filing of annual working statements. It is very burdensome on the patent holder to carry out a deep analysis on each Indian patent every year and if ever a patent is litigated then some of these details sought in the working statements will have to be provided by the plaintiff. As such there is no value even to patent office from these working statements, which are collected annually.

FABLESS DESIGN

44

CRI Guidelines 2016. Background: The first set of Draft CRI Guidelines were released by the IPO on 28th June 2013 for consultation with stakeholders. The CRI Guidelines clarified that business methods, mathematical methods as well as algorithms are not patentable. After due consultation with the stakeholders a well-reasoned CRI guidelines was given into effect on 21st August2015. The CRI guidelines of 21st August2015 allowed patentability of software inventions, which run on general purpose hardware. However, the CRI guidelines of 21st August 2015 was put in abeyance in December 2015 citing a reason that all the stakeholders were not consulted. However, all stakeholders were given ample opportunity to present their views during the stakeholders meeting of 2013. Now, the IPO has given into effect a new CRI guidelines on 19th Feb 2016, which requires a software invention to run on a novel hardware for the combination to be patentable. Requirement to show a novel hardware for a software invention to be patentable goes beyond the requirements (of novelty, inventive step, and usefulness) under patent law. Also, the CRI Guidelines of 19th Feb 2016 contravenes the judicial precedent set by the Delhi High Court (DHC) on software patents in its interim decision in Ericsson vs. Intex.

Recommendation: The GOI (i.e., DIPP) should intervene and direct the Indian Patent Office (IPO) to (a) Drop the requirement of “novel hardware”; or (b) Direct the IPO to recall the CRI Guidelines of 19th Feb 2016.

Specialized IP courts: Background: There are no specialized IP courts in India today. IP is a specialized legal area, which generally involves application of legal principles to IP, for example, as in case of patents. Given the workload and breadth of the variety of matters heard by the judges, it is hard on the judges and the parties to, quickly, have a good grasp/understanding of the subject matter. Moreover, the number of IP cases is increasing and it is bound to increase as the number of applications seeking IP protection is increasing as well. Thus, there is a need for specialized IP courts in India.

FABLESS DESIGN

45

Recommendation: Government may consider (a) Setting up of IP courts in India and to begin with we must have them at least in Delhi, Bangalore, Mumbai, and Chennai; (b) Focus on IP as a topic for trainings in the judicial academies in India; and (c) Involve experts from the judiciary, industry, and academics to share their learnings and experiences at the judicial academies.

Grant of foreign filing permissions: Background: As per Section 39 of the Indian Patent Act, an Indian Resident shall not apply for a foreign patent for the grant of patent without obtaining a written Foreign Filing License FFL permit from the Indian Patent Office. However, if the patent applicant has already filed a Patent in India, he may file a foreign patent after 6 weeks from the date of Filing of Indian Patent Application. Under Section 39 of the Indian Patent Act: “39. Residents not to apply for patents outside India without prior permission” (1) No person resident in India shall, except under the authority of a written permit sought in the manner prescribed and granted by or on behalf of the Controller, make or cause to be made any application outside India for the grant of a patent for an invention unless— (a) An application for a patent for same invention has been made in India, not less than six weeks before the application made outside India; and (b) Either no direction has been given under sub-section (1) of section 35 in relation to the application in India, or all such directions have been revoked. (2) The Controller shall dispose of every such application within such period as may be prescribed: Provided that if the invention is relevant for defense purpose or atomic energy, the Controller shall not grant permit without prior consent of the Central Government. (3) This section shall not apply in relation to an invention for which an application for protection has first been filed in a country outside India by a person resident outside India.” In all other cases, the patent applicant or inventor must obtain Foreign Filing Permission from the Indian Patent Office. IPO generally takes 4-8 weeks to grant foreign filing permissions. We would ideally like the patent office to grant Foreign Filing Licenses (FFL)/permissions within a week from the date of request.

Recommendation: Indian Patent Office (IPO) should consider (a) Use technology to do key word searches on requests/applications seeking FFL. (b) Applicants should be allowed to download FFLs FABLESS DESIGN

46

online after the application passes the key-word search. (c) While IPO implements a technology solution, IPO may consider granting FFLs within one week from the date of filing of FFL request.

Protection

of

Confidential

Information

(“Trade

Secrets”) For many companies, trade secrets form a critically important part of their IP portfolio and can be a substantial business differentiator. This holds true across a range of industrial sectors, including complex manufacturing, climate change technologies, defense, biotech, IT services, and food & beverages. Unlike patent rights that eventually expire, trade secrets can potentially be protected for an unlimited duration. Moreover, this protection arises without registration or other formalities, making trade secrets particularly attractive to Start-ups and SMEs that may not otherwise have the resources or sophistication to patent their innovations. India does not have a dedicated trade secret law which leaves companies to rely on contractual protection or other areas of law such as breach of confidence. While this is far from ideal, it is pleasing to see that there is a vigorous debate underway about improving the state of trade secret law. As Digital India and its supporting pillar, Make in India gain momentum, comprehensive trade secret reform would do much to support these objectives. Also, it is timely to note that there is a wave of trade secret reform underway worldwide suggesting that to stay competitive, India needs to follow the same path. India competes with neighboring countries and other emerging markets for FDI and will be quick to notice that Trans-Pacific Partnership Agreement (“TPP”) includes ground-breaking new measures to protect trade secrets including the adoption of criminal remedies. The value of trade secrets to MNCs and to the high-tech industry generally is well documented but what is less well understood is the importance of trade secrets to SMEs and in turn, value that MNCs gain from doing business in an environment where SMEs become ecosystem partners. In support of the TPP trade secret reforms, the US Chamber released a report entitled; “The Case for Enhanced Protection of Trade Secrets in the Trans-Pacific Partnership Agreement”4. The report made the following observations which have relevance in India:

4

https://www.uschamber.com/sites/default/files/legacy/international/files/Final%20TPP%20Trade%20Secrets%208_ 0.pdf FABLESS DESIGN

47

“The World Intellectual Property Organization (WIPO) highlights several case studies of trade secret protection playing a key role in the development of particular industries in emerging markets. Businesses in Singapore’s food products industry have relied heavily on trade secret protection for know-how such as recipes and specialty coffees.5 The rubber industry of Thailand, meanwhile, has used trade secret protection to safeguard know-how of the rubber recovery process. Due to the nature of the industry, the IP Management Group of Thailand’s National Science and Technology Development Agency found trade secret protection to be “vital to the successful commercialization of the [rubber recovery] technology.” India’s draft IP Strategy published in 2014, recognized the need to strengthen trade secret protection and acknowledged that protection in India is essentially contractual rather than statutory. As India continues to grow as an IT hub and an innovation economy, there is an opportunity to depart from the British model of contractual protection and to elevate trade secrets to genuine IP rights with statutory protection. This could be enhanced further with the addition of specific criminal sanction for deliberate misappropriation. Such provisions would do much to enhance investor confidence and encourage more high tech investment.”6 The option of enacting trade secret protection also raises many questions. Trade secret misappropriation is inherently one of the more difficult of the IP rights to prevent as often, the damage is done as soon as the secrets have been disclosed. It could also be argued that the British common law principles have served India well and that there has not been a raft of trade secret thefts to point to as a proof point for reform. Similarly, it can be said that a criminal law remedy could be ahead of its time for India where criminal enforcement is a greatly troubled area plagued with inefficiency. In summary; there are many excuses for doing nothing and waiting for a catastrophic proof point before enacting remedial law. We acknowledge the existence of a lively international debate on the value of enacting trade secret law and in particular, criminalizing intentional trade secret theft. However, on balance we believe that there is an overwhelming case for law reform in India. While much of the international press on trade secrets is taken up by a small number cases involving international espionage, the more relevant commercial justification for India is that strong trade secret law encourages high tech investment and increases confidence in the tech ecosystem and supports Make in India. This in turn creates more opportunities for SMEs to be part of international supply chains and gain the foothold they need to grow into larger companies and eventually become MNCs in their own right. Similarly, it can be argued that

5

Id. For example, in Brazil where no real IPR improvements have been made in the 90s, one researcher found that companies were “hesitant to train employees to use sensitive technology due to weak enforcement of trade secret protection,” and as a result, there were “[f]ew Brazilian companies willing to improve products.” Robert M. d, Intellectual Property Systems and Investment Stimulation: The Rating of Systems in Eighteen Developing Countries, IDEA: The Journal of Law and Technology, 37 IDEA 261 (1997). 6

FABLESS DESIGN

48

criminal reforms enhance trade secret protection simply by their existence as they create an effective deterrent which minimizes the chance of trade secret theft happening at all.

Recommendation: That the recommendations on Trade Secret Law contained in the National IP Policy be acted upon as soon as possible and that the law provide comprehensive reform and codification of law to include the criminalization of intentional trade secret theft.

FABLESS DESIGN

49

Import-Export

Issue

Recommendation

24X7 Green Channel Clearance for imports and exports.

There is need for an independent and dedicated policy and compliance guidelines with regard to imports by R&D units in India. Especially the compliance guidelines for import/export clearance processes at the customs ports need to be revised to cater to faster clearance of R&D / prototype samples. R&D units need to be allowed to clear all their R&D prototypes / engineering samples under a Green Channel facility based on the Risk Management System (RMS) established at the various ports.

The customs regulatory environment in India does not distinguish R&D activities from other commercially activities. The same rules and processes that govern commercial activity are applied to R&D activity. This hampers the ability of R&D companies to quickly move R&D samples and equipment in and out of the country.

Hand carry import and export for R&D samples The hand carry of critical R&D samples for carrying out testing and validation is a critical need for the R&D sector. The shrinking product life cycle for PC’s, tablets, smart phones and other form factor devices, requires R&D units to be produced over a faster life cycle. Transit time of importing samples is one of the key contributors in the supply chain of R&D units. Currently import of prototype / engineering samples are not allowed under the hand carry route and all these imports have to be done via cargo or courier mode of import.

Single window agency for issue of product regulatory licenses. Currently, multiple approvals / licenses are required for IT, Electronic components which are imported by R&D units. A separate license is needed from multiple government compliance administration departments like the Bureau of Indian Standards, Department of Telecommunication, Director General of Foreign Trade, Ministry of Environment and Forest, etc. The compliance requirements differ from agency to FABLESS DESIGN

Specific guidelines need to be notified for the import of R&D samples under the hand carry route. (Note: the customs regulations already allows imports under hand carry for the Gems and Jewelry sector subject to specific conditions) Change required: A time saving procedure is required so as to allow / clearance of hand carried items by the Assistant /Deputy Commissioner of Customs (AC/DC) /Station Duty Officer (SDO) at the airport after completing examination formalities and formalizing filing of the Bill of Entry procedures as post facto activity within a stipulated time frame. For the purpose of protecting customs revenue, a simple valuation guideline for computation of customs duties may be prescribed as per global standards. It should be noted that such inputs are not sold in the normal course of business transaction as most transactions are by way of intercompany transfer. There is urgent need to re-look at these regulations and revise the compliance requirements to cater to R&D activities. The appointment of single window agency to issue various licenses and approvals & also initiating a policy framework for certain new technologies, will help in reducing the lead time and also enable rapid growth of R&D in India. Empower the concerned development commissioners or directors of export processing zones, who would monitor 50

agency, which hinders seamless execution of R&D programs & increases lead time. Most of these regulations are old and suffer from lack of clarity on the applicability of the compliance requirements to R&D operations carried out under the export oriented scheme. Further, clarity in terms of timelines for issue of such licenses is found wanting.

a large portion of compliance of the R&D units operating under the export zone scheme, to administer compliances required under product regulatory regulation

All import and export transaction based on selfdeclaration without any prior approval.

There is need to have self-certification/declaration scheme for captive R&D units operating under export zone scheme. In this connection, a clear guidelines/scheme need to be established /notified from the foreign trade/customs authorities on the selfdeclaration/compliance for import/export clearance process at the customs and post clearance activities.

The current Foreign Trade Policy/Customs regulatory environment in India put huge emphasis on pre-approval for import and export transactions with multiple compliance administrative agencies for captive R&D units (operating under any export zone set up). This multiple pre-approval process is counter-productive for R&D operations especially when trying to move R&D samples/equipment quickly in and out of the country. This is also requiring the additional commitment of resources and systems from the government side too.

Changes required: the current Foreign Trade Policy/Customs guidelines established to monitor the transactional based approval system needs to be changed and R&D units allowed to be operated under a larger selfcertification / declaration scheme for day to day operations.

Incentivizing R&D

Issue Grant duty free status for import of consumables by captive R&D semiconductor undertakings Current foreign trade policy guidelines established for captive R&D units operating under the export zone scheme restricts the import of consumables under customs duty exemption mode. This significantly impacts the cost of conducting R&D activities in India.

Recommendation A policy change is needed to allow consumables under duty free mode for the R&D units operating under export processing zone (STPI). This will enable India to become cost competitive and a one stop destination allowing units from R&D operations to compete with neighboring countries currently extending this facility. Change Required: Define and allow the consumables which are used by the Software/R&D/IT – ITES/Semiconductor Hardware units operating under export processing zone (STPI) scheme Notify suitable Standard Input Output Norms (SION) for export of software/IT IT-ES and R&D services electronically without using disks, drives etc. as medium of export.

FABLESS DESIGN

51

Utilization of Funds available in Government schemes: There are many Government schemes/policies like Electronic Development Funds (EDF), Marketing and Export Promotion Scheme (MEPS), Department of Scientific & Industrial Research (DSIR) etc., from which funds are made available for various specified proposals. However, these funds are not available for the R&D units operating under STPI units. As the STPI units have the required ecosystem for promoting R&D and Innovation, such funds should be made available to STPI units for meaningful progress in R&D and Innovation. Future Investments in R&D - 25% of capital subsidy/R&D Cost

There is need for policy change to allow for cross utilization of these funds on specific investments by R&D units operating under export processing zone (STPI). Given the lower utilization of funds under these schemes, this would help grow the R&D sector in India if extended to STPI units.

Electronics and hardware design require significant investment in talent, labs and equipment. Government may consider giving subsidy/ tax breaks on investments made to meet the industry’s efforts.

Other Reforms

Issues Publishing sensitive R&D information Currently all the import and export information from R&D units are being published under the customs regulations. Some of the data mining companies get hold of these data, partnering with market analysts and using this data to speculate on progress of R&D programs. This is impacting significantly on sensitive R&D programs and product road map for R&D units. Centralize administration Mechanism-Currently the administration of STPI units is based on the location. The units having pan-India based operations need to register with multiple STPI directorates and customs/central excise agencies.

Empower DG STPI/Local STPI director with delegated powers of IMSC. The current scheme of IMSC process for the special approvals / and issue of necessary policy-administrative guidelines is not providing effective support for STPI units. The approval process is too long and subjective FABLESS DESIGN

Recommendation There is need of policy change to exclude publishing of such information by customs for the R&D units operating under export processing zone (STPI).

It is requested to notify the centralized administration scheme (Change from Unit based registration to Legal Entity based registration) for the unit’s operating under pan-India basis.

The request. Empower DG STPI/Local STPI directors with the delegated powers currently resting with IMSC. This will benefit industry at large.

52

MOEF Licensing for import of used Electronic Goods to support R & D. The new scheme introduced post 2014, calls for an open license to be secured from MOEF for water falling any used electronics goods. The licensing process takes around 3 Months and is issued for a period of 18 Months.

It is requested that items imported for R&D by STPI unit should get an exemption from the licensing.

Necessary to secure No Objection Certificate (NOC) from MOEF for any re export return of electronics goods sent for repair/ calibration etc.

Government has already issued revised rules exempting license for re-import but these are not Gazetted yet.

Alternatively: Empower local STPI director to issue licenses: This should be a one-time license linked to an existing main STPI license.

Request; the Ministry should expedite having the revised rules published in gazette.

Experimental Licenses for Spectrum - WPC (Wireless Planning & Coordination) e.g. license for testing of Wi Gig modules operating at a frequency band of 57-66 Ghz.

Request; There is a need for a blanket approval for testing Wi Gig modules for a minimum period of two years across various models but within the same frequency and power of radiation levels.

R&D in broadband and other related technologies need availability of experimental spectrum Licenses. The current system of obtaining experimental license is cumbersome where one need to be procured from WPC before the import/ test of any Wi Gig products needed to support R & D activities. This system is model-centric. The whole process of securing grant letter, Import License (IL) and Experimental License (EL) takes anywhere from 3-5 Months. The EL, which is issued for 3 months can only be renewed for an additional three months as this is under Radiating license.

FABLESS DESIGN

53

Improving India’s regulatory framework for Ease of Doing Business: Providing simple regulatory guidelines, moving all processes online, and ensuring less paperwork and less bureaucratic discretion would do much to improve Ease of Doing Business. Beyond that, there is a need to attract more investment to help strengthen the ecosystem of businesses that will enable growth and inspire confidence in the ease of establishing, maintaining and growing business. The Government of India has already embarked on an agenda to improve India’s Doing Business ranking and the new Budget has brought about welcome improvements which should see this rating improve.

Issues

Recommendations

Streamline Service tax refunds process

There is a need to amend the current law to make refund claims process easier –

In line with the stated policy of the Government to zero-rate exports, all exporters are eligible for a refund of un-utilized Cenvat Credit in respect of inputs and input services. However, some INR 37000 Crores of such refunds claimed by exporters is pending with the Government. The refunds process is extremely onerous due to conditions around eligibility of specific categories of input services and unreasonable documentation requirements from the tax authorities. Funds that may be critically required to invest in the business are stuck with the tax authorities making India an expensive place for doing business

FABLESS DESIGN

There should be no restriction on the categories of input services that are eligible for refund. A portion of refunds (say 50%) should be granted upfront (within 15 days) for companies with a proven track record. Once the refund is granted, the authorities can carry out detailed scrutiny. Any refund granted erroneously can be demanded back (within the same deadline of 15 days) without interest. Policy changes to align with SEZ’s – upfront exemption vs. refunds (to be considered for GST as well).

54