Compal La-8951p R0.1 Schematics

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Compal Confidential 1

Model Name : VIUS3/S4 File Name : LA-8951PR01 BOM P/N:43

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Compal Confidential 2

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VIUS3/S4 M/B Schematics Document Intel Ivy Bridge ULV Processor + Panther Point PCH AMD Seymour XT

2011-12-28

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3

REV:0.1

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4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

2012/07/12

Deciphered Date

Title

Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

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Thursday, February 02, 2012

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Compal confidential

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Chief River

File Name :VIUS3/VIUS4

AMD Seymour XT 23mm *23mm

1

D

Intel IVY Bridge SV/ULV (Sandy Bridge) Processor

PCI-E X16 Gen 2

VRAM 128MB*16 gDDR3*4

UP TO 1G

DDR3-SO-DIMM X1 1

BANK 0, 1 Dual Channel DDR3-1066/1333(1.5V) for Sandy Bridge DDR3-1600(1.5V) for Ivy Bridge

BGA1023

SATA3.0 HDD CONN FDI *8 100MHz 2.7GT/s

HDMI 1.4a

Std HDMI Connector

DMI2 *4 100MHz 5GT/s

SATA3.0 HDD (SSD) 6*SATA

(port0,1 Support SATA3) 2

PX 5.0

LVDS Connector

PCI Express (Half) Mini card Slot 1

USB(WiMAX)

6*PCI-E x1

PCI-E(WLAN)

WLAN/WiMAX

PCI Express (Full) Mini card Slot 2 SSD

2

Intel Panther Point

4*USB3.0 14*USB2.0

USB PORT 3.0 x1 (Left) HM77/HM70

USB PORT 2.0 x2 (Right)

FCBGA 989 Balls 25mm*25mm

mSATA(SSD)

IO Board

HD Audio

Card Reader RTS 5178 (2in1) IO Board

Gen 2

3

CMOS Camera BlueTooth CONN WLAN/WiMAX WWAN

LPC BUS

SPI ROM BIOS 4MB*1 2MB*1

EC ENE KB9012

WLAN/WiMAX

LAN(10/100/Giga) Realtek 8105E-VD (10/100) 8111F-VL (Giga)

2Channel Speaker

Int.KBD RealTek ALC259-VC2

RJ45 CONN Sub-borad

Single Digital MIC

Audio Codec

Touch Pad

4

3

Audio Combo Jack (APPLE type)

Thermal Sensor

HeadPhone Output Microphone Input

EMC1403

POWER BOARD

4

IO Board

LED BOARD Compal Secret Data

Security Classification 2011/07/21

Issued Date

IO Board

2012/12/31

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

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MB Block Diagram Rev 0.2

Thursday, February 02, 2012

Sheet E

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Voltage Rails

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SIGNAL

STATE

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Full ON +5VS +3VS

power plane

+1.5VS +1.05VS_VTT

1

+5VALW

+1.5V

+CPU_CORE

+3VALW

+1.5V_IO

+B

+VGA_CORE

BOARD ID Table

+1.8VS +0.75VS

O

S3

O

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

1

+VCC_GFXCORE_AXG

State

S0

+VALW

O

Board ID 0 1 2 3 4 5 6 7

O

O

O

O

X

O

O

X

X

S5 S4/ Battery only

O

X

X

X

S5 S4/AC & Battery don't exist

X

X

X

X

Board ID / SKU ID Table for AD channel Vcc Ra/Rc/Re

PCB Revision 0.1

Board ID

0 1 2 3 4 5 6 7

3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC

V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V

V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V

Porject

V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V

G-series G-series G-series G-series Y-series Y-series Y-series Y-series

Phase

MP PVT DVT EVT EVT DVT PVT MP

2

2

S5 S4/AC

USB Port Table USB 3.0 xHCI1 xHCI2 xHCI3 xHCI4

Address

EC SM Bus1 address

EC SM Bus2 address

Device

Device

Smart Battery

0001 011X b

BOM Structure Table

USB 2.0 UHCI0 UHCI1 EHCI1 UHCI2

Address

Thermal Sensor F75303M

Port

1001_101xb

UHCI3

PCH SM Bus address

3

UHCI4

Device

Address

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

EHCI2

UHCI5 UHCI6

AMD-GPU SM Bus address Device

Address

Internal thermal sensor

1001 111Xb (0x9E)

0 1 2 3 4 5 6 7 8 9 10 11 12 13

3 External USB Port USB 3.0 Port (Left Side) Mini Card(WLAN) X (USB PORT disabled on HM70 ) X (USB PORT disabled on HM70 ) X (USB PORT disabled on HM70 ) X (USB PORT disabled on HM70 ) USB/B (Right Side USB-BD) USB/B (Right Side USB-BD) USB Port (Right Side CR-BD)

Camera (LVDS) X (USB PORT disabled on HM70 )

HM70 Disable xHCI3,xHCI4

SMBUS Control Table

4

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMBCLK SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA

KB9012

+3VALW KB9012

+3VALW PCH

+3VALW PCH

+3VALW PCH

+3VALW

VGA

BATT

X X X X V +3VS

V +3VALW X X X X

3

X (USB PORT disabled on HM70 )

SATA Port Table

SOURCE

BTO Item BOM Structure INTEL UMA only UMA@ GPU:Seymour XT PX@ PX5@ HDMI HDMI@ HDD1 (HM77 SATA 3.0) HDD1@ HDD2 (HM70 SATA 2.0) HDD2@ Interna-Intel-USB3.0 IU3@ Interna-Intel-USB2.0 IU2@ Blue Tooth BT@ 10/100 LAN 8105E@ GIGA LAN 8111F@ Connector ME@ 45 LEVEL 45@ Unpop @

WLAN KB9012 SODIMM WWAN

X X X X V +3VS

X X V +3VS X X

X X V +3VS X X

SATA SATA SATA SATA SATA SATA

Thermal Sensor PCH

X X X X V +3VS

X V +3VS X X X

HM77 HM70 P0 GEN3/2/1 GEN3/2/1 P1 GEN3/2/1 Disable GEN2/1 P2 GEN2/1 Disable P3 GEN2/1 GEN2/1 P4 GEN2/1 GEN2/1 P5 GEN2/1

PCIe Port Table SSD HDD (HM77) HDD (HM70)

HM70 Disable P1,P3

PCIe PCIe PCIe PCIe PCIe PCIe PCIe PCIe

B

HM77

HM70

Enable

Enable

LAN

Enable

Enable

WLAN

Enable

Enable

Enable

Enable

Enable

Disable

Enable

Disable

Enable

Disable

Enable

Disable

4

HM70 Disable P5,P6,P7,P8

2011/06/15

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/11

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

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P1 P2 P3 P4 P5 P6 P7 P8

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Notes List Document Number

Rev 0.2

LA-7981P Friday, February 03, 2012

Sheet E

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Without BACO option :

Power-Up/Down Sequence

PXS_RST# : Low -> Reset dGPU ; High ->Normal operation PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. D

BACO option :

2. VDDR3 should ramp-up before or simultaneously with VDDC.

4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up. 5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).)

Note: Do not drive any IOs before VDDR3 is ramped up.

VDDR3(3.3VGS)

D

PXS_RST# : High ->Normal operation (dGPU is not reset on BACO mode) PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)

3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.

PCIE_VDDC(1.0V) VDDR1(1.5VGS) C

1

dGPU Power Pins

Voltage

PX 3.0

BACO Mode Max current

PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD, DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI, DPLL_PVDD, MPV18, and SPV18

1.8V

OFF

ON

1679mA

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and SPV10

1.0V

OFF

ON

575mA

PCIE_VDDC

1.0V

OFF

ON

2A

VDDR3 , and A2VDD

3.3V

OFF

ON

190mA

BIF_VDDC (current consumption = [email protected], in BACO mode) BIF_VDDC=VGA_CORE When GPU enable BIF_VDDC=1.0V When BACO

Same as VDDC

OFF

ON Same as PCIE_VDDC

70mA

VDDR1

1.5V

OFF

OFF

2.8A

VDDC/VDDCI

1.12V

OFF

OFF

12.9A C

VDDC/VDDCI(1.12V) VDD_CT(1.8V)

iGPU

PXS_RST#

PE_EN

dGPU

PERSTb

BACO Switch

BIF_VDDC PXS_PWREN

REFCLK

PX_mode

+3.3VALW

Straps Reset

+1.0V

Straps Valid

B

+3.3VGS

MOS

1

Regulator

2

+1.5V

+1.0VGS

+1.5VGS

SI4800

3

Regulator

4

Global ASIC Reset +1.8V

SI4800

T4+16clock

+B

+1.8VGS

5

B

+VGA_CORE

PWRGOOD

CPU part

PCB part ZZZ2

UCPU1

CPU1@

I3_3217 1.8G

SA00005L510

UCPU1

CPU2@

I5_3427 1.8G

SA00005L900

UCPU1

CPU3@

I5_2557 1.4G

SA00004VZ00

UCPU1

CPU4@

ZZZ1

ZZZ3

ZZZ4

ZZZ5

977_1.4G

Hynix

S512@ X7641338L01

PCB 0R LA-8951P REV0 M/B

SA00005BJ40

DA60000TO00

Hynix

H512@ X7641338L02

Hynix

S1G@ X7641338L03

Hynix

H1G@ X7641338L04

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/15

Issued Date

Deciphered Date

2012/07/11

Title

VGA Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.2

LA-7981P

Date:

5

4

3

2

Thursday, February 02, 2012

Sheet 1

4

of

55

A

B

C

D

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils - typical impedance = 14.5 mohms

1

+1.05VS_VTT

R249 24.9_0402_1% UCPU1A

[15] [15] [15] [15]

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

N3 P7 P3 P11

[15] [15] [15] [15]

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

[15] [15] [15] [15]

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

[15] [15] [15] [15] [15] [15] [15] [15]

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

[15] [15] [15] [15] [15] [15] [15] [15]

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

[15] [15]

FDI_FSYNC0 FDI_FSYNC1

[15]

FDI_INT

[15] [15]

FDI_LSYNC0 FDI_LSYNC1

K3 M7 P4 T3

U7 W11 W1 AA6 W6 V4 Y2 AC9 U6 W10 W3 AA7 W7 T4 AA3 AC8 AA11 AC12 U11

1 2

R247 24.9_0402_1%

K1 M8 N4 R2

AA10 AG8

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]

FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC

W=12mil L=500mil S=15mil EDP_COMP

3

AF3 AD2 AG11 AG4 AF4

AC1 AA4 AE10 AE6

eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX# eDP_AUX

eDP

AC3 AC4 AE11 AE7

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PCI EXPRESS -- GRAPHICS

M2 P6 P1 P10

Intel(R) FDI

+1.05VS_VTT

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms can't be left floating ,even if disable eDP function...

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI

2

[15] [15] [15] [15]

eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

G3 G1 G4

2

W=12mil L=500mil S=15mil

1

E

PEG_COMP

1

Layout placement: Place close to U8 (GPU)

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

PEG_GTX_C_HRX_N0 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N15

C259 C276 C257 C274 C254 C272 C252 C270 C250 C268 C248 C267 C246 C264 C244 C262

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@

0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K

PEG_GTX_HRX_N0 PEG_GTX_HRX_N1 PEG_GTX_HRX_N2 PEG_GTX_HRX_N3 PEG_GTX_HRX_N4 PEG_GTX_HRX_N5 PEG_GTX_HRX_N6 PEG_GTX_HRX_N7 PEG_GTX_HRX_N8 PEG_GTX_HRX_N9 PEG_GTX_HRX_N10 PEG_GTX_HRX_N11 PEG_GTX_HRX_N12 PEG_GTX_HRX_N13 PEG_GTX_HRX_N14 PEG_GTX_HRX_N15

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

PEG_GTX_C_HRX_P0 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P15

C258 C277 C256 C275 C255 C273 C253 C271 C251 C269 C249 C266 C247 C265 C245 C263

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@

0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K

PEG_GTX_HRX_P0 PEG_GTX_HRX_P1 PEG_GTX_HRX_P2 PEG_GTX_HRX_P3 PEG_GTX_HRX_P4 PEG_GTX_HRX_P5 PEG_GTX_HRX_P6 PEG_GTX_HRX_P7 PEG_GTX_HRX_P8 PEG_GTX_HRX_P9 PEG_GTX_HRX_P10 PEG_GTX_HRX_P11 PEG_GTX_HRX_P12 PEG_GTX_HRX_P13 PEG_GTX_HRX_P14 PEG_GTX_HRX_P15

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

PEG_HTX_GRX_N0 PEG_HTX_GRX_N1 PEG_HTX_GRX_N2 PEG_HTX_GRX_N3 PEG_HTX_GRX_N4 PEG_HTX_GRX_N5 PEG_HTX_GRX_N6 PEG_HTX_GRX_N7 PEG_HTX_GRX_N8 PEG_HTX_GRX_N9 PEG_HTX_GRX_N10 PEG_HTX_GRX_N11 PEG_HTX_GRX_N12 PEG_HTX_GRX_N13 PEG_HTX_GRX_N14 PEG_HTX_GRX_N15

C562 C582 C564 C584 C566 C587 C568 C589 C570 C591 C572 C593 C574 C594 C576 C597

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@

0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K

PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N15

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_HTX_GRX_P0 PEG_HTX_GRX_P1 PEG_HTX_GRX_P2 PEG_HTX_GRX_P3 PEG_HTX_GRX_P4 PEG_HTX_GRX_P5 PEG_HTX_GRX_P6 PEG_HTX_GRX_P7 PEG_HTX_GRX_P8 PEG_HTX_GRX_P9 PEG_HTX_GRX_P10 PEG_HTX_GRX_P11 PEG_HTX_GRX_P12 PEG_HTX_GRX_P13 PEG_HTX_GRX_P14 PEG_HTX_GRX_P15

C561 C583 C563 C585 C565 C586 C567 C588 C569 C590 C571 C592 C573 C595 C575 C596

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@

0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K

PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P15

PEG_GTX_HRX_N[0..15] PEG_GTX_HRX_P[0..15]

[22] [22]

PEG_HTX_C_GRX_N[0..15] PEG_HTX_C_GRX_P[0..15]

[22] [22]

2

3

IVY-BRIDGE_BGA1023 @

Typ- suggest 220nF. The change in AC capacitor value from 100nF to 220nF is to enable compatibility with future platforms having PCIE Gen3 (8GT/s)

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

Issued Date

Deciphered Date

2012/07/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Custom

Rev 0.1

Sherry and Royal

Date:

Sheet

Thursday, February 02, 2012 E

5

of

55

A

B

C

D

E

+1.05VS_VTT CLK_CPU_DPLL#

R517 2

1 1K_0402_5%

CLK_CPU_DPLL

R516 2

1 1K_0402_5%

Checklist1.5 P.67 Graphis Disable Guide DIS only SKU eDP disable DPLL_REF_SSCLK PD 1K_5% to GND DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT 1

1

UCPU1B

[17]

F49

H_SNB_IVB#

偵偵CPU有有有有

Follow DG 1.5& Tacoma_Fall2 1.0 reserve

XBOX

PROC_SELECT#

C57

T33 PAD @ H_CATERR#

C49

@ C614 2

1 0.1U_0402_16V4Z

H_CPUPWRGD_R

follow Checklist 1.5 R292

2

1 10K_0402_5%

+1.05VS_VTT [37,42]

R534 2

[18,37]

1 62_0402_5% H_PROCHOT#

H_PROCHOT#

H_PECI R533 56_0402_5% 1 2

[18]

A48

H_PECI

H_PROCHOT#_R

PECI

C45

PROCHOT#

D45

H_THERMTRIP#

DPLL_REF_CLK DPLL_REF_CLK#

PM_SYNC

UNCOREPWRGOOD:

[18]

1 R305

H_CPUPWRGD

2 H_CPUPWRGD_R 0_0402_5%

B46

UNCOREPWRGOOD

R237

1 2 VDDPWRGOOD_R 130_0402_1%

BE45

SM_DRAMPWROK

SM_DRAMPWROK:DRAM power ok BUF_CPU_RST#

CLK_CPU_DPLL CLK_CPU_DPLL#

SM_RCOMP2 W=15mil L=500mil S=13mil SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

AT30

SM_DRAMRST#

BF44 BE43 BG43

SM_RCOMP0 R272 SM_RCOMP1 R273 SM_RCOMP2 R267

SM_DRAMRST#

2 2 2

1 140_0402_1% 1 25.5_0402_1% 1 200_0402_1%

@

C82

100P_0402_50V8J

[7]

1

2

DDR3 Compensation Signals

D44

RESET#

TCK TMS TRST#

JTAG & BPM

C48

H_PM_SYNC

AG3 AG1

THERMTRIP#

PWR MANAGEMENT

[15]

非CORE外外外OK

CLK_CPU_DMI [14] CLK_CPU_DMI# [14]

SM_RCOMP0,SM_RCOMP1 W=20mil L=500mil S=13mil

PRDY# PREQ#

2

J3 H2

CATERR#

THERMAL

三三三三

PROC_DETECT#

CLOCKS

外外外

BCLK BCLK#

DDR3 MISC

都 後後

MISC

非 做

PROC_SELECT# PH VCPLL and connect to PCH DF_TVS

PCH->CPU UNCOREPWRGOOD: CORE OK SM_DRAMPWROK:DRAM power ok RESET#: ok CPU reset

TDI TDO

N53 N55 L56 L55 J58

XDP_TCK XDP_TMS XDP_TRST#

M60 L59

XDP_TDI XDP_TDO

ESD C Reserve 2

PU/PD for JTAG signals DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

K58

+1.05VS_VTT

XDP_DBRESET#

G58 E55 E59 G55 G59 H60 J59 J61

R20 R39 R37

2 2 2

XDP_TCK R40 XDP_TRST# R28

2 2

XDP_TMS XDP_TDI XDP_TDO

1 51_0402_5% 1 51_0402_5% 1 51_0402_5% @

+3VS XDP_DBRESET# R312 2

1 51_0402_5% 1 51_0402_5%

1 1K_0402_5%

Tacoma_Fall2 1.0 PH 1K +3VS Check list 1.5 PH 1K +3VS Debug port DG1.1-1.3 50~5K ohm

IVY-BRIDGE_BGA1023 @

+3VALW

+3VS

+1.05VS_VTT

D

2 G Q4 2N7002K_SOT23-3

RUN_ON_CPU1.5VS3#

BUF_CPU_RST#

4

SN74LVC1G07DCKR_SC70-5

NC

Y A

1 2PCH_PLTRST#

PCH_PLTRST#

[17]

3

C43 0.1U_0402_16V4Z @

5

U45 BUFO_CPU_RST#

S @

3

RUN_ON_CPU1.5VS3#

R544 43_0402_5% 1 2

2

R38 39_0402_5%

1 2

@

[10]

C617 0.1U_0402_16V4Z

R546 75_0402_5%

1

74AHC1G09GW_TSSOP5

3

2

A

4PM_SYS_PWRGD_BUF

P

P

1

5 2

O

1

PM_DRAM_PWRGD

B

3

[15]

1

G

@ R35 10K_0402_5% 1 2

SYS_PWROK

2

U22

[15]

G

R238 200_0402_5%

1

1

C228 0.1U_0402_16V4Z

2

R31 10K_0402_5% 1 2

1

3

Buffered reset to CPU +1.5V_CPU_VDDQ

2

+3VS

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

Deciphered Date

2012/07/12

Title

PROCESSOR(3/7) DDRIII

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

A

B

C

D

Thursday, February 02, 2012

Sheet E

6

of

55

A

B

C

D

UCPU1C

UCPU1D

DDR_A_D[0..63]

1

2

3

[12] [12] [12]

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

[12] [12] [12]

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

AG6 AJ6 AP11 AL6 AJ10 AJ8 AL8 AL7 AR11 AP6 AU6 AV9 AR6 AP8 AT13 AU13 BC7 BB7 BA13 BB11 BA7 BA9 BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

AU36 AV36 AY26

AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9 BD13 BF12 BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60

SA_CLK_DDR0 [12] SA_CLK_DDR#0 [12] DDRA_CKE0_DIMMA [12]

AT40 AU40 BB26

SA_CLK_DDR1 [12] SA_CLK_DDR#1 [12] DDRA_CKE1_DIMMA [12]

BB40 BC41

DDRA_CS0_DIMMA# DDRA_CS1_DIMMA#

AY40 BA41

SA_ODT0 SA_ODT1

[12] [12]

[12] [12]

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS#[0..7]

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS[0..7]

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_MA[0..15]

[12]

[12]

[12]

BG39 BD42 AT22

AV43 BF40 BD45

IVY-BRIDGE_BGA1023 @

3

[37]

1 R62

2 DRAMRST_CNTRL 0_0402_5%

DRAMRST_CNTRL

DRAMRST_CNTRL_EC

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

2

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

3

1

1

2

G

[10]

1 R64

2 0_0402_5% DS3@

1

For DS3

1 R219

2 1K_0402_5%

DIMM_DRAMRST#

S0 DRAMRST_CNTRL_PCH hgih ,MOS ON SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH Dimm not reset S3 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# lo,DDR3 DRAMRST# HIGH Dimm not reset S4,5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# lo,DDR3 DRAMRST# low Dimm reset

4

DRAMRST_CNTRL_PCH

SB_CK[1] SB_CK#[1] SB_CKE[1]

R212 1K_0402_5%

1 DIMM_DRAMRST#_R Q16 BSS138_NL_SOT23-3

2

SM_DRAMRST# R217 4.99K_0402_1%

[14]

1

IVY-BRIDGE_BGA1023 @

D

SM_DRAMRST#

S

[6]

通通DIMM做reset

BA34 AY34 AR22

2

CPU

SB_CK[0] SB_CK#[0] SB_CKE[0]

+1.5V

Follow CRB1.0 R216 0_0402_5% 1 2 @

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

DDR SYSTEM MEMORY B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR SYSTEM MEMORY A

[12]

E

C190 0.047U_0402_16V7K

2

[12]

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

2012/07/12

Deciphered Date

Title

PROCESSOR(3/7) DDRIII

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

A

B

C

D

Thursday, February 02, 2012

Sheet E

7

of

55

A

B

C

D

E

CFG Straps for Processor CFG2

1

49.9_0402_1%

2

VCC_VAL_SENSE

R91 100_0402_1%

1

@ VCC_VAL_SENSE VSS_VAL_SENSE

H43 K43

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

H45 K45

VCC_VAL_SENSE VSS_VAL_SENSE

2

VSS_VAL_SENSE R306

1

49.9_0402_1% T18

PAD @

F48 H48 K48

2

2

+VGFX_CORE

R310

1

49.9_0402_1%

2

VAXG_VAL_SENSE

R95 100_0402_1%

1

@

BA19 AV19 AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26 BF23 BE24

VSSAXG_VAL_SENSE

VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_DIE_SENSE

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

2

1

PEG Static Lane Reversal - CFG2 is for the 16x 1: Normal Operation; Lane # definition matches socket pin map definition

CFG2

M13 M14 U14 W14 P13

*

AT49 K24

RSVD45

AH2 AG13 AM14 AM15 N50

*

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

R293 1K_0402_1%

1:Disable 0:Enable

2

CFG6 CFG5

R543 1K_0402_1% @

These pins are for solder joint reliability and non-critical to function. For BGA only.

R541 1K_0402_1% @

PCIE Port Bifurcation Straps

2 R311

(Default) 1x16 PCI Express *11: 10: 2x8 PCI Express 01: Reserved

IVY-BRIDGE_BGA1023 @

00: 1x8,2x4 PCI Express

1

3

關關

eDP enable CFG4

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

啟啟

UMA,Optimus eDP DISO eDP

@

RSVD41 RSVD42 RSVD43 RSVD44

CFG[6:5] 49.9_0402_1%

0:Lane Reversed

CFG4

RSVD39 RSVD40

RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

N42 L42 L45 L47

1

R302

RSVD30 RSVD31 RSVD32 RSVD33

R296 1K_0402_1%

N59 N58

2

2

CFG4 CFG5 CFG6 CFG7

BCLK_ITP BCLK_ITP#

1

+CPU_CORE

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17]

2

CFG2 1

B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53

1

CFG0

2

PAD @

RESERVED

T32

1

UCPU1E

3

1

CFG7 R297 1K_0402_1%

2

@

Tacoma_Fall2 1.0 P.12

PEG DEFER TRAINING CFG7

1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

Issued Date

Deciphered Date

2012/07/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

PROCESSOR(4/7) RSVD,CFG

Size Document Number Custom

Rev 0.1

Sherry and Royal

Date:

Sheet

Thursday, February 02, 2012 E

8

of

55

B

C

UCPU1F

ULV type DC 33A

D

POWER

8.5A +1.05VS_VTT

INTEL Recommend VCCIO 2*330UF,10*10uF(0603) and 26*1uF(0402) PD0.8 CAP at Power side

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

For PEG

2

+3VS

R521 10K_0402_5%

W16 W17

VCCIO_SEL

1

VCCIO_SEL after Ivy bridge ES2 Voltage support

R522 10K_0402_5% @

BC22 2

VCCIO_SEL

BC22

*

1/NC : (Default) +1.05VS_VTT 0: +1.0VS_VTT

VCCIO_SEL

+1.05VS_VTT

A44 B43 C44

R529 75_0402_5%

R528 1 R527 1 R530 1

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

2 43_0402_1% 2 0_0402_5% 2 0_0402_5%

VR_SVID_ALRT# [50] VR_SVID_CLK [50] VR_SVID_DAT [50]

+CPU_CORE

1 1 R79

2

R281 100_0402_1%

R282 1 R289 1

R513 1

AN16 AN17

0_0402_5% 0_0402_5%

2 10_0402_5% +1.05VS_VTT

VCCIO_SENSE VSSIO_SENSE_L

@

VCCSENSE VSSSENSE

R512 10_0402_5%

Should change to connect form power cirucit & layout differential with VCCIO_SENSE.

2

IVY-BRIDGE_BGA1023 @

[50] [50]

R288 100_0402_1%

VCCIO_SENSE [47] VSSIO_SENSE_L [47]

1

VCCIO_SENSE VSS_SENSE_VCCIO

2 2

1

F43 VCCSENSE_R G43 VSSSENSE_R

2

VCC_SENSE VSS_SENSE

2

100_0402_1%

SENSE LINES

3

Place the PU resistors close to CPU

2

R531 130_0402_5%

1 2 C553 1U_0402_6.3V6K

VIDALERT# VIDSCLK VIDSOUT

+1.05VS_VTT

1

AM25 AN22

1

+1.05VS_VTT

VCCPQE[1] VCCPQE[2]

Place the PU resistors close to VR

4

1

1

PEG IO AND DDR IO

For DDR

+1.05VS_VTT

VCCIO50 VCCIO51

SVID

3

VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

QUIET RAILS

2

CORE SUPPLY

INTEL Recommend VCC 4*470UF,12*22uF(0805) and 35*2.2uF(0402) PD0.8 CAP at Power side

1

VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] VCC[26] VCC[27] VCC[28] VCC[29] VCC[30] VCC[31] VCC[32] VCC[33] VCC[34] VCC[35] VCC[36] VCC[37] VCC[38] VCC[39] VCC[40] VCC[41] VCC[42] VCC[43] VCC[44] VCC[45] VCC[46] VCC[47] VCC[48] VCC[49] VCC[50] VCC[51] VCC[52] VCC[53] VCC[54] VCC[55] VCC[56] VCC[57] VCC[58] VCC[59] VCC[60] VCC[61] VCC[62] VCC[63] VCC[64] VCC[66] VCC[67] VCC[68] VCC[69] VCC[70] VCC[71] VCC[72] VCC[73] VCC[74] VCC[75] VCC[76]

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

2

VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29]

+CPU_CORE

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

E

2

A

4

Check list 1.5

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

2012/07/12

Deciphered Date

Title

PROCESSOR(5/7) PWR,BYPASS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

A

B

C

D

Thursday, February 02, 2012

Sheet E

9

of

55

A

B

C

+1.5V

D

E

+1.5V_CPU_VDDQ @ J1 2

2

2

R175 15K_0402_1% 1 2

SUSP#

1 2 @ 0_0402_5% R82

@

BSS138_NL_SOT23-3 Q2204

1

2

DRAMRST_CNTRL_PCH DRAMRST_CNTRL

S

[7] 1

1

1 G

S

S

Q8 2N7002K_SOT23-3

2

R77 330K_0402_5% @

2

D 2

G Q6 2N7002K_SOT23-3

RUN_ON_CPU1.5VS3#

G

C115 0.047U_0603_25V7K

3

[37,40,45,46,47,49]

1

1 CPU1.5V_S3_GATE

2

3

[37,40]

1 0_0402_5%

+VREF_DQ_DIMMA

1

1

1 1 2 RUN_ON_CPU1.5VS3#

2

2 0_0402_5%

@

3

SA_DIMM_VREFDQ

2 Q7 2N7002K_SOT23-3

RUN_ON_CPU1.5VS3

D

@ R81

1

R86

D

R85 82K_0402_5%

@

M3 Support C116 0.1U_0402_10V6K

G

R78 100K_0402_5%

@

D

1 2 3

S

+VSB

+3VALW

1

R80 220_0402_5%

U11 AO4430L_SO8 8 7 6 5

2

R65

3

1 0_0402_5%

SUSP

4

[40,45,46]

1

PAD-OPEN 4x4m

2

1

+1.5V_CPU_VDDQ +1.5V 1

+V_SM_VREF

1

2

1

@ R116 1K_0402_1% 2

RUN_ON_CPU1.5VS3

2

SA_DIMM_VREFDQ SB_DIMM_VREFDQ Check list1.5 P18 M1 default M3 no stuff

@

C349

@

1

@

2

INTEL Recommend VDDQ 1*330uF,8*10uF(0603) ,10*1uF(0402) PD0.8

C316

2

1 2

1

1 2

2

1

1 2

1 2

1

1 2

2

2 @

C320

1 + C286 330U_D2_2V_Y 2

@

Place BOT OUT BGA

1

C298

2

1 2

1

1 2

2

1

1 2

2

1 2

1

C339

10U_0603_6.3V6M

C299

10U_0603_6.3V6M

C295

10U_0603_6.3V6M

C296

10U_0603_6.3V6M

C338

10U_0603_6.3V6M

C337

10U_0603_6.3V6M

C340

2

DDR3

@

C318

1U_0402_6.3V6K

@

C312

1U_0402_6.3V6K

@

C328

1U_0402_6.3V6K

@

C348

1U_0402_6.3V6K

@

C351

1U_0402_6.3V6K

C329

10U_0603_6.3V6M

GRAPHICS

+1.5V_CPU_VDDQ

Place TOP IN BGA C321

10U_0603_6.3V6M

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8] VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

1U_0402_6.3V6K

- 1.5V RAILS

5A AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

1

@

2

1

1

2

R124 1K_0402_1%

R518 @ 1K_0402_1% 2

R519 @ 1K_0402_1%

1

2

2

3

G

VREF

@ R76 1K_0402_1%

Q11 AO3414_SOT23-3

C117 0.1U_0402_16V4Z

1U_0402_6.3V6K

1

R113 1K_0402_1% D

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

1 0_0402_5%

@

SGA20331E10 S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9

R308

3

2 +1.5V_CPU_VDDQ

Place TOP IN BGA +VCCSA

@

@

@

1 2

1 2

1 2

1

1

2

2 @

C308 1U_0402_6.3V6K

B phase Cost down proposal 4

C301 1U_0402_6.3V6K

@

C300 1U_0402_6.3V6K

2

1U_0402_6.3V6K

SGA20331E10 S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9

+ C242 330U_D2_2V_Y

C302 1U_0402_6.3V6K

C309

1

1 2

1 2

1 2

1

1 2

1

VDDQ_SENSE VSS_SENSE_VDDQ

2

1 0.1U_0402_10V7K

C151

2

1 0.1U_0402_10V7K

C152

2

1 0.1U_0402_10V7K

C157

2

1 0.1U_0402_10V7K

VCCSA

U10

VCCSA_SENSE

CPU EDS1.3 P.93 VCCSA_VID0 Must PD

+VCCSA_SENSE

@ D48 D49

VCCSA_VID[0] VCCSA_VID[1]

[48]

VID0 VID1 Vout

R248 0_0402_5%

H_VCCSA_VID0 H_VCCSA_VID1

H_VCCSA_VID0 H_VCCSA_VID1

ULV HR

CR

0

0

0.9V

V

V

0

1

0.85V

V

V

1

0

0.775V

X

V

1

1

0.75V

X

V

[48] [48]

4

C559 10U_0603_6.3V6M

2

VCCSA[1] VCCSA[2] VCCSA[3] VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16]

IVY-BRIDGE_BGA1023 @

C579 10U_0603_6.3V6M

C555 10U_0603_6.3V6M

C560 10U_0603_6.3V6M

10U_0603_6.3V6M

C577

L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20

C150

BC43 BA43

@

Place BOT OUT BGA

INTEL Recommend VCCSA 1*330uF,5*10uF(0603) ,5*1uF(0402) PD0.8

6A

C317 1U_0402_6.3V6K

+1.5V

1

2

SENSE LINES

1 2

1 2

1

C280 1U_0402_6.3V6K

2

C281 1U_0402_6.3V6K

C153

10U_0603_6.3V6M C633

22U_0805_6.3V6M

+VCCSA

1

VCCPLL[1] VCCPLL[2] VCCPLL[3]

VCCSA VID lines

2

BB3 BC1 BC4

SA RAIL

1.2A

100_0402_5%

Place BOT OUT Conn

1.8V RAIL

R309

+1.5V_CPU_VDDQ

AM28 AN26

VCCDQ[1] VCCDQ[2]

2

VAXG_SENSE VSSAXG_SENSE

1

[50] VCC_AXG_SENSE [50] VSS_AXG_SENSE

QUIET RAILS

F45 G45

SENSE LINES

2

100_0402_1%

2

1 R87 100_0402_5% @

+1.8VS

+V_SM_VREF_CNT

BE7 BG7

1U_0402_6.3V6K

3

+VGFX_CORE

AY43

1U_0402_6.3V6K

CR CheckList Rev1.5

SM_VREF SA_DIMM_VREFDQ SB_DIMM_VREFDQ

R117 2

S

2

VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32] VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56]

1U_0402_6.3V6K

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46 N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61

INTEL Recommend VAXG 2*470uF,6*22uF(0805) and 6*10uF(0603) 11*1U(0402) PD0.8

INTEL Recommend VCCPLL 1*330uF,2*1uF(0402) PD0.8

POWER

DC 29A

1

UCPU1G +VGFX_CORE

+V_SM_VREF_CNT should have 20 mil trace width

1

[6]

2

RUN_ON_CPU1.5VS3#

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

Deciphered Date

2012/07/12

Title

PROCESSOR(6/7) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size R&D Document Number Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

A

B

C

D

Thursday, February 02, 2012 E

Sheet

10

of

55

A

B

C

D

E

UCPU1H UCPU1I

2

3

4

VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

VSS

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53 BG9 C29 C35 C40 D10 D14 D18 D22 D26 D29 D35 D4 D40 D43 D46 D50 D54 D58 D6 E25 E29 E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G51 G6 G61 H10 H14 H17 H21 H4 H53 H58 J1 J49 J55 K11 K21 K51 K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61 M11 M15

VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249]

VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

VSS

NCTF

1

A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 A9 AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46 AC6 AD17 AD20 AD4 AD61 AE13 AE8 AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61 AG7 AH4 AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48 AJ7 AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61 AM13 AM20 AM22 AM26 AM30 AM34

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48

1

2

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

3

IVY-BRIDGE_BGA1023 @

4

Issued Date IVY-BRIDGE_BGA1023 @

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

Deciphered Date

2012/07/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

A

PROCESSOR(7/7) VSS

B

C

D

Thursday, February 02, 2012

Sheet E

11

of

55

A

B

C

D

E

+1.5V +VREF_DQ_DIMMA

+1.5V

DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17

[7]

DDR_A_MA[0..15]

[7]

DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19

Layout Note: Place near JDIMM1

+1.5V

DDR_A_D24 DDR_A_D25 DDR_A0_DM3

2

1

2

C310 1U_0402_6.3V6K

2

1

C291 1U_0402_6.3V6K

1

C326 1U_0402_6.3V6K

2

C294 1U_0402_6.3V6K

1

DDR_A_D26 DDR_A_D27

[7]

[7]

DDR_A_BS2

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

2

+1.5V

DDR_A_MA8 DDR_A_MA5

2

1

2

C289 10U_0603_6.3V6M

2

1

C314 10U_0603_6.3V6M

1

C284 10U_0603_6.3V6M

2

C287 10U_0603_6.3V6M

1

DDR_A_MA3 DDR_A_MA1 [7] [7]

+1.5V

+

[7]

DDR_A_BS0

DDR_A_MA10 DDR_A_BS0

[7] [7]

DDR_A_WE# DDR_A_CAS#

DDR_A_WE# DDR_A_CAS#

DDRA_CS1_DIMMA#

DDR_A_MA13 DDRA_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

@

2

DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41

3

DDR_A0_DM5 DDR_A_D42 DDR_A_D43

+0.75VS

DDR_A_D48 DDR_A_D49

2

1

2

C414 1U_0402_6.3V6K

2

1

C413 1U_0402_6.3V6K

1

C412 1U_0402_6.3V6K

2

C411 1U_0402_6.3V6K

1

DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A0_DM7 DDR_A_D58 DDR_A_D59

Layout Note: Place near JDIMM1.203,204 +3VS

2

205 207 R336 10K_0402_5%

GND1 BOSS1

GND2 BOSS2

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

DIMM_DRAMRST#

[7]

DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A0_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31

DDRA_CKE1_DIMMA

DDRA_CKE1_DIMMA

[7]

DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7

2

DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 SA_CLK_DDR1 SA_CLK_DDR#1

SA_CLK_DDR1 SA_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_A_BS1 [7] DDR_A_RAS# [7]

DDRA_CS0_DIMMA# SA_ODT0

DDRA_CS0_DIMMA# SA_ODT0 [7]

SA_ODT1

SA_ODT1

[7] [7]

+1.5V

[7]

R265 1K_0402_1%

[7]

+VREF_CA DDR_A_D36 DDR_A_D37

1

DDR_A0_DM4 DDR_A_D38 DDR_A_D39

2

DDR_A_D44 DDR_A_D45

R269 1K_0402_1%

DDR_A_DQS#5 DDR_A_DQS5

3

DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A0_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 SMB_DATA_S3 SMB_CLK_S3

SMB_DATA_S3 [14,31,38] SMB_CLK_S3 [14,31,38]

+0.75VS

206 208

TYCO_2-2013022-1

Channel A 4

1

2 1

2

2

R331 10K_0402_5%

1

C408 0.1U_0402_16V4Z

1

+0.75VS C409 2.2U_0402_6.3V6M

4

DDR_A0_DM0 DDR_A0_DM1 DDR_A0_DM2 DDR_A0_DM3 DDR_A0_DM4 DDR_A0_DM5 DDR_A0_DM6 DDR_A0_DM7

CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT

1

DDR_A0_DM1 DIMM_DRAMRST#

C354 2.2U_0402_6.3V6M

@ 2

1

SA_CLK_DDR0 SA_CLK_DDR#0

C311 220U_B2_2.5VM_R35

2

1

C343 10U_0603_6.3V6M

1

C293 10U_0603_6.3V6M

2

C303 10U_0603_6.3V6M

1

[7]

SA_CLK_DDR0 SA_CLK_DDR#0

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT

DDR_A_D12 DDR_A_D13

C353 0.1U_0402_16V4Z

73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

DDRA_CKE0_DIMMA

DDRA_CKE0_DIMMA

DDR_A_D6 DDR_A_D7

1

DDR_A_D[0..63]

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_DQS#0 DDR_A_DQS0

2

[7]

DDR_A_D8 DDR_A_D9

DDR_A_D4 DDR_A_D5

1

[7]

DDR_A_DQS[0..7]

2

DDR_A_D2 DDR_A_D3

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

2

DDR_A_DQS#[0..7]

1

VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS

1

1 2

2

1

R226 1K_0402_1%

C221 0.1U_0402_16V4Z

1

DDR_A0_DM0

VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS

2

1 2

DDR_A_D0 DDR_A_D1

C222 2.2U_0402_6.3V6M

All VREF traces should have 10 mil trace width

+1.5V JDIMM1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

+VREF_DQ_DIMMA R223 1K_0402_1%

DIMM_1 Standard H:4.0mm

ME@



Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

2012/07/12

Deciphered Date

Title

DDRIII DIMMB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

A

B

C

D

Thursday, February 02, 2012

Sheet E

12

of

55

A

B

C

D

E

1

1

RTCRST close to RAM door

R501 0_0603_5%

@

U13A

@ 2

Prevent back drive issue. 2

C440 1U_0402_6.3V6K

G

2

+5VS

+RTCBATT

Q3 BSS138_NL_SOT23-3 1

3

HDA_SYNC_PCH_R 2 1M_0402_5%

SM_INTRUDER#

R355 1

2 330K_0402_5%

PCH_INTVRMEN

[36]

R48 1

INTVRMEN

1

：Integrated VRM enable L：Integrated VRM disable

SM_INTRUDER#

K22

PCH_INTVRMEN

C17

HDA_BITCLK_PCH

N34

HDA_SYNC_PCH

L34

HDA_SPKR

T10

HDA_RST_PCH#

K34

0_0402_5% HDA_SDIN0

HDA_SDIN0

E34

2

G34 C34

(INTVRMEN should always be pull high.)

A34 +3VS R109 1

2 1K_0402_5%

@

HDA_SPKR

HDA_SDOUT_PCH

A36

HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature

*

R162 1

LOW= Disable (Default internal PD) +3V_PCH

2

@

R341 2 @

HDA_SDOUT_PCH

2 1K_0402_1%

PCH_GPIO33

C36

1 10K_0402_5%

PCH_GPIO13

N32

R100 51_0402_5% 2 1

PCH_JTAG_TCK

J3

PCH_JTAG_TMS

H7

HDA_SDO

PCH_JTAG_TDI

K5

ME debug mode,this signal has a weak internal PD Low = Disabled (Default) High = Enabled [Flash Descriptor Security Overide]

PCH_JTAG_TDO

H1

[37]

*

+3V_PCH

R46 1K_0402_5% 2 1 @ R73 0_0402_5% 2 1

ME_FLASH

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

G22

HDA_SPKR

2 @

R29 [36] 1M_0402_5%

H

D20

PCH_SRTCRST#

D

S

R358 1

PCH_RTCRST#

RTCX2 RTCRST#

FWH4 / LFRAME# SRTCRST# INTRUDER#

LDRQ0# LDRQ1# / GPIO23

INTVRMEN

SERIRQ

HDA_BCLK

SATA 6G

1 1

R372 0_0603_5%

RTCX1

HDA_SYNC SPKR HDA_RST# HDA_SDIN0

SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXP

HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDO HDA_DOCK_EN# / GPIO33

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA

C20

PCH_SRTCRST#

RTC

PCH_RTCX2

PCH_RTCRST#

1

*

A20

IHDA

1 2 R356 20K_0402_5% 1 2 R357 20K_0402_5%

PCH_RTCX1

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

HDA_DOCK_RST# / GPIO13 SATA5RXN SATA5RXP SATA5TXN SATA5TXP

JTAG_TCK

JTAG

2

C439 1U_0402_6.3V6K

2

+RTCBATT

JTAG_TMS JTAG_TDI

SATAICOMPO SATAICOMPI

JTAG_TDO SATA3RCOMPO SATA3COMPI

C38 A38 B37 C37

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

D36

LPC_FRAME#

2

1 1K_0402_5%

HDA_SYNC_PCH SPI_SB_CS0#

Y14

SPI_SB_CS1#

T1

On Die PLL VR Select is supplied by

*1.5V when sampled high

SPI_SI

1.8V when sampled low Needs to be pulled High for Huron River platfrom

SPI_SO_R

V4 U3

SPI_CLK

SATA3RBIAS

LPC_FRAME#

+3VS SERIRQ

[31,37]

SPI_CS1#

SATALED#

SPI_MOSI

SATA0GP / GPIO21

SPI_MISO

SATA1GP / GPIO19

[36]

[36] [36]

HDA_SYNC_AUDIO

HDA_RST_AUDIO# HDA_SDOUT_AUDIO

R134 200_0402_5%

HDA_BITCLK_PCH

2

HDA_SYNC_PCH_R

2

HDA_RST_PCH#

2

HDA_SDOUT_PCH

+3V_PCH

1

+3V_PCH

1

+3V_PCH

2

R143 200_0402_5%

R266 1

V5

SERIRQ

AM3 AM1 AP7 AP5

SERIRQ

[37]

2 2

SATA_PTX_DRX_C_N0 SATA_PTX_DRX_C_P0

SATA_PRX_DTX_C_N0 [31] SATA_PRX_DTX_C_P0 [31] SATA_PTX_DRX_N0 [31] SATA_PTX_DRX_P0 [31]

1 C1185 0.01U_0402_16V7K 1 C1208 0.01U_0402_16V7K

AM10 AM8 AP11 AP10

SATA_DTX_C_R_PRX_N1 SATA_DTX_C_R_PRX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1

R148 R149 R150 R151

HDD1@ HDD1@ HDD1@ HDD1@

2 2 2 2

1 1 1 1

0_0402_5% 0_0402_5% 0_0402_5% SATA_PTX_R_DRX_N1_CO HDD1@ 2 0_0402_5% SATA_PTX_R_DRX_P1_CO HDD1@ 2

AD7 AD5 AH5 AH4

SATA_DTX_C_R_PRX_N2 SATA_DTX_C_R_PRX_P2 SATA_PTX_DRX_N2 SATA_PTX_DRX_P2

R154 R157 R160 R161

HDD2@ HDD2@ HDD2@ HDD2@

2 2 2 2

1 1 1 1

0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

AB8 AB10 AF3 AF1

1 1

R137 200_0402_5%

R127 1

2SPI_HOLD#1 3.3K_0402_5% 2 SPI_WP# 3.3K_0402_5%

SPI_SB_CS1# SPI_SO_R

R172 0_0402_5% 2 1 1 2

Disable w/ HM70

Y3 Y1 AB3 AB1

2

Y11

L=500mil S=15mil

Y10

SATA_COMP

AB12

L=500mil S=15mil

AB13

SATA3_COMP

1 R121

RBIAS_SATA3

+1.05VS_VTT

1

2 49.9_0402_1%

1

2 750_0402_1%

R126 AH1

+1.05VS_VTT 2 37.4_0402_1%

R440

2

+3VS

GPIO19 has internal Pull up GPIO21 Debug Port DG 1.2 PH 4.7K +3VS

P3 V14 P1

BBS_BIT0_R

R466

2

1 10K_0402_5%

PCH_SATALED#

R429

2

1 10K_0402_5%

PCH_GPIO21

R136

2

1 10K_0402_5%

PCH_SATALED# PCH_GPIO21

No use PH 10K +3VS

BBS_BIT0_R

Boot BIOS

8MB SPI ROM FOR ME & Non-share ROM.

*

LPC Reserved SPI

GPIO51 0 0 1 1

GPIO19 0 1 0 1

3

U46 CS1# SPI_SO1 SPI_WP#1

R188 33_0402_5%

1 2 3 4

CS# SO WP# GND

VCC HOLD# SCLK SI

8 7 6 5

SPI_HOLD#1 SPI_CLK1 SPI_SI1

0_0402_5% R199 2 SPI_CLK_PCH_R 2 SPI_SI R196 33_0402_5%

1 1

C459 10P_0402_50V8J 1 2 2 @ R434

Reserve for EMI 1 @

SPI_CLK_PCH_R 33_0402_5%

2SPI_HOLD# 3.3K_0402_5%

R142 100_0402_1%

U6 Rersver 4M+2M Solution +3VS

2

R140 100_0402_1% 2

2

R141 100_0402_1%

R171 1 PCH_JTAG_TDI

HDD1 w/ HM70

1

2 1

2 1

PCH_JTAG_TMS

[35] HDD0 w/ HM77 [35] [35] Disable w/ HM70 [35]

Y7 Y5 AD3 AD1

16M W25Q16BVSSIG SOIC 8P PCH_JTAG_TDO

SSD

SATA_DTX_C_PRX_N1 SATA_DTX_C_PRX_P1 C1209 0.01U_0402_16V7K SATA_PTX_R_DRX_N1 C1223 0.01U_0402_16V7K SATA_PTX_R_DRX_P1

SATA_DTX_C_PRX_N1 SATA_DTX_C_PRX_P1 SATA_PTX_R_DRX_N1_CO SATA_PTX_R_DRX_P1_CO

+3VS

2 SPI_WP#1 3.3K_0402_5%

1 10K_0402_5%

Boot BIOS Strap

+3VS

R221 1

1

3

HDA_BITCLK_AUDIO



[36]

2

1

PANTHER_FCBGA989 R75 33_0402_5% 1 R30 33_0402_5% 1 R74 33_0402_5% 1 R72 33_0402_5% 1

R118

SPI_CS0#

SPI

T3

SPI_CLK_PCH_R R47

[31,37] [31,37] [31,37] [31,37]

E36 K36

+3V_PCH

This signal has a weak internal pull-down

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

C191 1 2 PCH_RTCX1 1 R406 4

1

2 10M_0402_5% Y2

R173 0_0402_5% 1 SPI_SB_CS0#2 1 2 SPI_SO_R

PCH_RTCX2

33_0402_5% R169

2

U44 CS# SPI_SO_L SPI_WP#

1 2 3 4

CS# SO WP# GND

0.1U_0402_16V4Z VCC HOLD# SCLK SI

8 7 6 5

SPI_HOLD# SPI_CLK_PCH 1 1 SPI_SI_R

32M W25Q32BVSSIG SOIC 8P

0_0402_5% R168 2 SPI_CLK_PCH_R 2 SPI_SI R170 33_0402_5%

4

18P_0402_50V8J

32.768KHZ_12.5PF_9H03200019

1

1 C452

2

C451 18P_0402_50V8J

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2

2011/06/24

2012/07/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

D

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number Custom

Rev 0.1

Sherry and Royal

Date:

Thursday, February 02, 2012

Sheet E

13

of

55

B

C

D

E

+3V_PCH

U13B

WLAN_CLKREQ#_R

R110

2

1 10K_0402_5%

PCH_GPIO20

R414

2

1 10K_0402_5%

PCH_GPIO25

BF36 BE36 AY34 BB34

+3V_PCH

R389

2

1 10K_0402_5%

LAN_CLKREQ#_R

R53

2

1 10K_0402_5%

PCH_GPIO26

R50

2

1 10K_0402_5%

PCH_GPIO44

R32

2

1 10K_0402_5%

PCH_GPIO45

R51

2

1 10K_0402_5%

PCH_GPIO46

R54

2

1 10K_0402_5%

HM70 not support PCIE port 4-7

BG37 BH37 AY36 BB36 BJ38 BG38 AU36 AV36 BG40 BJ40 AY40 BB40

PCH_GPIO56

BE38 BC38 AW 38 AY38

[32] [32]

PCIE LAN 2

No use PH 10K +3VALW

[32]

[31] [31]

WLAN

[31]

No use PH 10K +3VS

CLK_PCIE_LAN# CLK_PCIE_LAN LAN_CLKREQ#

CLK_PCIE_WLAN1# CLK_PCIE_WLAN1 WLAN_CLKREQ#

1 1

R153 R163

1

R164

2 0_0402_5% CLK_PCIE_LAN#_R 2 0_0402_5% CLK_PCIE_LAN_R 2 0_0402_5% LAN_CLKREQ#_R

Y40 Y39 J2

R165 R166

1 1

2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 2 0_0402_5% CLK_PCIE_WLAN1_R AB47

R167

1

2 0_0402_5% WLAN_CLKREQ#_R

M1 AA48 AA47

No use PH 10K +3VS

PCH_GPIO20

V10 Y37 Y36

No use PH 10K +3VALW

PCH_GPIO25

A8 Y43 Y45

No use PH 10K +3VALW

PCH_GPIO26

L12

PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5

SML0DATA

SML1ALERT# / PCHHOT# / GPIO74 SML1CLK / GPIO58 SML1DATA / GPIO75

PERN6 PERP6 PETN6 PETP6 PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8

CL_CLK1 CL_DATA1 CL_RST1#

PCH_SML0CLK

G12

PCH_SML0DATA

R405

1

2

2.2K_0402_5%

PCH_SMBDATA

R370

1

2

2.2K_0402_5%

DRAMRST_CNTRL_PCH

R391

1

2

DRAMRST_CNTRL_PCH

S3 reduse

[7]

1K_0402_5%

PCH_HOT#

R392

1

2

10K_0402_5%

PCH_SML1CLK

R403

1

2

2.2K_0402_5%

PCH_SML1DATA

R369

1

2

2.2K_0402_5%

PEG_CLKREQ#_R

R25

1

2

10K_0402_5%

No use PH 10K +3VALW

C13

PCH_HOT#

E14

PCH_SML1CLK

EC-PCH SMBUS

M16

PCH_SML1DATA

PH 2.2K +3VALW

PCH_HOT#

1

UMA@

No use PH 10K +3VALW

[37]

+3VS

For DDR R404 2.2K_0402_5% 1 2

M7 PCH_SMBDATA 6

T11

1

@ 2 R9 1 0_0402_5%

P10

PEG_CLKREQ#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

AB37 AB38

PEG_CLKREQ#_R

1

R56

3

CLK_PCIE_VGA#_R CLK_PCIE_VGA_R

4

PCIECLKRQ1# / GPIO18 CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P CLKOUT_PCIE2N CLKOUT_PCIE2P CLKIN_DMI_N CLKIN_DMI_P

PCIECLKRQ2# / GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P

CLKIN_DMI2_N CLKIN_DMI2_P

PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLKIN_DOT_96P CLKOUT_PCIE4N CLKOUT_PCIE4P CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P

PCIECLKRQ4# / GPIO26

AV22 AU22

CLK_CPU_DMI# CLK_CPU_DMI

CLK_PCIE_VGA# [22] CLK_PCIE_VGA [22]

CLK_CPU_DMI# [6] CLK_CPU_DMI [6]

2

1

3

PCH_SML1CLK CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI

R152 1 R147 1

2 10K_0402_5% 2 10K_0402_5%

BJ30 BG30

CLKIN_GND1# CLKIN_GND1

R453 1 R452 1

2 10K_0402_5% 2 10K_0402_5%

G24 E24

CLK_BUF_DREF_96M# CLK_BUF_DREF_96M

R99 R93

1 1

2 10K_0402_5% 2 10K_0402_5%

AK7 AK5

CLK_BUF_PCIE_SATA# R139 1 CLK_BUF_PCIE_SATA R138 1

2 10K_0402_5% 2 10K_0402_5%

K45

CLK_BUF_ICH_14M

R101 1

2 10K_0402_5%

H45

CLK_PCI_LPBACK

V47 V49

XTAL25_IN XTAL25_OUT

EC_SMB_DA2

EC_SMB_DA2

[23,34,37]

4

EC_SMB_CK2

EC_SMB_CK2

[23,34,37]

Q33B DMN66D0LDW-7_SOT363-6

+3V_PCH

Pull down 10K ohm for using internal Clock

R551 2.2K_0402_5% PCH_SML0CLK

L14 AB42 AB40

No use PH 10K +3VALW

PCH_GPIO56

E6 V40 V42

No use PH 10K +3VALW

PCH_GPIO45

T13 V38 V37

No use PH 10K +3VALW

PCH_GPIO46 PCIE_CLK_8N PCIE_CLK_8P

K12 AK14 AK13

PCIECLKRQ5# / GPIO44

CLKIN_PCILOOPBACK

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

XTAL25_IN XTAL25_OUT

PCH_SML0DATA

2 R96

W=12mil S=15mil

PEG_B_CLKRQ# / GPIO56 XCLK_RCOMP

R545 2.2K_0402_5%

Y47

XCLK_RCOMP

1 @ 33_0402_5%

1 @

C29

CLK_PCI_LPBACK

2 22P_0402_50V8J

[17]

3

Reserve for EMI please close to PCH R120 90.9_0402_1% 1 2

+1.05VS_VTT

CLKOUT_PCIE6N CLKOUT_PCIE6P

+3VS

PCIECLKRQ6# / GPIO45 CLKOUT_PCIE7N CLKOUT_PCIE7P PCIECLKRQ7# / GPIO46 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

1

PCH_GPIO44

K43 F47

K49

PCH_LAN_48M

DGPU_PRSNT#

DGPU_PRSNT#

PANTHER_FCBGA989

XTAL25_IN

R421 10K_0402_5%

UMA@

H47 LAN_48M1 R207 @2 22_0402_5%

1

XTAL25_OUT

2

No use PH 10K +3VALW

REFCLK14IN

R431

2

3

CLKOUT_PCIE5N CLKOUT_PCIE5P

FLEX CLOCKS

V45 V46

[12,31,38]

Pull up at EC side. For VGA,EC,Thermal sensor

Q33A DMN66D0LDW-7_SOT363-6

AM12 AM13 BF18 BE18

SMB_CLK_S3

SMB_CLK_S3

+3VS

PCH_SML1DATA 6

CLKOUT_DMI_N CLKOUT_DMI_P

[12,31,38]

Q34B DMN66D0LDW-7_SOT363-6

210K_0402_5%

R58 PX@0_0402_5% 2 1 CLK_PCIE_VGA# 2 1 CLK_PCIE_VGA R59 PX@0_0402_5%

SMB_DATA_S3

R371 2.2K_0402_5% 1 2 +3VS

[23]

PX@

M10

+3VS

SMB_DATA_S3

Q34A DMN66D0LDW-7_SOT363-6

PCH_SMBCLK

PEG_A_CLKRQ# / GPIO47

CLKOUT_PCIE1N CLKOUT_PCIE1P

DDR,WLAN,XDPSMBUS PH 2.2K +3VALW

DRAMRST_CNTRL_PCH

C8

PCH_SMBCLK

EC LID SW OUT

No use PH 10K +3VALW

CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0# / GPIO73

A12

10K_0402_5%

2

1 10K_0402_5%

SML0CLK

PCH_SMBDATA

2

2

2

SML0ALERT# / GPIO60

C9

1

1

R424

PERN3 PERP3 PETN3 PETP3

PCH_SMBCLK

R33

5

+3VS

SMBDATA

H14

PCH_GPIO11

5

BG36 BJ36 AV34 AU34

PERN2 PERP2 PETN2 PETP2

PCH_GPIO11

2

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

BE34 BF34 BB32 AY32

SMBCLK

E12

2

1 1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

SMBALERT# / GPIO11

Link

1

C482 C481

2 0.1U_0402_16V7K 2 0.1U_0402_16V7K

No use PH 10K +3VALW PERN1 PERP1 PETN1 PETP1

SMBUS

WLAN

1 1

BG34 BJ34 AV32 AU32

Controller

[31] PCIE_PRX_DTX_N2 [31] PCIE_PRX_DTX_P2 [31] PCIE_PTX_C_DRX_N2 [31] PCIE_PTX_C_DRX_P2

C480 C478

PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

CLOCKS

PCIE LAN

PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1

PCI-E*

[32] [32] [32] [32]

1

A

3 2

R420 10K_0402_5%

PX@

1 1



C457 10P_0402_50V8J

2 1M_0402_5% OSC NC

NC OSC

4 1

Y3 25MHZ_10PF_7V25000014

1

2

2

C468 10P_0402_50V8J

GPIO67 DGPU_PRSNT# 4

4

DIS,Optimus UMA

Compal Electronics, Inc.

Compal Secret Data

Security Classification Issued Date

0 1

2011/06/24

2012/07/12

Deciphered Date

Title

PCH (2/9) PCIE, SMBUS, CLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

A

B

C

D

Thursday, February 02, 2012

Sheet E

14

of

55

A

B

C

D

E

U13C

+3V_PCH 1

R34

2

1 10K_0402_5%

SUSWARN#_R

R49

2

1 10K_0402_5%

PCH_GPIO72

R390

2

1 10K_0402_5%

RI#

1 300_0402_5%

PM_DRAM_PWRGD

2

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

BE24 BC20 BJ18 BJ20

[5] [5] [5] [5]

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

AW24 AW20 BB18 AV18

[5] [5] [5] [5]

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

AY24 AY20 AY18 AU18

+1.05VS_VTT

1 10K_0402_5%

PCH_RSMRST#

+3VS

2 DMI_IRCOMP 49.9_0402_1% 2 DMI2RBIAS 750_0402_1%

[37]

1

not support AMT APWROK can mux with PWROK (check list1.5 P.47) [37]

R303 1 @

PCH_APWROK

[6]

FDI_FSYNC0

DMI_IRCOMP

FDI_FSYNC1

DMI2RBIAS

FDI_LSYNC0 FDI_LSYNC1

[37]

[37]

DS3@ 1 200K_0402_5%

AC_PRESENT_R

[37]

1 R129 D3 1

PBTN_OUT#

[23,37,43]

ACIN

2 PCH_PWROK_R 0_0402_5%

L22

2 PBTN_OUT#_R 0_0402_5%

SYS_RESET# SYS_PWROK PWROK

2

3

Ring Indicator CRB1.0 PH 10K +3VALW

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

AC_PRESENT_R

WAKE#

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

AW16

FDI_INT

AV12

FDI_FSYNC0

BC10

FDI_FSYNC1

AV14

FDI_LSYNC0

BB10

FDI_LSYNC1

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

[5] [5] [5] [5] [5] [5] [5] [5]

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

[5] [5] [5] [5] [5] [5] [5] [5]

FDI_INT

H20 E10

DSWODVREN

E22

PCH_DPWROK

B9

PCH_PCIE_WAKE#

N3

CLKRUN#

G8

SUS_STAT#

N14

SUSCLK

D10

PM_SLP_S5#

H4

PM_SLP_S4#

F4

PM_SLP_S3#

G10

SLP_A#

G16

SLP_SUS#

1 R133

DSWODVREN

*

R350

2

R368

2

1 330K_0402_5% 1 330K_0402_5%

@

： ：

DSWODVREN - On Die DSW VR Enable H Enable internal DSW +1.05VS 1

L Disable Must always PH at +RTCVCC +3V_PCH PCH_PCIE_WAKE# R374

1

PCH_GPIO29

R36

1

CLKRUN#

R423

1

2 10K_0402_5%

[5]

FDI_FSYNC0

A18

+RTCBATT

[5]

FDI_FSYNC1

[5]

FDI_LSYNC0

[5]

FDI_LSYNC1

[5]

@

2 10K_0402_5% +3VS

@

PCH_DPWROK

2 R135 DS3@

2 8.2K_0402_5%

10_0402_5%

DPWROK_EC

[37]

not support Deep S4,S5 DPWROK mux with RSMRST# check list1.5 P.50

2 PCH_RSMRST# 0_0402_5%

PCH_PCIE_WAKE#

[31,32] 2

CLKRUN# / GPIO32 SUS_STAT# / GPIO61 SUSCLK / GPIO62 SLP_S5# / GPIO63 SLP_S4#

PWRBTN#

A10

RI#

DPWROK

SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#

E20

RB751V-40_SOD323-2 PCH_GPIO72

No use PH 10K +3VALW

SUSACK#

K3 P12

1 2 PCH_RSMRST# R125 0_0402_5% R1489 0_0402_5% 2 1 SUSWARN#_R DS3@

SUSWARN#

C12

SYS_PWROK

PM_DRAM_PWRGD

EC_RSMRST#

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

For DS3

2 0_0402_5% APWROK L10

PM_DRAM_PWRGD

For DS3

For Deep S3 2

BH21

2 XDP_DBRESET#_R 10K_0402_5%

1 R107

PCH_PWROK

AEPWROK can be connect to PWROK if iAMT disable

R195

DMI_ZCOMP

BG25

R1468 0_0402_5% 2 1 SUSACK#_R DS3@

SUSACK# +3VS

APWROK

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

DSWVRMEN

R415

+3VALW

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

For DS3

2

1 0_0402_5%

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

4mil width and place within 500mil of the PCH

PM_DRAM_PWRGD

not support Deep S4,S5 can be left unconnected. Check list1.5 P.81

PCH_PWROK_R 2 R191

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

BJ24

L=500mil S=15mil

1 R156 1 R155 R397 @ 2 1 200_0402_5%

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_INT

Follow G R394

[5] [5] [5] [5]

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

1

2

R393

BC24 BE20 BG18 BG20

SLP_A#

ACPRESENT / GPIO31

SLP_SUS#

BATLOW# / GPIO72

PMSYNCH

RI#

SLP_LAN# / GPIO29

AP14

H_PM_SYNC

K14

PCH_GPIO29

T1@

PAD

R375 10K_0402_5% SUSCLK

T4@

[37]

2

AC_PRESENT_R

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

FDI

1 200K_0402_5%

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

System Power Management

2

R26

[5] [5] [5] [5]

DMI

+3V_PCH

PM_SLP_S5#

[37]

PM_SLP_S4#

[37]

PM_SLP_S3#

[37]

PAD

SLP_SUS# H_PM_SYNC

[37,40]

0111 Add R375 to GND

Can be left NC when IAMT is not support on the platfrom

For DS3

[6]

not support Deep S4,S5 can NC PCH EDS1.5 P.75 3

If Intel LAN no use, can let be NC.

PANTHER_FCBGA989 +3VS

Y A

SYS_PWROK

3

MC74VHC1G08DFT2G_SC70-5

SYS_PWROK

R119 100K_0402_5%

2

R104 10K_0402_5%

4

[6]

1

1

2

VGATE

1

[50]

P

U36 2 B

PCH_PWROK

PCH_PWROK

G

[37]

5

tell PCH all power ok but cpu core

ALL power OK

C52

1

0.047U_0402_16V7K @2

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

Deciphered Date

2012/07/12

Title

PCH (3/9) DMI,FDI,PM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

A

B

C

D

Thursday, February 02, 2012

Sheet E

15

of

55

A

B

C

D

E

U13D

1

1

2 2.2K_0402_5%

CTRL_CLK

R105

1

2 2.2K_0402_5%

CTRL_DATA

CTRL_CLK CTRL_DATA

L=500mil S=20mil

Change to eDP only R108

T40 K47

R132

DIS only can NC

2.37K_0402_1% 2 1

W=10mil S=30mil

LVDS_IBG

AF37 AF36

LVD_VREF

AE48 AE47

UMA LVDS DDC R428

1

2 2.2K_0402_5%

EDID_CLK

R425

1

2 2.2K_0402_5%

EDID_DATA

Check list1.5 P.60 disable Graphics ALL Can NC but DAC_IREF still need PD LVDS disable: DATA/Clock/Control an NC VCC_TX_LVDS,VCCA_LVDS PD to GND 2

CRT disable: DATA/Clock/Control an NC VCCADAC connect to +3VS DAC_IREF connect 1K_0402_5%

[29] [29]

LVDS_ACLK# LVDS_ACLK

[29] [29] [29]

LVDS_A0# LVDS_A1# LVDS_A2#

[29] [29] [29]

LVDS_A0 LVDS_A1 LVDS_A2

T45 P39

LVDS_ACLK# LVDS_ACLK

AK39 AK40

LVDS_A0# LVDS_A1# LVDS_A2#

AN48 AM47 AK47 AJ48

LVDS_A0 LVDS_A1 LVDS_A2

AN47 AM49 AK49 AJ47 AF40 AF39

UM77 not support LVDS/CRT

AH45 AH47 AF49 AF45 AH43 AH49 AF47 AF43

N48 P49 T49 T39 M40 M47 M49 3

T43 T42

SDVO_INTN SDVO_INTP

AP39 AP40

R144 2.2K_0402_5% HDMI@

L_CTRL_CLK L_CTRL_DATA

1

LVD_IBG LVD_VBG

SDVO_CTRLCLK SDVO_CTRLDATA

LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_CLK CRT_DDC_DATA

R131 2.2K_0402_5% HDMI@

DDPB_AUXN DDPB_AUXP DDPB_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA

CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN

DDPD_AUXN DDPD_AUXP DDPD_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

P38 M39

HDMICLK_NB HDMIDAT_NB

AT49 AT47 AT40

TMDS_B_HPD#

HDMICLK_NB HDMIDAT_NB

[30] [30]

TMDS_B_HPD#

AV42 TMDS_B_DATA2#_PCH AV40 TMDS_B_DATA2_PCH AV45 TMDS_B_DATA1#_PCH AV46 TMDS_B_DATA1_PCH AU48 TMDS_B_DATA0#_PCH AU47 TMDS_B_DATA0_PCH AV47 TMDS_B_CLK#_PCH AV49 TMDS_B_CLK_PCH

HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@

C406 C352 C539 C538 C535 C534 C537 C536

1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2

[30]

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

HDMI_TX2-_CK HDMI_TX2+_CK HDMI_TX1-_CK HDMI_TX1+_CK HDMI_TX0-_CK HDMI_TX0+_CK HDMI_CLK-_CK HDMI_CLK+_CK

[30] [30] [30] [30] [30] [30] [30] [30]

HDMI D2 HDMI D1

HDMI

HDMI D0 HDMI CLK

P46 P42

Place close to connector side AP47 AP49 AT38

2

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 M43 M36 AT45 AT43 BH41 BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

3

PANTHER_FCBGA989

R114 1K_0402_5%



2

CRT disable use 1K_0402_5%

AM42 AM40

1

SDVO_STALLN SDVO_STALLP

L_DDC_CLK L_DDC_DATA

+3VS

AP43 AP45 1

L_BKLTCTL

1

CRT_IREF

SDVO_TVCLKINN SDVO_TVCLKINP

2

+3VS

P45

EDID_CLK EDID_DATA

L_BKLTEN L_VDD_EN

2

PCH_PWM

J47 M45

Digital Display Interface

[29] [29] [29]

PCH_ENBKL

LVDS

PCH_ENBKL PCH_ENVDD

CRT

[29] [29]

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

Issued Date

Deciphered Date

2012/07/12

Title

PCH (4/9) LVDS,CRT,DP,HDMI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Sherry and Royal Thursday, February 02, 2012

Rev 0.1 Sheet E

16

of

55

A

B

C

R409 8 7 6 5

1 2 3 4

PCH_GPIO2 PCH_GPIO3 PCH_GPIO4 PXS_PWREN_R

8.2K_1206_8P4R_5% R408 1

2 8.2K_0402_5%

PCH_GPIO51

R418 1

2 8.2K_0402_5%

PCH_WL_OFF#

R432 1

2 8.2K_0402_5%

PCH_GPIO53

R433 1

2 8.2K_0402_5%

PCH_GPIO52

R401 1

2 8.2K_0402_5%

PCH_GPIO5

B21 M20 AY16 BG46

+3VS

R66

1

2 8.2K_0402_5%

1 R41 @

2 8.2K_0402_5%

DGPU_HOLD_RST#_R

[39]

USB3_RX2_N

USB3_RX2_N

[39]

USB3_RX2_P

USB3_RX2_P

USB3.0 [39]

USB3_TX2_N

[39]

USB3_TX2_P

USB3_TX2_N

Boot BIOS Strap GPIO19 GPIO51 Boot BIOS Bit11 Bit10 Destination

Internal PH

0

1

1

0

PCI

1

1

SPI

0

0

LPC

*

USB3_TX2_P

無無

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCI Interrupt Requests

CR Check list 1.5 only use for GPIO No use PH +3VS [24,49] PXS_PWREN Only GPIO CR Check list 1.5 only use for GPIO function PH(Internal PH), GPIO PH +3VS

如如

[31]

R55

2

R57

2

1 0_0402_5% PX5@ DGPU_HOLD_RST#_R PCH_GPIO52 1 0_0402_5% PX5@ PXS_PWREN_R PCH_GPIO51 PCH_GPIO53 PCH_WL_OFF#

PCH_WL_OFF#

GPIO55 @

NV_ALE NV_CLE NV_RCOMP

BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

NV_RE#_WRB0 NV_RE#_WRB1 NV_WE#_CK0 NV_WE#_CK1

K40 K38 H38 G38 C46 C44 E40 D47 E42 F46

PCH_GPIO2 PCH_GPIO3 PCH_GPIO4 PCH_GPIO5

G42 G40 C42 D44

PCI_PME#

K10

2 1K_0402_5%

3

[37]

A16 swap overide Strap/Top-Block Swap Override jumper

[6]

Low=A16 swap override/Top-Block PCI_GNT3# Swap Override enabled High=Default *

[14]

CLK_PCI_LPBACK [37] CLK_PCI_EC [31] CLK_PCI_DB

CLK_PCI_LPBACK CLK_PCI_EC CLK_PCI_DB

PCI_PME#

PCH_PLTRST#

R417 2 R84 1 R340 1

PCH_PLTRST# 1 22_0402_5% 2 22_0402_5% 2 22_0402_5%

@

CLK_PCI0 CLK_PCI1 CLK_PCI2

C6 H49 H43 J48 K42 H40

PIRQA# PIRQB# PIRQC# PIRQD#

AT10 BC8 AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 AV5 AY1

1

DF_TVS

DMI,FDI Termination Voltage

AV10 AT8

DF_TVS

AY5 BA2

Set to Vcc when HIGH

HR CPU NC

Set to Vss when LOW

CR CPU PD

CR Check list P.89 PH 2.2K series 1K

AT12 BF3

+1.8VS

Reserved

DGPU_HOLD_RST#

1

TP21 TP22 TP23 TP24

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

NV_RB#

2

GNT1#/ GPIO51

NV_DQS0 NV_DQS1

AY7 AV7 AU3 BG4

REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

1

1

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

USB20_N1 USB20_P1 USB20_N2 USB20_P2

USB20_N1 USB20_P1 USB20_N2 USB20_P2

[39] [39] [31] [31]

Mini Card (WLAN) 2

DF_TVS

EHCI 1

R146

USBRBIAS

C33

1 1K_0402_5%

H_SNB_IVB#

[6]

CLOSE TO THE BRANCHING POINT HM70 not support USB port 4,5,6,7,12,13 USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11

USB20_N8 [38] USB20_P8 [38] USB20_N9 [38] USB20_P9 [38] USB20_N10 [38] USB20_P10 [38] USB20_N11 [29] USB20_P11 [29]

USB2 (Right side) +3V_PCH

USB2 (Right side) EHCI 2

CMOS Camera (LVDS)

USB_OC7#

0110 modify WLAN USB port to USB8 Port9 is for debug.

USBRBIAS

B33

1 R399

2 R24

1 10K_0402_5%

2 R367 2 R378

1 10K_0402_5% 1 10K_0402_5%

2 R377

1 10K_0402_5%

USB_OC0#

Card Reader

USB_OC5# USB_OC6#

USBRBIAS#

2

R145 2.2K_0402_5%

USB3 (Left side) 2

8.2K_1206_8P4R_5%

TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

NVRAM

PCI_PIRQC# PCI_PIRQB# PCI_PIRQA# PCI_PIRQD#

USB

1 2 3 4

PCI

8 7 6 5

RSVD

BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45

R90

R215

E

U13E

+3VS

PCH_WL_OFF#

D

2 22.6_0402_1%

L=500mil S=15mil

+3V_PCH

PME#

3

R349

PLTRST#

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

A14 K20 B17 C16 L16 A16 D14 C14

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

USB_OC0#

[39]

USB_OC4#

[38]

Card reader

4 3 2 1

USB_OC1# USB_OC4# USB_OC3# USB_OC2#

5 6 7 8

10K_1206_8P4R_5%

PANTHER_FCBGA989 @

R10 0_0402_5% 2 1

P

B

Y

4

PLT_RST#

[31,32,37]

1

A

R11 100K_0402_5%

MC74VHC1G08DFT2G_SC70-5 4

2

3

1

G

PCH_PLTRST#

5

+3VS

U25 @ 2

4

P Y

A

4

GPU_RST#

[22]

G

1

R6 0_0402_5% 2 1

Issued Date MC74VHC1G08DFT2G_SC70-5

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification 3

DGPU_HOLD_RST#

5

+3VS U29 PX@ 2 B

2011/06/24

Deciphered Date

2012/07/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B

C

D

Title

PCH (5/9) PCI, USB, NVRAM

Size Document Number Custom

Rev 0.1

Sherry and Royal

Date:

Thursday, February 02, 2012

Sheet E

17

of

55

A

B

C

D

E

+3VS

+3VS

1

1

HDA_SYNC PH(PLL =+1.5VS) +3VS

+3V_PCH

PCH_GPIO1

A42

PCH_GPIO6

H36

EC_SCI#

E38

EC_SMI#

C10

No use PH 10K +3VS No use PH 10K +3VS

[37]

EC_SCI#

No use PH 10K +3VALW

[37]

EC_SMI#

No use PH +3VALW[37]

1

1 10K_0402_5% 2 10K_0402_5%

@

PCH_GPIO27

EC_LID_OUT# @1 @

EC_LID_OUT#

No use PH +3VS

[31] 1

No use PH 10K +3VS

Blue Booth

[31]

No use PH +3VALW

DDR3

VGA_PWRGD

No use PH 10K +3VS

R261

1

@

2 1K_0402_5%

EC_SMI#

SATA2GP/GPIO36 & SATA3GP/GPIO37 Sampled at Rising edge of PWROK. Weak internal pull-down. (weak internal pull-down is disabled after PLTRST# de-asserts) NOTE: This signal should NOT be pulled high when strap is sampled

D40 T5

BT_DISABLE

BT_DISABLE

EC_LID_OUT#

BT ON/OFF

[31]

1

E8

2 PCH_GPIO27 R61 0_0402_5% PCH_GPIO28

PCH_BT_ON#

1

R243

No use can NC

U2

2 0_0402_5% VGA_PWRGD_R

No use PH 10K +3VALW

+3V_PCH

G2

PCH_GPIO24

No use PD 10K to GND

2

2 PCH_GPIO15 R60 0_0402_5% mSATA_DET#

mSATA_DET#

R45

[22,49]

C4

PCH_GPIO12

No use PH +3VALW

DS3@

R83

1

0 1

2

PCH_GPIO71

USB3.0 by PCH USB3.0 by NEC

R43 200K_0402_5%

1

2 10K_0402_5%

E16 P8

PCH_BT_ON#

K1

PCH_GPIO35

K4

Can't PH

PCH_GPIO36

V8

Can't PH

PCH_GPIO37

M5

OPTIMUS_EN#

N2

No use PH 10K +3VS

Optimus(L)/ non optimus(H)

No use PH 10K +3VS

PCH_GPIO39

M3

No use PH 10K +3VS

PCH_GPIO48

V13

SATA5GP&TEMP_ALERT# CRB PH 10K +3VS

PCH_GPIO49

V3

No use PH +3VALW

PCH_GPIO57

D6

A4 UMA@

R427

+3VS

1

2 10K_0402_5%

OPTIMUS_EN#

PX@ 1

2 10K_0402_5%

PCH_GPIO0

R402

1

2 10K_0402_5%

PCH_GPIO1

R70

1

2 10K_0402_5%

PCH_GPIO6

R426

1

2 10K_0402_5%

3

R419

1

2 10K_0402_5%

PCH_GPIO39

R97

1

2 10K_0402_5%

BT_DISABLE

R416

1

2 10K_0402_5%

PCH_BT_ON#

R128

1

2 10K_0402_5%

PCH_GPIO48

R111

1

2 10K_0402_5%

PCH_GPIO49

*

+3VS

R412

1

2 1K_0402_5%

PCH_GPIO15

R52

1

2 10K_0402_5%

PCH_GPIO57

R92

1

2 10K_0402_5%

PCH_GPIO24

A6 B3

0 1

B47 BD1

+3VS BE49

2 PCH_GPIO12

Muxless nonMuxless

R244 10K_0402_5% @ PCH_GPIO37

1

2 10K_0402_5%

A5

BE1

TACH6 / GPIO70

TACH3 / GPIO7

TACH7 / GPIO71

BF1 R245 10K_0402_5% @ PCH_GPIO36

BF49

PCH_GPIO68

B41

PCH_GPIO69

C41

PCH_GPIO70

A40

PCH_GPIO71

Need? +3VS

R106 10K_0402_5%

GPIO8 LAN_PHY_PWR_CTRL / GPIO12 GPIO15

A20GATE

SATA4GP / GPIO16 TACH0 / GPIO17 SCLOCK / GPIO22 GPIO24 / MEM_LED

PECI RCIN# PROCPWRGD THRMTRIP# INIT3_3V#

P4

GATEA20

AU16

PCH_PECI_R

P5

EC_KBRST#

1 2 @ 0_0402_5% R158

AY11 AY10

NC_1 STP_PCI# / GPIO34 NC_2 GPIO35 NC_3 SATA2GP / GPIO36 NC_4 SATA3GP / GPIO37 NC_5

[37,6]

KBRST#

[37]

H_CPUPWRGD PCH_THRMTRIP#_R 1 R159

[37]

PECI CPU-EC CTRL+ALT+DEL non CPU power ok

[6]

2 H_THERMTRIP# 390_0402_5%

H_THERMTRIP#

[6]

130c shut down

T14

INIT3_3V

GPIO27 GPIO28

H_PECI

Checklist1.5 P.69 +3VS

This signal has weak internal PU, can't pull low,leave NC

AH8 AK11 AH10

TS_VSS1~4 PD to GND

AK10

EC_KBRST#

R103

1

2 10K_0402_5%

PCH_GPIO68

R400

1

2 10K_0402_5%

2

P37

SLOAD / GPIO38 SDATAOUT0 / GPIO39 SDATAOUT1 / GPIO48

VSS_NCTF_15

SATA5GP / GPIO49

VSS_NCTF_16

GPIO57

VSS_NCTF_17

VSS_NCTF_1

VSS_NCTF_19

VSS_NCTF_2

VSS_NCTF_20

VSS_NCTF_3

VSS_NCTF_21

VSS_NCTF_4 VSS_NCTF_5

VSS_NCTF_22 VSS_NCTF_23

VSS_NCTF_6

VSS_NCTF_24

VSS_NCTF_7

VSS_NCTF_25

VSS_NCTF_8

VSS_NCTF_26

VSS_NCTF_9

VSS_NCTF_27

VSS_NCTF_10

VSS_NCTF_28

VSS_NCTF_11

VSS_NCTF_29

VSS_NCTF_12

VSS_NCTF_30

VSS_NCTF_13

VSS_NCTF_31

VSS_NCTF_14

VSS_NCTF_32

BG2 BG48 BH3 BH47 BJ4

9/15 Layout request remove Test point They will route by itself

BJ44 BJ45 BJ46 BJ5 3

BJ6 C2 C48 D1 D49 E1 E49 F1 F49

PANTHER_FCBGA989

R881 10K_0402_5% 2

1

A46

BD49

+3V_PCH

R376

A45

1

VGA_PWRGD_R

A44

9/15 Layout request remove Test point They will route by itself

OPTIMUS_EN#

2

MSATA_DET#

2 10K_0402_5%

TACH2 / GPIO6

C40

1

2 10K_0402_5%

1

TACH5 / GPIO69

R552 10K_0402_5% 2

1

R71

GPIO38

1

R115

TACH4 / GPIO68

TACH1 / GPIO1

VSS_NCTF_18 +3VS

R112

BMBUSY# / GPIO0

2

No use PH 10K +3VS

No use PH +3VS

For DS3 2

R68 10K_0402_5% @

1

T7

CPU/MISC

PCH_GPIO0

GPIO

Deep S4,S5 wake event signal RTC alarm,Power BTN,GPIO27 PCH_GPIO27 (Have internal Pull-High) Deep S4,S5 wake event signal

No use PH 10K +3VS

NCTF

2 1

Debug Port DG 1.2 PH 4.7K +3VALW_PCH

R208

13/14" NA

U13F

R413 1K_0402_5%

+3VALW

0 1

1

PCH_GPIO28

@

Function

PCH_GPIO71

R44 200K_0402_5%

1

R411 10K_0402_5% 2

R42 @ 10K_0402_5%

Fan Tachometer Inputs TACH1~7 only on server can insted to GPIO

1

1

PCH_GPIO70

PCH_GPIO70

2

PCH_GPIO69

R69 10K_0402_5%@

2

H On-Die PLL voltage regulator enable L On-Die PLL Voltage Regulator disable

2

*

2

R67 @ 10K_0402_5%

：：

This signal has a weak internal pull up

2

On-Die PLL Voltage Regulator

1

GPIO28

For DDR3L control 4

[46]

DDR3L_EN#

R63 @ 1

0_0402_5% 2 PCH_GPIO24

GPIO24 Unmultiplexed NOTE: GPIO24 configuration register bits are not cleared by CF9h reset event. CRB1.0 PH10K to +3VALW

GPIO36/GPIO37 is Strap functionality that requires internal pull down to be sampled at rising PWROK. When uses as SATA2GP/SATA3GP for mechanical presence detect -use a external pull up 150K-200K ohm to Vcc3_3 When used as GP input -ensure GPI is not driven high during strap sampling window When Unused as GPIO or SATA*GP -use 8.2K-10K pull-down check list page 47

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

2012/07/12

Deciphered Date

Title

PCH (6/9) GPIO, CPU, MISC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

A

B

C

D

Thursday, February 02, 2012

Sheet E

18

of

55

A

B

C

D

E

Thermal Senser share with VCCADAC power rail so can't remove this power

POWER

1300mA

2

Place Near AA23

VCCADAC

CRT

VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15] VCCCORE[16] VCCCORE[17]

VSSADAC

1

C53

1

VCCALVDS VSSALVDS

VCCTX_LVDS[1] VCCTX_LVDS[2]

60mA VCCTX_LVDS[3]

0.01U_0402_16V7K 0.1U_0402_16V7K 2 2

VCCTX_LVDS[4]

AK36

AN17 AN21 AN26 AN27

+1.05VS_VTT

AP21

2

AP23

2

AP26 AT24 AN33

Place Near AN16,AN21,AN33

AN34

+3VS BH29 1

Place Near BH29

C107 0.1U_0402_16V7K

AP16 @ T17

+1.05VS_VCCAPLL_FDI

BG6

1

2925mA

VCC3_3[6]

0_0603_5%

AM37 AM38

Place Near AM37

AP36

1

AP37

1

2

AU20 C98 1U_0402_6.3V6K

C92 0.01U_0402_16V7K

C108 22U_0603_6.3V6K

0.01U_0402_16V7K V33

Place Near V33

V34

I/O Buffer Voltage

C61 0.1U_0402_16V7K

2

VCCVRM[3]

AT16

VCCIO[21]

VCCIO[23] VCCIO[24]

Internal PLL and VRM(+1.5VS)

+1.05VS_VTT

VCCIO[20]

VCCIO[22]

PCH Power Rail Table

+1.5VS

VCCIO[18] VCCIO[19]

VCCDMI[1]

20mA

VCCIO[1]

AT20 1 AB36

DMI buffer logic

C96 1U_0402_6.3V6K

2

place near AT20

Core Well I/O Buffer

190mA

VCCIO[25] VCCIO[26]

VCCPNAND[1]

VCC3_3[3]

VCCVRM[2] VCCFDIPLL

VCCPNAND[2] VCCPNAND[3]

AG16 +1.8VS

VccDFTERM should PH +1.8VS or +3VS

AG17 1 AJ16 2

VCCPNAND[4]

VCCIO[27] VCCDMI[2]

20mA

VCCSPI

+1.8VS

0.1uH inductor, 200mA

VCCIO[17]

PANTHER_FCBGA989

Near AU20

L27 0.1UH_MLF1608DR10KT_10%_1608 2 1

+3VS

AJ17

Voltage

S0 Iccmax Current(A)

V_PROC_IO

1.05

0.001

Processor I/F

V5REF

5

0.001

PCH Core Well Reference Voltage

V5REF_Sus

5

0.001

Suspend Well Reference Voltag

Vcc3_3

3.3

0.266

I/O Buffer Voltage

VccADAC

3.3

0.001

Display DAC Analog Power. This power is supplied by the core well.

2

VccADPLLA

1.05

0.08

Display PLL A power

VccADPLLB

1.05

0.08

Display PLL B power

place near AG16

VccCore

1.05

1.3

Internal Logic Voltage

V1

For SPI control logi 1

2

Voltage Rail

C81 0.1U_0402_16V7K

+3VS

3

2

+VCCTX_LVDS

1 C91

1 VCC3_3[7]

1

2

R442

+1.05VS_VTT AP17

On-Die PLL Voltage Regulator

VCCIO[16]

+1.5VS

2

PAD

VCCIO[15]

FDI

2

1

C86 1U_0402_6.3V6K

2

1

C90 1U_0402_6.3V6K

2

1

C88 1U_0402_6.3V6K

1

C87 1U_0402_6.3V6K

2

C80 10U_0603_6.3V6M

1

AP24

HVCMOS

H On-Die PLL voltage regulator enable VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

C40 10U_0603_6.3V6M

AK37

266mA

VCCAPLLEXP

DMI

：

AN16

NAND / SPI

On-Die PLL Voltage Regulator

+3VS

2

+VCCA_LVDS

VCCIO[28]

VCCIO

+VCCAPLLEXP BJ22

T31 @

1

C54

U47

2 PAD

L16 MBK1608221YZF_2P 2 1

Place Near U48

+VCCADAC

1mA

1mA

+1.05VS_VTT AN19

U48

+3VS

LVDS

2

1

C75 1U_0402_6.3V6K

2

1

C67 1U_0402_6.3V6K

1

C64 1U_0402_6.3V6K

2

1

C106 10U_0603_6.3V6M

1

VCC CORE

AA23 AC23 AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26 AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31

+1.05VS_VTT

1

U13G

2

+1.05VS_VTT

C60 1U_0402_6.3V6K

VccDMI

1.05

0.042

DMI Buffer Voltage

VccIO

1.05

2.925

Core Well I/O buffers

VccASW

1.05

1.01

1.05 V Supply for Intel R Management Engine and Integrated LAN

VccSPI

3.3

0.02

3.3 V Supply for SPI Controller Logic

VccDSW

3.3

0.003

3.3v supply for Deep S4/S5 well

VccpNAND

1.8

0.19

1.8V power supply for DF_TVS

VccRTC

3.3

6 uA

Battery Voltage

VccSus3_3

3.3

0.266

Suspend Well I/O Buffer Voltage

3



Trace 20mil

：

H On-Die PLL voltage regulator enable VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

4

3.3 / 1.5

0.01

VccVRM

1.8 / 1.5

0.16

High Definition Audio Controller Suspend Voltage 1.8 V Internal PLL and VRMs (1.8 V for Desktop)

VccCLKDMI

1.05

0.02

DMI Clock Buffer Voltage

VccSSC

1.05

0.095

Spread Modulators Power Supply

VccDIFFCLKN

1.05

0.055

Differential Clock Buffers Power Supply

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

Analog power supply for LVDS (Mobile Only) Analog power supply for LVDS (Mobile Only)

2011/06/24

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification Issued Date

VccSusHDA

2012/07/12

Deciphered Date

Title

PCH (7/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

A

B

C

D

Thursday, February 02, 2012

Sheet E

19

of

55

B

AL29

+1.05VS_VTT R407 0_0603_5% 2 1

PAD

+VCCSUS1 AL24

T15 @

+VCCDSW3_3

AA19 +1.05VS_VTT

AA21 AA24

AA27 AA29 AA31

1 1

2

2

C66 1U_0402_6.3V6K

2

Near BF47

1

C73 1U_0402_6.3V6K

2 1

C187 22U_0805_6.3V6M

2

C104 1U_0402_6.3V6K

2

C112 220U_B2_2.5VM_R35

+

1

AA26

AC26 1

+1.05VS_VCCA_B_DPL

1

2

1 2 1 R301 0_0603_5%

2

2

Near BD47

C56 1U_0402_6.3V6K

1 2 L26 10UH_LB2012T100MR_20%

1

C110 22U_0603_6.3V6K

2 2

@

C103 1U_0402_6.3V6K

+

C118 220U_B2_2.5VM_R35

1

C113 22U_0603_6.3V6K

+1.05VS_VCCA_A_DPL

AC27 AC29 AC31 AD29 AD31

Near AA19

W21 W23 W24 W26 W29 W31 W33

Near M6 1 0.1U_0402_16V7K

N16

+VCCRTCEXT

119mA

VCCAPLLDMI2 VCCIO[14] DCPSUS[3]

VCCASW[1] VCCASW[2]

Y49

+1.05VS_VCCA_A_DPL

BD47

+1.05VS_VCCA_B_DPL

BF47 AF17 AF33 AF34 AG34

+1.05VS_VTT

1mA

VCCASW[3] VCCASW[4] VCCASW[5] VCCASW[6] VCCASW[7] VCCASW[8] VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14] VCCASW[15]

VCCSUS3_3[1]

+1.05VS_VTT

1mA

2

Near V16

C57

2 PAD

1 +VCCSST 0.1U_0402_16V7K

V16

+1.05VM_VCCSUS T17 V19

T13 @

VCCASW[19]

2

1

2

2

1

2

C453 0.1U_0402_16V7K

Place near BJ8

1

C450 0.1U_0402_16V7K

2

Near T23

2

V24

1

C46 0.1U_0402_16V7K

C45 0.1U_0402_16V7K

2

Near T24

+3V_PCH

P24 +1.05VS_VTT

+5V_PCH

D23 RB751V-40_SOD323-2

T26

R348 100_0402_5%

Near M26 M26

+PCH_V5REF_SUS

AN23

+VCCA_USBSUS

AN24

@

1 2 C37 0.1U_0402_16V7K

T16 PAD

suppied by internal 1.05V VR Must NC

+3V_PCH

VCCSUS3_3[4] VCCSUS3_3[5] VCC3_3[1] VCC3_3[8]

P34

+3VS

+5VS

D29

R130 100_0402_5%

+PCH_V5REF_RUN

+3V_PCH

2

N20 1

N22 P20

C38 1U_0402_6.3V6K

2

C42 1U_0402_6.3V6K

Near P34

Near N20

P22

+3VS

AA16 1

W16 T34

C471 0.1U_0402_16V7K

2 Place near AJ2

1

C62 0.1U_0402_16V7K

2 Place near AA16,W16

VCC3_3[2]

1

C49 0.1U_0402_16V7K

2 Place

near

T34

DCPRTC VCCVRM[4]

VCCIO[13]

80mA 80mA

VCCADPLLA VCCADPLLB

VCCIO[6] VCCAPLLSATA VCCVRM[1]

VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[11]

55mA

VCCIO[2]

VCCIO[10]

VCCIO[4]

95mA

AF13 1 AH13

VCCASW[22] VCCASW[23] VCCASW[21]

Near AH13,AH14,AF13 C76 1U_0402_6.3V6K

GPIO28

AF14 AK1

+VCCSATAPLL

@ T29

PAD

VCCRTC

PANTHER_FCBGA989

10mAVCCSUSHDA

：

H On-Die PLL voltage regulator enable VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

+1.05VS_VTT

AC16 AC17

3

On-Die PLL Voltage Regulator +1.5VS

AF11

Near AC16

AD17

1

C68 1U_0402_6.3V6K

2

+1.05VS_VTT

DCPSUS[1] DCPSUS[2]

1mA

2

AH14

DCPSST

V_PROC_IO

+1.05VS_VTT

AJ2

T21 V21 T19 +3V_PCH

A22 1

1

V23

+RTCBATT

C445 1U_0402_6.3V6K

C111 0.1U_0402_16V7K

1

C109 0.1U_0402_16V7K

isolation between SSC (AG33) and DIFFCLKN(AF33,AF34,AG34) 18mil width(DIFFCLKN) 10mil (SSC)

2

C114 4.7U_0603_6.3V6K

1

4

VCCSUS3_3[3]

VCCASW[20]

+1.05VS_VTT

BJ8

T24

VCCASW[18]

MISC

suppied by internal 1.05V VR Must NC

Place near AF33, AF34,AG34

AG33 1 C74 1U_0402_6.3V6K

+3V_PCH

T23

VCCASW[17]

HDA

2

V5REF

VCCSUS3_3[2]

VCCIO[3]

1 C72 1U_0402_6.3V6K

T29

RB751V-40_SOD323-2

VCC3_3[4]

CPU

Place near AG33

V5REF_SUS DCPSUS[4]

VCCASW[16]

RTC

1 C79 1U_0402_6.3V6K 2

VCCSUS3_3[10]

VCCIO[34]

SATA

Place near AG33

+1.05VS_VTT

Place near AF17

VCCSUS3_3[9]

1010mA

3

2

VCCSUS3_3[8]

VCCIO[12]

+1.5VS

1 C77 1U_0402_6.3V6K

VCCSUS3_3[7]

VCCIO[5]

2 C39

1

Near N26

VCC3_3[5]

VCCSUS3_3[6]

+1.05VS_VTT L25 @ 10UH_LB2012T100MR_20% 1 2

VCCIO[33]

C51 1U_0402_6.3V6K

2

T27

1

+3VALW

VCCIO[32]

P28

2

：

BH23

+VCCAPLL_CPY_PCH

T30 @

3mA DCPSUSBYP

1

P26

1

PAD

On-Die PLL Voltage Regulator H On-Die PLL voltage regulator enable VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

T38

+3VS_VCC_CLKF33

VCCIO[31]

1

suppied by internal 1.05V VR must NC

GPIO28

V12

+PCH_VCCDSW

T14 @

VCCIO[30] VCCDSW3_3

N26

2

PAD

T16

Near T16

VCCIO[29]

1

2

+1.05VS_VTT

VCCACLK

2

Near T38

Not support Deep S4,S5 connect to +3VALW

POWER

U13J

AD49

C47 0.1U_0402_16V7K

2

2

+VCCDSW3_3

1

PCI/GPIO/LPC

2

1

VCCDMI = 42mA detal waiting for newest spec

+VCCACLK

1

+3VS_VCC_CLKF33 1

C55 1U_0402_6.3V6K

1 C71 10U_0603_6.3V6M

E

VCC3_3 = 266mA detal waiting for newest spec

R430 @ 0_0603_5% 2 1

Clock and Miscellaneous

L23 10UH_LB2012T100MR_20% 1 2

D

+1.05VS_VTT

+1.05V analog internal clock PLL Can NC

USB

+3VS

C

2

A

Need +3VALW and 0.1U close PCH

P32 1



C41 0.1U_0402_16V4Z

4

2

Near P32

Near A22 Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

Deciphered Date

2012/07/12

Title

PCH (8/9) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

A

B

C

D

Thursday, February 02, 2012 E

Sheet

20

of

55

A

B

C

D

E

U13I

1

U13H H5 AA17 AA2 AA3 AA33 AA34 AB11 AB14 AB39 AB4 AB43 AB5 AB7 AC19 AC2 AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39 AD4 AD40 AD42 AD43 AD45 AD46 AD8 AE2 AE3 AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38 AF4 AF42 AF46 AF5 AF7 AF8 AG19 AG2 AG31 AG48 AH11 AH3 AH36 AH39 AH40 AH42 AH46 AH7 AJ19 AJ21 AJ24 AJ33 AJ34 AK12 AK3

2

3

VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79]

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

PANTHER_FCBGA989

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31 B35 B39 B7 F45 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38 BB4 BB46 BC14 BC18 BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46 BD5 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BD3 BF30 BF38 BF40 BF8 BG17 BG21 BG33 BG44 BG8 BH11 BH15 BH17 BH19 H10 BH27 BH31 BH33 BH35 BH39 BH43 BH7 D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42 D8 E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34 F3

VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258]

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

1

2

3

4

4

PANTHER_FCBGA989

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/24

2012/07/12

Deciphered Date

Title

PCH (9/9) VSS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

A

B

C

D

Thursday, February 02, 2012

Sheet E

21

of

55

5

[5]

PEG_HTX_C_GRX_P[15..0]

[5]

PEG_HTX_C_GRX_N[15..0]

4

PEG_HTX_GRX_P[15..0]

3

PEG_GTX_HRX_P[0..15]

U8A

PEG_HTX_GRX_N[15..0]

PEG_GTX_HRX_N[0..15]

2

PEG_GTX_HRX_P[0..15]

[5]

PEG_GTX_HRX_N[0..15]

[5]

1

U8F

LVDS CONTROL PEG_HTX_C_GRX_P15 AF30 PEG_HTX_C_GRX_N15AE31

PCIE_RX0P PCIE_RX0N

PCIE_TX0P PCIE_TX0N

PCIE_RX1P PCIE_RX1N

PCIE_TX1P PCIE_TX1N

PCIE_RX2P PCIE_RX2N

PCIE_TX2P PCIE_TX2N

AH30 AG31

PEG_GTX_HRX_P15 PEG_GTX_HRX_N15

AG29 AF28

PEG_GTX_HRX_P14 PEG_GTX_HRX_N14

AF27 AF26

PEG_GTX_HRX_P13 PEG_GTX_HRX_N13

AD27 AD26

PEG_GTX_HRX_P12 PEG_GTX_HRX_N12

AC25 AB25

PEG_GTX_HRX_P11 PEG_GTX_HRX_N11

Y23 Y24

PEG_GTX_HRX_P10 PEG_GTX_HRX_N10

AB27 AB26

PEG_GTX_HRX_P9 PEG_GTX_HRX_N9

Y27 Y26

PEG_GTX_HRX_P8 PEG_GTX_HRX_N8

W24 W23

PEG_GTX_HRX_P7 PEG_GTX_HRX_N7

V27 U26

PEG_GTX_HRX_P6 PEG_GTX_HRX_N6

U24 U23

PEG_GTX_HRX_P5 PEG_GTX_HRX_N5

T26 T27

PEG_GTX_HRX_P4 PEG_GTX_HRX_N4

T24 T23

PEG_GTX_HRX_P3 PEG_GTX_HRX_N3

P27 P26

PEG_GTX_HRX_P2 PEG_GTX_HRX_N2

P24 P23

PEG_GTX_HRX_P1 PEG_GTX_HRX_N1

M27 N26

PEG_GTX_HRX_P0 PEG_GTX_HRX_N0

VARY_BL DIGON

AB11 AB12

D

D

PEG_HTX_C_GRX_P14 AE29 PEG_HTX_C_GRX_N14 AD28 PEG_HTX_C_GRX_P13 AD30 PEG_HTX_C_GRX_N13 AC31 PEG_HTX_C_GRX_P12 AC29 PEG_HTX_C_GRX_N12 AB28

PEG_HTX_C_GRX_P10 AA29 PEG_HTX_C_GRX_N10 Y28 PEG_HTX_C_GRX_P9 Y30 PEG_HTX_C_GRX_N9 W31

PCIE_RX4P PCIE_RX4N PCIE_RX5P PCIE_RX5N PCIE_RX6P PCIE_RX6N

C

PEG_HTX_C_GRX_P8 W29 PEG_HTX_C_GRX_N8 V28 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_N7

V30 U31

PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_N6

U29 T28

PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_N5

T30 R31

PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_N4

R29 P28

PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3

P30 N31

B

PEG_HTX_C_GRX_P2 N29 PEG_HTX_C_GRX_N2 M28 PEG_HTX_C_GRX_P1 M30 PEG_HTX_C_GRX_N1 L31 PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0

L29 K30

PCIE_RX7P PCIE_RX7N PCIE_RX8P PCIE_RX8N PCIE_RX9P PCIE_RX9N PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_RX12P PCIE_RX12N

PCIE_TX3P PCIE_TX3N

PCI EXPRESS INTERFACE

PEG_HTX_C_GRX_P11 AB30 PEG_HTX_C_GRX_N11 AA31

PCIE_RX3P PCIE_RX3N

PCIE_TX4P PCIE_TX4N PCIE_TX5P PCIE_TX5N PCIE_TX6P PCIE_TX6N PCIE_TX7P PCIE_TX7N PCIE_TX8P PCIE_TX8N PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N PCIE_TX12P PCIE_TX12N

PCIE_RX13P PCIE_RX13N

PCIE_TX13P PCIE_TX13N

PCIE_RX14P PCIE_RX14N

PCIE_TX14P PCIE_TX14N

PCIE_RX15P PCIE_RX15N

PCIE_TX15P PCIE_TX15N

TXCLK_UP_DPF3P TXCLK_UN_DPF3N TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N TXOUT_U3P TXOUT_U3N

AH20 AJ19 AL21 AK20 AH22 AJ21 AL23 AK22 AK24 AJ23

LVTMDP TXCLK_LP_DPE3P TXCLK_LN_DPE3N TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N TXOUT_L3P TXOUT_L3N

AL15 AK14 AH16 AJ15

C

AL17 AK16 AH18 AJ17 AL19 AK18

216-0774207-A11ROB_FCBGA631 PX@

LVDS B

CLOCK [14] [14] [18,49]

CLK_PCIE_VGA CLK_PCIE_VGA#

CLK_PCIE_VGA CLK_PCIE_VGA#

R222 2 @

VGA_PWRGD

AK30 AK32

PCIE_REFCLKP PCIE_REFCLKN

0_0402_5% 1

CALIBRATION PCIE_CALRP

2 R299PX@1 10K_0402_5%

A

[17]

GPU_RST#

GPU_RST#

N10 AL27

PWRGOOD

PCIE_CALRN

PERSTB

PX@ Y22 1.27K_0402_1% 1

2 R298

AA22

2 R300

2K_0402_1% 1 PX@

+1.0VGS

PCIE LANE PX@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

216-0774207-A11ROB_FCBGA631

A

2010/07/12

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SeymourXT-S3 PCIE/LVDS Document Number Thursday, February 02, 2012

Rev 0.1 Sheet 1

22

of

55

5

4

3

2

1

U8B

Y11 AE9 L9 N9

+1.8VGS

+DPC_VDD18

1

1

@

2

C306 0.1U_0402_10V6K

@

+DPC_VDD18 C305 1U_0402_6.3V4Z

L8 2 1 BLM15BD121SN1D_0402 PX@

C304 10U_0603_6.3V6M

D

AE8 AD9 AC10 AD7 AC8 AC7 AB9 AB8 AB7 AB4 AB2 Y8 Y7

1

@

2

[27] [27] [27]

2

VRAM_ID2 VRAM_ID1 VRAM_ID0

VRAM_ID2 VRAM_ID1 VRAM_ID0

TXCAP_DPA3P TXCAM_DPA3N DVCLK DVCNTL_0 DVCNTL_1 DVCNTL_2

DVO

TX0P_DPA2P TX0M_DPA2N

DPA

TX1P_DPA1P TX1M_DPA1N

DVDATA_12 DVDATA_11 DVDATA_10 DVDATA_9 DVDATA_8 DVDATA_7 DVDATA_6 DVDATA_5 DVDATA_4 DVDATA_3 DVDATA_2 DVDATA_1 DVDATA_0

TX2P_DPA0P TX2M_DPA0N TXCBP_DPB3P TXCBM_DPB3N TX3P_DPB2P TX3M_DPB2N

DPB

TX4P_DPB1P TX4M_DPB1N TX5P_DPB0P TX5M_DPB0N

+1.0VGS

+DPC_VDD18

+DPC_VDD18

W6 V6

+DPC_VDD18

+DPC_VDD18

AC6 AC5

+DPC_VDD10

+DPC_VDD10

AA5 AA6

+DPC_VDD10 L9

1

1

@

2

C347 0.1U_0402_10V6K

C346 1U_0402_6.3V4Z

@

+DPC_VDD10 C307 10U_0603_6.3V6M

2 1 BLM15BD121SN1D_0402 PX@

1

@

2

AG3 AG5 AH3 AH1 AK3 AK1 AK5 AM3

D

AK6 AM5 AJ7 AH6 AK8 AL7

DPC

DPC_PVDD DPC_PVSS

TXCCP_DPC3P TXCCM_DPC3N

DPC_VDD18#1 DPC_VDD18#2

TX0P_DPC2P TX0M_DPC2N

DPC_VDD10#1 DPC_VDD10#2

TX1P_DPC1P TX1M_DPC1N

2

U1 W1 U3 Y6 AA1

AF2 AF4

DPC_VSSR#1 DPC_VSSR#2 DPC_VSSR#3 DPC_VSSR#4 DPC_VSSR#5

TX2P_DPC0P TX2M_DPC0N DPC_CALR

V4 U5 W3 V2 Y4 W5 AA3 Y2 J8

1 R307 2 150_0402_1% PX@

I2C SCL SDA

L6 GPIO24_TRSTB L5 GPIO25_TDI L3 GPIO26_TCK L1 GPIO27_TMS K4 T64 GPIO28_TDO 1R326 2 TEST_EN K7 AF24 PX@ 5.11K_0402_1% T65 AB13 W8 W9 W7 AD10

+DPLL_PVDD L14 C324 1U_0402_6.3V4Z

1

PX@

C325 0.1U_0402_10V6K

+DPLL_PVDD C323 10U_0603_6.3V6M

2 1 BLM15BD121SN1D_0402 PX@

1

PX@

2

1

PX@

2

AC14 AB16

1 2 R613 4.7K_0402_5%

R2 R2B G2 G2B B2 B2B C Y COMP H2SYNC V2SYNC VDD2DI VSS2DI

HPD1 PX_EN

A2VDD A2VDDQ

+1.8VGS +1.0VGS

+DPLL_VDDC

PX@

1

PX@

2

2

C332 0.1U_0402_10V6K

C331 1U_0402_6.3V4Z

C330 10U_0603_6.3V6M

+DPLL_VDDC 1

1

PX@

A2VSSQ 1499_0402_1%

+DPLL_PVDD

+DPLL_VDDC

AF14 AE14

+DPLL_VDDC

AD14

XTALIN XTALOUT

PX@

A

1

2

2

PX@

C336 0.1U_0402_16V4Z

C335 1U_0402_6.3V4Z

C334 10U_0603_6.3V6M 1

PX@

PX@ 2 R335 2 R333 PX@

1

2

10_0402_5% 10_0402_5%

AM28 AK28 AC22 AB22

DPLL_PVDD DPLL_PVSS

DDC1CLK DDC1DATA AUX1P AUX1N

DPLL_VDDC

DDC2CLK DDC2DATA

XTALIN XTALOUT

AUX2P AUX2N

XO_IN XO_IN2

DDCCLK_AUX3P DDCDATA_AUX3N DDCCLK_AUX5P DDCDATA_AUX5N

PX@ T4 T2 R334

1 R337

2 10M_0402_5%

+3VGS +TSVDD

AE23 +VDD1DI AD23

2

C400 1U_0402_6.3V4Z

PX@

1

PX@

2

1

PX@

PX@

2

AM12 AK12

+1.8VGS

+VDD1DI

AL11 AJ11

1

AK10 AL9

PX@

2

1

2

1

PX@

PX@ 2.61K_0402_5% 1 2 +TSVDD

R5 AD17 AC17

PX@

DPLUS DMINUS

GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 GPU_GPIO5

R339 R338 R325 R320

2 @ 2 PX@ 2 PX@ 2 PX@

1 1 1 1

GPU_GPIO8 GPU_GPIO9

R313 R314

2 2

GPU_GPIO11 R315 GPU_GPIO12 R316 GPU_GPIO13 R317

+VDD1DI

VGA_HSYNC VGA_VSYNC

L11 1 2 BLM15BD121SN1D_0402 PX@

2

R548 R549

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

@ @

1 10K_0402_5% 1 10K_0402_5%

2 PX@ 2 @ 2 @

1 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5%

1 @ 1 @

2 10K_0402_5% 2 10K_0402_5%

PX@

AH12 AM10 AJ9 AL13 AJ13

T53 T54

THERMAL

DDC6CLK DDC6DATA

B

+3VGS

AD19 AC19 AE20

R327 10K_0402_5%

+3VGS R328 10K_0402_5%

AE17 AE19 VGA_SMB_CK2_R AG13 1 R330 2 715_0402_1%

1 PX@ Q64A 2N7002DW-T/R7_SOT363-6

6

4

VGA_SMB_DA2_R

@ DDC/AUX PLL/CLOCK +DPLL_PVDD

+TSVDD +TSVDD

1

PX@ 1 R318 2 499_0402_1% +AVDD +AVDD

+3VGS

PX@

VREFG R2SET

2

+1.8VGS L17 2 1 BLM18AG121SN1D_0603

AC16

+VREFG_GPU

2 R332 1249_0402_1% PX@ 2 1 C322 0.1U_0402_10V6K PX@

L49 2 1 BLM15BD121SN1D_0402 PX@

PX@ 2 R329

AG24 AE22

+1.8VGS L10 1 2 BLM15BD121SN1D_0402

+AVDD

DAC2

@

2

AD22

+AVDD

+VDD1DI

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO TESTEN TESTEN_LEGACY GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4

VGA_HSYNC VGA_VSYNC

PX@

AE6 AE5

EC_SMB_CK2

[14,34,37]

EC_SMB_DA2

[14,34,37]

5

+1.8VGS B

PEG_CLKREQ#

GPIO24_TRSTB GPIO25_TDI GPIO27_TMS GPIO26_TCK

T57

AH26 AJ27

2

2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5%

R321 R322 R323 R324

VDD1DI VSS1DI

0117 AMD request to stuff R320

AH24 AG25

1

1 1 1 1

AVDD AVSSQ

C

2

PX@ PX@ PX@ PX@

RSET

T56

1

[14]

+3VGS

GPU_VID1

HSYNC VSYNC

T55

AL25 AJ25

2

[49]

GPU_VID0

B BB

DAC1

AM26 AK26

C401 10U_0603_6.3V6M

[49]

G GB

C315 10U_0603_6.3V6M

1

ACIN

GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16_SSIN GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB

C396 1U_0402_6.3V4Z

D4

CH751H-40PT_SOD323-2 [15,37,43]

U6 U10 T10 U8 U7 @ 2 T9 T8 T7 P10 GPU_GPIO8 P4 GPU_GPIO9 P2 N6 GPU_GPIO11 N5 GPU_GPIO12 N3 GPU_GPIO13 Y9 N1 GPU_VID0 M4 T63 R6 W10 PX@ 2 M2 R319 1 10K_0402_5% P8 GPU_VID1 P7 T70 N8 N7 PEG_CLKREQ# GPU_GPIO0 GPU_GPIO1 GPU_GPIO2 VGA_SMB_DA2_R VGA_SMB_CK2_R GPU_GPIO5

C397 0.1U_0402_10V6K

R RB

GENERAL PURPOSE I/O

C

C313 0.1U_0402_10V6K

R1 R3

3

Q64B 2N7002DW-T/R7_SOT363-6

AD2 AD4

PX@

AC11 AC13 AD13 AD11 AD20 AC20 AE16 AD16 AC1 AC3

T58 T59 A

TS_FDO TSVDD TSVSS

Y6 4 XTALIN

1

NC OSC

3

OSC

XTALOUT 216-0774207-A11ROB_FCBGA631

2

NC

2 27MHZ 16PF +-30PPM X3G027000FG1H-HX PX@ PX@ C341 15P_0402_50V8J 1

1

Issued Date

PX@ C350 15P_0402_50V8J

Compal Electronics, Inc.

Compal Secret Data

Security Classification

PX@ 2

2010/07/12

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

SeymourXT-S3 Main Generic/MSIC Size C Date:

5

4

3

2

Document Number

Rev 0.1

Thursday, February 02, 2012

Sheet 1

23

of

55

5

4

3

2

1

[email protected], in BACO mode

D

+BIF_VDDC

D

+VGA_CORE

1 R398

2 0_0805_5%

2

1

PX@

2

1

2

R270

@ Q36

2 51K_0402_5% PX@

S 2N7002K_SOT23-3

PXS_PWREN

1 PX@ R271 PX@R271 0_0402_5% D

1

Q30 PX@ S 2N7002K_SOT23-3

2

2 G

1 1

2 PXS_PWREN#1 @ R283 0_0402_5%

2 PXS_PWREN# Q26 DTC124EKAT146_SC59-3

2

D

S

@ Q35

2 G

C

1

470_0603_5%

2

Q27 PX@ AP2301GN-HF_SOT23-3

PX@

OUT

D

2 G

C1142 PX@ 0.1U_0402_25V6

+1.5V_IO

2

R263 100K_0402_5% @ R284

C345 PX@ 1U_0402_6.3V6K

1

1

PX@ C344 10U_0603_6.3V6M

3

3

470_0603_5%

1

1

1 3

Q32 PX@ S 2N7002K_SOT23-3

2 G

1

3

1 PXS_PWREN#1 @ R287 0_0402_5%

47K_0402_5% D

2MM

2

+5VALW

1R1451 PX@2

75K_0402_5%

10U_0603_6.3V6M

1

1

1

C1141 PX@ 1U_0402_6.3V6K

3

2

PXS_PWREN#

2

@ R290

4

R279

1 2 3

PX@ C1140 10U_0603_6.3V6M

1

2

+VSB

PX@

1

8 7 6 5

C

1

PX@ 1 C1139

2MM U15 PX@ AO4430L_SO8

2

@

2

2

1

+3VALW

+3VGS J2

1

2

PX@ C375 10U_0603_6.3V6M

+3VS

@

[17,49]

PXS_PWREN 2

PXS_PWREN

IN

2N7002K_SOT23-3 PX@

C1143 PX@ 0.1U_0402_16V4Z

GND

+1.8VGS J4 2

2

+1.8VS

+3.3VS TO +3.3VGS

3

+1.8VS TO +1.8VGS

C342 PX@ 22U_0603_6.3V6K

+1.5VGS J9 2

@ 1

2MM U12 PX@ AO4430L_SO8

2

4

2

1

+VSB

B

PX@ C1146 10U_0603_6.3V6M

@ R285 PXS_PWREN#1

1

1 2 3

2 2 G 0_0402_5% @ Q31 2N7002K_SOT23-3

PX@ R275 20K_0402_5%

@ R274 470_0603_5%

C1147 PX@ 1U_0402_6.3V6K 1 2

8 7 6 5

1

C1145 PX@

D

3

B

1

10U_0603_6.3V6M

2

+1.5V TO +1.5VGS

S

1

D

3

Q37 PX@ S 2N7002K_SOT23-3

R280 0_0402_5% @

PX@ 1

PXS_PWREN# 2 G

1

2 43K_0402_5%

C1149 PX@ 0.1U_0402_25V6

2

1

2

R278

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

SeymourXT_S3_BACO POWER Size C Date:

5

4

3

2

Document Number

Rev 0.1

Sherry and Royal Sheet

Thursday, February 02, 2012 1

24

of

55

5

4

2

+DPEF_VDD18

2

@

U8G

@

2

DP E/F POWER DPE_VDD18#1 DPE_VDD18#2

+DPEF_VDD10

1

MBK1608121YZF_0603 Change to 0 ohm P/N

@

2

1

@

2

1

@

AG14 AH14 AM14 AM16 AM18

2

DPA_VDD18#1 DPA_VDD18#2

DPE_VDD10#1 DPE_VDD10#2

DPA_VDD10#1 DPA_VDD10#2

DPE_VSSR#1 DPE_VSSR#2 DPE_VSSR#3 DPE_VSSR#4 DPE_VSSR#5

DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5

DPF_VDD18#1 DPF_VDD18#2

DPB_VDD18#1 DPB_VDD18#2

AF6 AF7

1

AE1 AE3 AG1 AG6 AH5

@

AE13 AF13

2

1

@

2

L21

+1.0VGS PX@

1

2

1

@

2

MBK1608121YZF_0603

Change to 0 ohm P/N

C

+DPAB_VDD10

110mA

AF22 AG22 AF23 AG23 AM20 AM22 AM24

AF17

DPF_VDD10#1 DPF_VDD10#2

DPB_VDD10#1 DPB_VDD10#2

DPF_VSSR#1 DPF_VSSR#2 DPF_VSSR#3 DPF_VSSR#4 DPF_VSSR#5

DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5

DPEF_CALR

DPAB_CALR

AF8 AF9

20mA

AG18 AF19

DPE_PVDD DPE_PVSS

AE10

20mA

DP PLL POWER

DPA_PVDD DPA_PVSS

+DPAB_VDD10

AF10 AG9 AH8 AM6 AM8

+DPEF_VDD18 AG8 AG7

+DPEF_VDD18

B

2

D

Change to 0 ohm P/N

+DPAB_VDD18

+DPEF_VDD10

+DPEF_VDD18

2

@

+DPAB_VDD18

130mA

AF16 AG17

R463 PX@ 2 1 150_0402_1%

@

L19

2 1 1 MBK1608121YZF_0603

total:220mA

+DPEF_VDD18

C

2

AE11 +DPAB_VDD18 AF11 +DPAB_VDD10

110mA

AG20 AG21

C361 0.1U_0402_10V6K

2

total:240mA@LVDS total:220mA@DP 1 C360 1U_0402_6.3V4Z

L20

C356 10U_0603_6.3V6M

PX@

DP A/B POWER

130mA

AG15 AG16

1

C359 10U_0603_6.3V6M

2

@

1

C364 10U_0603_6.3V6M

+1.0VGS

@

1

C358 1U_0402_6.3V4Z

Change to 0 ohm P/N

1

C357 0.1U_0402_10V6K

1

C362 0.1U_0402_10V6K

1

MBK1608121YZF_0603

1

+1.8VGS PX@

total:300mA

C355 0.1U_0402_10V6K

2 D

+DPAB_VDD18

total:440mA@LVDS total:300mA@DP C368 1U_0402_6.3V4Z

L18

C367 10U_0603_6.3V6M

PX@

C363 1U_0402_6.3V4Z

+1.8VGS

3

1 R464 2 150_0402_1% PX@

+DPAB_VDD18

+DPAB_VDD18 +DPAB_VDD18

+DPEF_VDD18

20mA

AG19 AF20

20mA DPF_PVDD DPF_PVSS

DPB_PVDD DPB_PVSS

AG10 AG11

B

+DPAB_VDD18

216-0774207-A11ROB_FCBGA631 PX@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2010/07/12

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SeymourXT-S3 DP PWR Document Number Thursday, February 02, 2012

Rev 0.1 Sheet 1

25

of

55

5

4

3

2

1

+1.5VGS

2

+PCIE_VDDR

1

PX@

L24

2

1

PX@

AA11 AA12

2

V11 U11

VDDR4#1 VDDR4#2 VDDR4#3 NC#1 NC#2 NC#3 NC#4

0120 change power rail to +PCIE_VDDR

2

C449 0.1U_0402_10V6K

AM30

B

PX@

75mA L8

+SPV18

75mA H7

1

+SPV10

120mAH8

2

+1.0VGS

J7 L28

1 2 BLM15BD121SN1D_0402

1

PX@

2

1

2

C384 10U_0603_6.3V6M

PX@

PX@

PX@

PX@

2

PX@

1

2

1

2

1

2

1

2

+VGA_CORE

11.8A(RMS)/12.9A(Peak)

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

PX@

PX@

PX@

PX@

1

2

2

1

2

1

2

1

2

M6 N11 N12 N13 N16 N18 N21 P6 P9 R12 R15 R17 R20 T13 T16 T18 T21 T6 U15 U17 U20 U9 V13 V16 V18 Y10 Y15 Y17 Y20 R11 T11

7/22 modify

NC_VDDRHA +BIF_VDDC

NC_VSSRHA

+VDDCIPX@

PX@

PX@

PX@

PX@

1

PCIE_PVDD BIF_VDDC#1 BIF_VDDC#2

R21 U21

2

NC_MPV18 SPV18 SPV10 SPVSS

1

ISOLATED CORE I/O

VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8

M13 M15 M16 M17 M18 M20 M21 N20

1

2

2

1

2

1

2

1

2

+VGA_CORE R745 0_0603_5% 1 2

PCIE_VSS#1 PCIE_VSS#2 PCIE_VSS#3 PCIE_VSS#4 PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31

GND#56 GND#57 GND#58 GND#59 GND#60 GND#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8 GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55

GND

VSS_MECH#1 VSS_MECH#2 VSS_MECH#3

A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6

C

A32 AM1 AM32

1

PX@

216-0774207-A11ROB_FCBGA631

2

PX@ B

216-0774207-A11ROB_FCBGA631 PX@

PX@

+1.0VGS PX@

PX@

1

PX@

PX@ PX@

+MPV18

AA27 AB24 AB32 AC24 AC26 AC27 AD25 AD32 AE27 AF32 AG27 AH32 K28 K32 L27 M32 N25 N27 P25 P32 R27 T25 T32 U25 U27 V32 W25 W26 W27 Y25 Y32

1920mA

PLL

For Seymour, PCIE_PVDD is PCIE_VDDR.

C458 0.1U_0402_10V6K

1

+PCIE_VDDR

2

C464 1U_0402_6.3V4Z

PX@

L16

C456 10U_0603_6.3V6M

2

2

L17

1

C463 0.1U_0402_10V6K

C462 10U_0603_6.3V6M

L48 PX@ 1 2 BLM15BD121SN1D_0402 1 PX@

C447 1U_0402_6.3V4Z

2

1

C454 1U_0402_6.3V4Z

C446 10U_0603_6.3V6M

MEM CLK 1

PX@

C430 0.1U_0402_10V6K

PX@

L47 1 2 BLM15BD121SN1D_0402

V12 Y12 U12

170mA 1

POWER

Change to PX@0 ohm P/N

C429 1U_0402_6.3V4Z

1 2 BLM15BD121SN1D_0402 C

VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4

D

C426 10U_0603_6.3V6M

AA17 AA18 AB17 AB18

60mA PX@

VDDC#1 VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8 VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23

CORE

I/O

PX@

2

C425 10U_0603_6.3V6M

2

AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 M11 M12

PX@

2

C420 1U_0402_6.3V4Z

2

@

VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4

PX@ L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

2

C419 1U_0402_6.3V4Z

PX@

LEVEL TRANSLATION AA20 AA21 AB20 AB21

17mA

1

2

C418 1U_0402_6.3V4Z

2

PX@

PX@

1

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

Change to 0 ohm P/N PX@

C417 1U_0402_6.3V4Z

1

C428 1U_0402_6.3V4Z

2

C410 1U_0402_6.3V4Z

2

PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8 PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12

+3VGS

1

C427 10U_0603_6.3V6M

2

1

C422 0.1U_0402_10V6K

1

Change PX@ to 0 ohm P/N

C405 1U_0402_6.3V4Z

110mA C404 10U_0603_6.3V6M

L46 1 2 BLM15BD121SN1D_0402

PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8

U8E

MBK1608121YZF_0603

1

C403 1U_0402_6.3V4Z

+VDDC_CT

VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17

1

C416 1U_0402_6.3V4Z

+1.8VGS

H13 H16 H19 J10 J23 J24 J9 K10 K23 K24 K9 L11 L12 L13 L20 L21 L22

1

C424 10U_0603_6.3V6M

PCIE

C423 10U_0603_6.3V6M

MEM I/O

C383 1U_0402_6.3V4Z

PX@

C415 1U_0402_6.3V4Z

PX@

C516 1U_0402_6.3V4Z

PX@

C461 1U_0402_6.3V4Z

PX@

C385 0.1U_0402_10V6K

PX@

C399 1U_0402_6.3V4Z

PX@

C398 1U_0402_6.3V4Z

PX@

C432 1U_0402_6.3V4Z

PX@

1

C431 1U_0402_6.3V4Z

PX@

C470 1U_0402_6.3V4Z

PX@

PX@

C460 1U_0402_6.3V4Z

PX@

9/28 Reserved for VGA_CORE 10/8 change to B2 size

L22 2

+PCIE_VDDR

C465 1U_0402_6.3V4Z

PX@

D

+1.8VGS

504mA U8D

C380 10U_0603_6.3V6M

2

C388 1U_0402_6.3V4Z

2

1

C466 10U_0603_6.3V6M

2

1

C387 1U_0402_6.3V4Z

2

1

C392 0.1U_0402_10V6K

2

1

C381 0.1U_0402_10V6K

2

1

C391 0.1U_0402_10V6K

2

1

C390 0.1U_0402_10V6K

2

1

C389 0.1U_0402_10V6K

2

1

C374 1U_0402_6.3V4Z

2

1

C373 1U_0402_6.3V4Z

2

1

C372 1U_0402_6.3V4Z

1

C371 1U_0402_6.3V4Z

1

C370 1U_0402_6.3V4Z

C369 10U_0603_6.3V6M

2

C366 10U_0603_6.3V6M

C365 10U_0603_6.3V6M

2.3A(RMS)/2.8A(Peak) 1

PX@

PX@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2010/07/12

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

SeymourXT-S3 PWR/GND Size C Date:

5

4

3

2

Document Number

Rev 0.1

Thursday, February 02, 2012

Sheet 1

26

of

55

5

[28] [28]

M_DA[63..0]

M_DA[63..0]

M_DQM[7..0]

M_DQM[7..0] M_DQS[7..0]

[28]

M_DQS#[7..0]

M_DQS[7..0] M_DQS#[7..0]

D

PARK SCL has different recommand

9/28 change P/N to SD034100A80R455

DRAM_RST#

2

10_0402_1% 1

DRAM_RST

1

[28]

1 R366 2 51.1_0402_1% PX@ C469 120P_0402_50V8J

1

PX@R456

4.99K_0402_1%

2

2 PX@

PX@

C

+1.5VGS

1

1

+1.5VGS

R365 40.2_0402_1%

2

2

R363 40.2_0402_1% +MVREFDA

+MVREFSA 1

PX@

1

1

C467 0.1U_0402_16V4Z

2

R457 100_0402_1% 2

2

PX@ R364 100_0402_1%

PX@

1

C514 0.1U_0402_16V4Z

2 PX@

PX@

2

PX@

B

+1.5VGS

M_DA0 M_DA1 M_DA2 M_DA3 M_DA4 M_DA5 M_DA6 M_DA7 M_DA8 M_DA9 M_DA10 M_DA11 M_DA12 M_DA13 M_DA14 M_DA15 M_DA16 M_DA17 M_DA18 M_DA19 M_DA20 M_DA21 M_DA22 M_DA23 M_DA24 M_DA25 M_DA26 M_DA27 M_DA28 M_DA29 M_DA30 M_DA31 M_DA32 M_DA33 M_DA34 M_DA35 M_DA36 M_DA37 M_DA38 M_DA39 M_DA40 M_DA41 M_DA42 M_DA43 M_DA44 M_DA45 M_DA46 M_DA47 M_DA48 M_DA49 M_DA50 M_DA51 M_DA52 M_DA53 M_DA54 M_DA55 M_DA56 M_DA57 M_DA58 M_DA59 M_DA60 M_DA61 M_DA62 M_DA63

K27 J29 H30 H32 G29 F28 F32 F30 C30 F27 A28 C28 E27 G26 D26 F25 A25 C25 E25 D24 E23 F23 D22 F21 E21 D20 F19 A19 D18 F17 A17 C17 E17 D16 F15 A15 D14 F13 A13 C13 E11 A11 C11 F11 A9 C9 F9 D8 E7 A7 C7 F7 A5 E5 C3 E1 G7 G6 G1 G3 J6 J1 J3 J5

+MVREFDA +MVREFSA

K26 J26

R458 1 PX@ R459 1 PX@

2 240_0402_1% J25 2 240_0402_1% K25

DQA0_0/DQA_0 DQA0_1/DQA_1 DQA0_2/DQA_2 DQA0_3/DQA_3 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31 DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63

GDDR5/DDR3 MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA0_6 MAA0_7/MAA0_7 MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_13/BA2 MAA1_6/MAA_14/BA0 MAA1_7/MAA_15/BA1 WCKA0_0/DQMA_0 WCKA0B_0/DQMA_1 WCKA0_1/DQMA_2 WCKA0B_1/DQMA_3 WCKA1_0/DQMA_4 WCKA1B_0/DQMA_5 WCKA1_1/DQMA_6 WCKA1B_1/DQMA_7 EDCA0_0/RDQSA_0 EDCA0_1/RDQSA_1 EDCA0_2/RDQSA_2 EDCA0_3/RDQSA_3 EDCA1_0/RDQSA_4 EDCA1_1/RDQSA_5 EDCA1_2/RDQSA_6 EDCA1_3/RDQSA_7 DDBIA0_0/WDQSA_0 DDBIA0_1/WDQSA_1 DDBIA0_2/WDQSA_2 DDBIA0_3/WDQSA_3 DDBIA1_0/WDQSA_4 DDBIA1_1/WDQSA_5 DDBIA1_2/WDQSA_6 DDBIA1_3/WDQSA_7 ADBIA0/ODTA0 ADBIA1/ODTA1 CLKA0 CLKA0B CLKA1 CLKA1B RASA0B RASA1B CASA0B CASA1B CSA0B_0 CSA0B_1 CSA1B_0 CSA1B_1

MVREFDA MVREFSA

CKEA0 CKEA1

MEM_CALRN0 MEM_CALRP0

WEA0B WEA1B

GDDR5 DRAM_RST L10 1R460@ 51.1_0402_1% 2 1 2 R373@ 51.1_0402_1%

[email protected]_0402_16V4Z 1 2 C517@ 0.1U_0402_16V4Z

K8 L7

1

+1.8VGS

GDDR5/DDR3 M_MA[13..0]

M_MA[13..0]

[28]

3

U8C

MEMORY INTERFACE

[28]

4

MAA1_8 MAA0_8

K17 J20 H23 G23 G24 H24 J19 K19 J14 K14 J11 J13 H11 G11 J16 L15

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_BA2 M_BA0 M_BA1

E32 E30 A21 C21 E13 D12 E3 F4

M_DQM0 M_DQM1 M_DQM2 M_DQM3 M_DQM4 M_DQM5 M_DQM6 M_DQM7

H28 C27 A23 E19 E15 D10 D6 G5

M_DQS0 M_DQS1 M_DQS2 M_DQS3 M_DQS4 M_DQS5 M_DQS6 M_DQS7

H27 A27 C23 C19 C15 E9 C5 H4

M_DQS#0 M_DQS#1 M_DQS#2 M_DQS#3 M_DQS#4 M_DQS#5 M_DQS#6 M_DQS#7

L18 K16

VRAM_ODT0 VRAM_ODT1

H26 H25

M_CLK0 M_CLK#0

G9 H9

M_CLK1 M_CLK#1

G22 G17

M_RAS#0 M_RAS#1

G19 G16

M_CAS#0 M_CAS#1

H22 J22

M_CS#0

G13 K13

M_CS#1

K20 J17

M_CKE0 M_CKE1

G25 H10

M_WE#0 M_WE#1

R461 R462 R359 R360 R361 R362

1 1 1 1 1 1

X76@ 2 X76@ 2 X76@ 2 X76@ 2 X76@ 2 X76@ 2

VRAM_ID0

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

VRAM_ID1 VRAM_ID2

VRAM_ID0

[23]

VRAM_ID1

[23]

VRAM_ID2

[23]

D

M_BA2 M_BA0 M_BA1

[28] [28] [28]

Vendor

VRAM_ID0

VRAM_ID1

VRAM_ID2

K4W1G1646G-BC11

64MX16 (512MB) Samsung 128MB

R461

PN:SA00004GS00

R360

1

R362 0

0

H5TQ1G63DFR-11C

64MX16 (512MB) Hynix 128MB

R462

PN:SA000041S20

R359

0

R362

1

0

K4W2G1646C-HC11

Samsung 256MB

128M16 (1GB)

R461

PN:SA000047Q00

R360

1

R361

0

1

H5TQ2G63BFR-11C/H5TQ2G63DFR-11C

Hynix 256MB

128M16 (1GB)

R462

PN:SA00003YO10/

R359

0

R361

1

C

1

SA00003YOA0

ZZZ

G14 G20

VRAM_ODT0 VRAM_ODT1

[28] [28]

M_CLK0 [28] M_CLK#0 [28]

Hynix

H1G@ X7639238L02

M_CLK1 [28] M_CLK#1 [28] M_RAS#0 M_RAS#1

[28] [28]

M_CAS#0 M_CAS#1

[28] [28]

M_CS#0

[28]

M_CS#1

[28]

M_CKE0 M_CKE1

[28] [28]

M_WE#0 M_WE#1

[28] [28]

B

M_MA13

DRAM_RST CLKTESTA CLKTESTB

A

A

Route 50ohms single-ended/100ohm diff and keep short debug only, for clock observation,if not

216-0774207-A11ROB_FCBGA631

Issued Date

Compal Electronics, Inc.

Compal Secret Data

SecurityPX@ Classification

need, DNI.

2010/07/12

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SeymourXT-S3 MEM Interface Document Number Thursday, February 02, 2012

Rev 0.1 Sheet 1

27

of

55

5

[27]

M_DQS[7..0]

[27]

M_DQS#[7..0]

M_MA[13..0] M_DQM[7..0] M_DQS[7..0] M_DQS#[7..0]

U19

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

[27]

[27] [27] [27]

M_BA0 M_BA1 M_BA2

[27] [27] [27]

M_CLK0 M_CLK#0 M_CKE0

M2 N8 M3

M_CLK0 M_CLK#0 M_CKE0

J7 K7 K9

C

M_DQS2 M_DQS0

F3 C7

M_DQM2 M_DQM0

E7 D3

M_DQS#2 M_DQS#0

G3 B7

ODT/ODT0 CS/CS0 RAS CAS WE

1

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

DQSL DQSU DML DMU

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DQSL DQSU

RESET ZQ/ZQ0

J1 L1 J9 L9

E3 F7 F2 F8 H3 H8 G2 H7

M_DA22 M_DA20 M_DA19 M_DA18 M_DA21 M_DA17 M_DA23 M_DA16

D7 C3 C8 C2 A7 A2 B8 A3

M_DA3 M_DA1 M_DA0 M_DA5 M_DA6 M_DA7 M_DA2 M_DA4

M8 H1

+VREFC_A2 +VREFD_Q2 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

2

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

PX@

B2 D9 G7 K2 K8 N1 N9 R1 R9

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

+1.5VGS

M_BA0 M_BA1 M_BA2

M2 N8 M3

M_CLK0 M_CLK#0 M_CKE0

J7 K7 K9

A1 A8 C1 C9 D2 E9 F1 H2 H9

VRAM_ODT0 K1 L2 M_CS#0 J3 M_RAS#0 K3 M_CAS#0 L3 M_WE#0 M_DQS3 M_DQS1

F3 C7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

M_DQM3 M_DQM1

E7 D3

M_DQS#3 M_DQS#1

G3 B7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

DQSL DQSU DML DMU

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DQSL DQSU

RESET ZQ/ZQ0

J1 L1 J9 L9

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

PX@

96-BALL SDRAM DDR3 H5TQ1G63DFR-11C

E3 F7 F2 F8 H3 H8 G2 H7

M_DA25 M_DA28 M_DA27 M_DA31 M_DA24 M_DA29 M_DA26 M_DA30

D7 C3 C8 C2 A7 A2 B8 A3

M_DA14 M_DA10 M_DA15 M_DA11 M_DA12 M_DA8 M_DA13 M_DA9

M8 H1

+VREFC_A3 +VREFD_Q3 M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

B2 D9 G7 K2 K8 N1 N9 R1 R9

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

[27] [27] [27]

+1.5VGS A1 A8 C1 C9 D2 E9 F1 H2 H9

[27]

M_CLK1 M_CLK#1 M_CKE1

M_BA0 M_BA1 M_BA2

M2 N8 M3

M_CLK1 M_CLK#1 M_CKE1

J7 K7 K9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

M_DQS4 M_DQS5

F3 C7

M_DQM4 M_DQM5

E7 D3

M_DQS#4 M_DQS#5

G3 B7

X76@

DML DMU

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DQSL DQSU

RESET ZQ/ZQ0 NC/ODT1 NC/CS1 NC/CE1 NCZQ1

+1.5VGS

M_DA47 M_DA42 M_DA45 M_DA40 M_DA44 M_DA43 M_DA46 M_DA41

M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13

VREFCA VREFDQ

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

PX@

M_BA0 M_BA1 M_BA2

M2 N8 M3

M_CLK1 M_CLK#1 M_CKE1

J7 K7 K9

A1 A8 C1 C9 D2 E9 F1 H2 H9

VRAM_ODT1 K1 L2 M_CS#1 J3 M_RAS#1 K3 M_CAS#1 L3 M_WE#1 M_DQS6 M_DQS7

F3 C7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

M_DQM6 M_DQM7

E7 D3

M_DQS#6 M_DQS#7

G3 B7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

CK CK CKE/CKE0 ODT/ODT0 CS/CS0 RAS CAS WE

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

DQSL DQSU DML DMU

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

DQSL DQSU

RESET ZQ/ZQ0

J1 L1 J9 L9

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

PX@

96-BALL SDRAM DDR3 H5TQ1G63DFR-11C

+1.5VGS

M_DA52 M_DA48 M_DA54 M_DA50 M_DA53 M_DA49 M_DA55 M_DA51

D7 C3 C8 C2 A7 A2 B8 A3

D

M_DA60 M_DA58 M_DA56 M_DA61 M_DA63 M_DA62 M_DA57 M_DA59

B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5VGS A1 A8 C1 C9 D2 E9 F1 H2 H9

C

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 B1 B9 D1 D8 E2 E8 F9 G1 G9

96-BALL SDRAM DDR3 H5TQ1G63DFR-11C X76@

+1.5VGS

E3 F7 F2 F8 H3 H8 G2 H7

+1.5VGS

BA0 BA1 BA2

L8

R444 243_0402_1%

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

DRAM_RST# T2

B1 B9 D1 D8 E2 E8 F9 G1 G9

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

X76@

+1.5VGS

D7 C3 C8 C2 A7 A2 B8 A3

M8 H1

+VREFC_A4 +VREFD_Q4

+1.5VGS

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

DQSL DQSU

96-BALL SDRAM DDR3 H5TQ1G63DFR-11C

M_DA35 M_DA34 M_DA36 M_DA37 M_DA32 M_DA38 M_DA33 M_DA39

+1.5VGS

ODT/ODT0 CS/CS0 RAS CAS WE

J1 L1 J9 L9

E3 F7 F2 F8 H3 H8 G2 H7

B2 D9 G7 K2 K8 N1 N9 R1 R9

VDD VDD VDD VDD VDD VDD VDD VDD VDD

CK CK CKE/CKE0

L8

R410 243_0402_1%

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

BA0 BA1 BA2

DRAM_RST# T2

B1 B9 D1 D8 E2 E8 F9 G1 G9

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

VRAM_ODT1K1 L2 M_CS#1 M_RAS#1 J3 M_CAS#1 K3 L3 M_WE#1

VRAM_ODT1 [27] M_CS#1 [27] M_RAS#1 [27] M_CAS#1 [27] M_WE#1

U21

VREFCA VREFDQ

+1.5VGS

BA0 BA1 BA2

L8

R451 243_0402_1%

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

DRAM_RST# T2

B1 B9 D1 D8 E2 E8 F9 G1 G9

U18

VREFCA VREFDQ

+1.5VGS VDD VDD VDD VDD VDD VDD VDD VDD VDD

CK CK CKE/CKE0

L8

R454 243_0402_1%

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

BA0 BA1 BA2

T2

DRAM_RST#

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

VRAM_ODT0K1 L2 M_CS#0 M_RAS#0 J3 M_CAS#0 K3 L3 M_WE#0

VRAM_ODT0 [27] M_CS#0 [27] M_RAS#0 [27] M_CAS#0 [27] M_WE#0

[27]

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

M_BA0 M_BA1 M_BA2

U20

VREFCA VREFDQ

1

D

M8 H1

2

+VREFC_A1 +VREFD_Q1

1

M_DQM[7..0]

1

2

[27]

2

1

M_DA[63..0] M_MA[13..0]

3

2

[27] [27]

4

M_DA[63..0]

X76@

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

2

PX@

PX@

PX@

C506 0.01U_0402_16V7K

+1.5VGS

C479

1

C513

1

PX@

4.99K_0402_1%

PX@

1

2

PX@ PX@

PX@

PX@

1

1

1

1

C487

1

C505

1

C504

PX@

PX@

PX@

1

C503

PX@ PX@

1

C502

PX@

1

C509

1

C508

1

C499

1

C498

1

C497

PX@

1

@ 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z

PX@

PX@

1

1

C496

PX@

1

C495

PX@

1

C494

PX@

1

C484

1 1

C511

C493

C491

2 2 2 10U_0603_6.3V6M10U_0603_6.3V6M

C483

PX@

C512 2

C510

PX@

C490

2 10U_0603_6.3V6M

1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z

1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 C492

C489 2

1

10U_0603_6.3V6M 1

C501

1

10U_0603_6.3V6M 1

C500

10U_0603_6.3V6M 1

PX@ 2 56_0402_1%

2

+VREFD_Q4 R445

+1.5VGS 1

2 56_0402_1%

1 R436

4.99K_0402_1%

1

+1.5VGS

C488

1 R422

R446

2

4.99K_0402_1%

1

2

C477

1

PX@

R447

2

C476

1 2

2

2

2

2

2

1

1

1

1

1

1 1 2

R448 4.99K_0402_1%

PX@ PX@

2

M_CLK#1

2

PX@

2 56_0402_1%

PX@

A

C474

1

C473

1 2

C472

1 2

2 PX@

1

PX@

0.1U_0402_10V6K

1 R396 PX@

M_CLK1

2

R449 4.99K_0402_1%

4.99K_0402_1%

+VREFC_A4 PX@

0.1U_0402_10V6K

PX@

1

R385

+VREFD_Q3 0.1U_0402_10V6K

2

R388 4.99K_0402_1%

4.99K_0402_1%

PX@ 0.1U_0402_10V6K

1

R384

4.99K_0402_1%

2 56_0402_1% PX@

M_CLK#0

R387 4.99K_0402_1%

R383

+VREFC_A3 PX@

0.1U_0402_10V6K

1 R443

+VREFD_Q2 PX@

0.1U_0402_10V6K

M_CLK0

+VREFC_A2 PX@

0.1U_0402_10V6K

PX@

0.1U_0402_10V6K

2

2

+VREFC_A1 PX@

1

R382 4.99K_0402_1%

C475

+VREFD_Q1 PX@ R386 4.99K_0402_1%

R381 4.99K_0402_1%

2

R380 4.99K_0402_1%

2

R379 4.99K_0402_1%

2

R450 4.99K_0402_1%

1

1

B

1

B

2 2 2 2 2 2 2 2@ 2 2@ 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z PX@

PX@

PX@

PX@ PX@

PX@

PX@

PX@ PX@

A

PX@

C507 0.01U_0402_16V7K

2

ref 139-02 recommand

PX@

VRAM P/N :

add off page

Hynix : SA000041S10 (S IC D3 64MX16 H5TQ1G63BFR-11C FBGA C38! )

Park SCL recommand pu 60.4 ohm

Samsung : SA000041T10 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA C38! )

to 1.5VGS 0619 update

update VRAM PN

Issued Date

0619 update

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2010/07/12

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

SeymourXT-S3 VRAM Size C Date:

5

4

3

2

Document Number

Rev 0.1

Thursday, February 02, 2012

Sheet 1

28

of

55

5

4

3

2

1

LCD POWER CIRCUIT +LCDVDD

CMOS Camera

+3VS

+5VALW

+3VS

W=60mils

(20 MIL)

1

1 R1454 150_0603_5%

D

R1455 100K_0402_5%

2

CMOS@ Q70 PMV65XP_SOT23-3~D

C1150 4.7U_0603_6.3V6K

1 OUT 3

1

GND

IN

3 1

2

2

1 3

2

PCH_ENVDD

1

Q72 PMV65XP_SOT23-3~D

R1458 CMOS@ 150K_0402_5%

W=60mils

D

[16]

C1154 0.1U_0402_16V4Z

G

Q71 2N7002_SOT23 S

2

G

R1457 220K_0402_5% 1 2

2 G

[37] 2

+LCDVDD

1

2 2

FBMA-L11-201209-221LMA30T_0805 C1156 4.7U_0603_6.3V6K

2

@ R1459 100K_0402_5%

1

1

2

2

10U 1

2

C1153 @ 10U_0603_6.3V6M

CMOS_ON#

+LCDVDD_CONN

L29 1

Q73 DTC124EK DTC124EKAT146_SC59-3

1

S

D

D

CMOS@ (20 MIL) 2 1 R1456 1 0_0603_5% CMOS@ C1152 0.1U_0402_16V4Z R02 2

D

S

3

+3VS_CMOS

R296 for CMOS shake issue reserve C1155 CMOS@ 0.1U_0402_16V4Z

C1157 0.1U_0402_16V4Z

VGA LCD/PANEL BD. Conn. +LEDVDD

B+

C

C

C1158 680P_0402_50V7K @

1

1

2

2

1 R1460 2 0_0805_5% C1159 4.7U_0805_25V6-K

+3VS

1

JLVDS1 ME@ R1462 0_0402_5% 2 1

R1461 @

BKOFF#

1

[37]

2

DISPOFF#

D30 @ CH751H-40PT_SOD323-2 R1464 10K_0402_5%

[16] [37]

R1463 1

PCH_PWM

R1465 1

EC_INVT_PWM

DISPOFF# INVT_PWM

2 0_0402_5% @

[16] [16]

2 0_0402_5%

[16]

R1466 2

PCH_ENBKL

1 0_0402_5%

ENBKL

LVDS_ACLK LVDS_ACLK#

[16] LVDS_A2 [16] LVDS_A2# [16] LVDS_A1 [16] LVDS_A1# [16] LVDS_A0 [16] LVDS_A0# [16] EDID_DATA [16] EDID_CLK

2

B

1

2

4.7K_0402_5% BKOFF#

[37] +3VS

2

1 680P_0402_50V7K C1160 @

R1467 100K_0402_1%

+LCDVDD_CONN

2

+3VS_CMOS USB20_P11 USB20_N11

[17] [17]

1

(60 MIL)

+3VS USB20_P11 USB20_N11

CMOS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

B

GND1 GND2 GND3 GND4 GND5 GND6

31 32 33 34 35 36

STARC_107K30-000001-G2 SP010011S00

A

A

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. LVDS/CAMERA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev 0.1

Sherry and Royal

Thursday, February 02, 2012

Sheet 1

29

of

55

5

4

3

2

1

+5VS +5VS

RB491D_SC59-3 D31 HDMI@ 2 1+HDMI_5V

2

W=40mils +5VS_HDMI F1 HDMI@ 1.1A_6VDC_FUSE 1 2 +5VS_HDMI 1

2

3

+3VS

1

2

HDMI@ R1470 2.2K_0402_5% 1

R1472 20K_0402_5% HDMI@

R1471 HDMI@ 2.2K_0402_5%

1

JHDMI1 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

HDMI_DET +5VS_HDMI HDMIDAT_R HDMICLK_R

C

+3VS

1

HDMI@ R1479 0_0402_5%

HDMI_CLK-_CK

HDMI_CLK-_CK R1473 1 @

2 0_0402_5%

HDMI_CLK-_CONN

HDMI_CLK+_CK HDMI_TX0-_CK

HDMI_CLK+_CKR1474 1 @ HDMI_TX0-_CK R1475 1 @

2 0_0402_5% 2 0_0402_5%

HDMI_CLK+_CONN HDMI_TX0-_CONN

[16] [16]

HDMI_TX0+_CK HDMI_TX1-_CK

HDMI_TX0+_CK R1476 1 @ HDMI_TX1-_CK R1477 1 @

2 0_0402_5% 2 0_0402_5%

HDMI_TX0+_CONN HDMI_TX1-_CONN

[16] [16]

HDMI_TX1+_CK HDMI_TX2-_CK

HDMI_TX1+_CK R1478 1 @ HDMI_TX2-_CK R1480 1 @

2 0_0402_5% 2 0_0402_5%

HDMI_TX1+_CONN HDMI_TX2-_CONN

[16]

HDMI_TX2+_CK

HDMI_TX2+_CK R1481 1 @

2 0_0402_5%

HDMI_TX2+_CONN

6

L30 HDMI_CLK+_CK

1

[16]

HDMIDAT_NB

4

3

HDMI_CLK-_CK

4

2

4

3

2

HDMI_CLK+_CONN

3

HDMI_CLK-_CONN

HDMICLK_R

HDMIDAT_R L31

Q75B HDMI@ 2N7002DW-T/R7_SOT363-6

HDMI_TX0+_CK

1

HDMI_TX0-_CK

4

2

4

3

L32 HDMI_TX1+_CK

1

HDMI_TX1-_CK

4

HDMI_CLK-_CONN HDMI_CLK+_CONN HDMI_TX1-_CONN HDMI_TX1+_CONN

HDMI@

1

2

HDMI_TX0+_CONN

3

HDMI_TX0-_CONN

WCM-2012HS-900T HDMIDAT_R

2

4

3

2

HDMI_TX1+_CONN

3

HDMI_TX1-_CONN

SD309680080 S ROW RES 1/16W 680 +-5% 8P4R

RP1 HDMI@

HDMI_TX0-_CONN HDMI_TX0+_CONN HDMI_TX2-_CONN HDMI_TX2+_CONN

HDMI@

1

680 +-5% 8P4R 5 4 6 3 7 2 8 1

680 +-5% 8P4R 5 4 6 3 7 2 8 1 RP2 HDMI@

+3VS

3

S

2

WCM-2012HS-900T D33 @ PJDLC05_SOT23-3

L33 HDMI_TX2+_CK

1

HDMI_TX2-_CK

4

B

D

HDMICLK_R

3

C

HDMI@

1

WCM-2012HS-900T B

20 21

1

2

Q75A HDMI@ 2N7002DW-T/R7_SOT363-6

1

HDMICLK_NB

ME@

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ D0D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

ACON_HMR2H-AK120C DC232001400

5

[16]

[16] [16] [16]

2

Pull up R for PCH OR VGA SIDE

D

2

3

C1161 HDMI@ 0.1U_0402_16V4Z 2

D32 @ BAT54S-7-F_SOT23-3

2

TMDS_B_HPD#

D

TMDS_B_HPD#

S

[16]

Q74 HDMI@ 2N7002H_SOT23-3

1

1

G

2

R1469 1M_0402_5% HDMI@

1

D

2 G Q76 HDMI@ 2N7002H_SOT23-3

HDMI@

1

2

4

3

2

HDMI_TX2+_CONN

3

HDMI_TX2-_CONN

WCM-2012HS-900T A

1

A

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification 2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDMI CONN Document Number

Date: Thursday, February 02, 2012

5

4

3

2

Rev 0.1

Sherry and Royal Sheet 1

30

of

55

B

C

D

E

Mini-Express Card for WLAN/WiMAX(Half) Mini-Express Card for SSD(Full)

Reserve for SW mini-pcie debug card. Series resistors closed to KBC side. LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB

Mini-Express Card(WLAN/WiMAX) +1.5VS

contact to +3VS_WLAN for AOAC function

+1.5VS_WLAN

[37]

R1505 1

EC_WL_WAKE#

2 0_0402_5%

R1520 1 @

EC_WL_WAKE#_R

2 0_0402_5%

PCH_PCIE_WAKE#

[15,32]

[18]

PCH_BT_ON# BT_DISABLE

R1490 1

2

R1491 1

2

BT_DISABLE_R WLAN_CLKREQ#

0_0402_5% 0_0402_5%

[14]

WLAN_CLKREQ#

[14] CLK_PCIE_WLAN1# [14] CLK_PCIE_WLAN1 PCI_RST#_R CLK_PCI_DB [14] [14] [14] [14]

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 +3VS_WLAN

EC_TX EC_RX

EC_TX EC_RX

For EC to detect debug card insert.

2

53

WAKE# 3.3V NC GND NC 1.5V CLKREQ# NC GND NC REFCLKNC REFCLK+ NC GND NC NC GND NC NC GND PERST# PERn0 +3.3Vaux PERp0 GND GND +1.5V GND SMB_CLK PETn0 SMB_DATA PETp0 GND GND USB_DNC USB_D+ NC GND NC LED_WWAN# NC LED_WLAN# NC LED_WPAN# NC +1.5V NC GND NC +3.3V GND

GND

2

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

2 2 2 2 2 2

LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 PLT_RST#

0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

LPC_FRAME# [13,37] LPC_AD3 [13,37] LPC_AD2 [13,37] LPC_AD1 [13,37] LPC_AD0 [13,37] CLK_PCI_DB

[17]

1 C1172 0.1U_0402_16V4Z

2

1

C1173 0.1U_0402_16V4Z R1503 0_0402_5% 1 2

+1.5VS_WLAN LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R R1492 1

USB20_N2_WLAN

0_0402_5% WL_RST# 2 @ 0_0402_5% 2 0_0402_5%

R1496 1 R1497 1

2 2

1 2 0_0402_5% R1504

USB20_P2_WLAN

2

R1494 1 R1495 1

PCH_WL_OFF# +3VALW +3VS_WLAN

[17] 2 1 PLT_RST# 0_0402_5% R1493

SMB_CLK_S3 SMB_DATA_S3

0_0402_5% @ 0_0402_5% @

PLT_RST#

[17,32,37]

USB20_N2 USB20_P2

+3VALW

SMB_CLK_S3 [12,14,38] SMB_DATA_S3 [12,14,38]

7

USB20_N2_WLAN USB20_P2_WLAN

USB20_N2_WLAN

5

USB20_P2_WLAN

3

NC

4

VCC

D-

HSD-

D+

HSD+

GND

OE#

8 6 2

C1273 @ 1 2 0.1U_0402_16V4Z USB20_N2 USB20_N2 USB20_P2

1

U1

@ TS3USB31RSER_QFN8_1P5X1P5 +3VS

+3VS_WLAN

R1518

2

AOAC@

C1170 1

2

R1500

0.1U_0402_16V4Z

1

1

2

2

[17] [17] [37]

R1519 @ 0_0402_5%

+3VS_WLAN_AOAC

nonAOAC@ 1 0_0603_5%

R1501 100K_0402_5%

USB20_P2

WLAN_USB_ON#

54

BELLW_80019-1021 DC040004X00

2

[37] [37]

100_0402_1% R1498 1 2 1 2 R1499 100_0402_1%

1

R1488 0_0603_5%

JWLAN1 ME@ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

@ [18]

@ @ @ @ @ @

1

+3VS_WLAN 1

1 1 1 1 1 1

2

9/18 JP1 Pin2,24,52

R1482 R1483 R1484 R1485 R1486 R1487

1

A

1 0_0603_5% 2

@ C1171 10U_0603_6.3V6M

+3VALW Q77

AO3413_SOT23-3 D

S

3

1

1

AOAC@ 2

G

[37]

Mini-Express Card(SSD) +3VS_SSD

1 C1176

2

1 C1177

1 C1178

2

2

@ C1179

11/07 Change type to 0603

3

[13] [13]

SATA_PRX_DTX_C_P0 SATA_PRX_DTX_C_N0 [13] [13]

SATA_PTX_DRX_N0 SATA_PTX_DRX_P0

0.01U_0402_16V7K 2 SATA_PRX_DTX_C_P0 2 SATA_PRX_DTX_C_N0 0.01U_0402_16V7K

C1181 1 SATA_DTX_IRX_P0 1 SATA_DTX_IRX_N0 C1180

SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 +3VS_SSD

@ R553 [18]

mSATA_DET#

For SSD use:

1

0_0402_5% 2 mSATA_DET#_R

1

2

AOAC@ C1175 0.1U_0402_16V4Z

1

2

2

9/18 Increase for Intel AOAC function

JUMP_43X79 @

2

10U_0603_6.3V6M 0.01U_0402_16V7K

AOAC@

J14

10U_0603_6.3V6M 1

1

R1502 150K_0402_5%

AOAC@ C1174 0.1U_0402_16V4Z

+3VS_SSD

+3VS

0.1U_0402_16V4Z

AOAC_ON#

SSD Active:4.5W(1.5A)

2

JSSD1 ME@ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53

WAKE# 3.3V NC GND NC 1.5V CLKREQ# NC GND NC REFCLKNC REFCLK+ NC GND NC NC GND NC NC GND PERST# PERn0 +3.3Vaux PERp0 GND GND +1.5V GND SMB_CLK PETn0 SMB_DATA PETp0 GND GND USB_DNC USB_D+ NC GND NC LED_WWAN# NC LED_WLAN# NC LED_WPAN# NC +1.5V NC GND NC +3.3V GND

GND

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

3

54

BELLW_80019-1021 DC040004X00

4

4

Compal Secret Data

Security Classification Issued Date

2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Mini-Card Size

B

C

D

Document Number

Rev 0.1

Sherry and Royal Date:

A

Compal Electronics, Inc.

Thursday, February 02, 2012

Sheet E

31

of

55

5

4

3

2

1

Layout Notice : Place as close chip as possible. +3V_LAN

+3VALW D

D

+LAN_VDD10 L34

J15

1 2 +LAN_REGOUT 2.2UH +-5% NLC252018T-2R2J-N

X5R

2

2

@

C1184 4.7U_0603_6.3V6K

1

SA00003PO40

1

JUMP_43X79

2

Layout Note: L39 must be within 200mil to Pin36, C700,C738 must be within 200mil to LL1 +LAN_REGOUT: Width =60mil

RTL8105E-VL-CGT

1 1

8105@

2

U47

C1182 0.1U_0402_16V4Z

U47

2 0.1U_0402_16V7K

PCIE_DTX_PRX_N1

23

[14]

[14] [14]

16

LAN_CLKREQ#

[17,31,37]

C

17 18

PCIE_PTX_C_DRX_P1 PCIE_PTX_C_DRX_N1

25

PLT_RST#

19 20

CLK_PCIE_LAN CLK_PCIE_LAN#

Pin 16 and Pin 28 are OD pins

1 R1508 1 R1509 @

[37] LAN_WAKE# [15,31] PCH_PCIE_WAKE#

+3V_LAN

+3V_LAN

2 0_0402_5% 2 0_0402_5%

LAN_XTALI

43

LAN_XTALO

44 28

PCIE_WAKE#_R

ISOLATEB 26

@ @

2 R1510 1 R1511

14 15 38

1 10K_0402_5% 2 1K_0402_5%

33

1

ENSWREG R1512 10K_0402_5% @

34 35

2

+LAN_VDDREG

1 2 R1513 2.49K_0402_1%

46 24 49

LAN_CLKREQ#

LED3/EEDO LED1/EESK LED0

HSON HSIP HSIN

EECS EEDI

CLKREQB

MDIP0 MDIN0 MDIP1 MDIN1 NC/MDIP2 NC/MDIN2 NC/MDIP3 NC/MDIN3

PERSTB REFCLK_P REFCLK_N

31 37 40

Layout Notice : Place as close chip as possible. @

30 32

R1506 2 R1507 2

+LAN_VDD10

1 10K_0402_5% 1 10K_0402_5%

1 2 4 5 7 8 10 11

MDI0+ MDI0MDI1+ MDI1MDI2+ MDI2MDI3+ MDI3-

MDI0+ MDI0MDI1+ MDI1MDI2+ MDI2MDI3+ MDI3-

[33] [33] [33] [33] [33] [33] [33] [33]

1 L35

Close to Pin 12,27,39,42,47,48

C1187 1U_0402_6.3V4Z

C1188 0.1U_0402_16V4Z

+3V_LAN

1

Close to Pin 21

0.1U_0402_16V4Z

1 0.1U_0402_16V4Z

CKXTAL1

1

CKXTAL2

DVDD10 DVDD10 DVDD10

13 29 41

0.1U_0402_16V4Z

+LAN_VDD10

1 +3V_LAN

LANW AKEB

GIGA@ 0.1U_0402_16V4Z

+LAN_VDDREG

1 GIGA@ 0.1U_0402_16V4Z

ISOLATEB

DVDD33 DVDD33

NC/SMBCLK NC/SMBDATA GPO/SMBALERT

AVDD33 AVDD33 AVDD33 AVDD33

ENSW REG EVDD10 VDDREG VDDREG

AVDD10 AVDD10 AVDD10 AVDD10

RSET GND PGND

REGOUT

27 39 12 42 47 48 21 3 6 9 45

2 0_0603_5%

+3V_LAN

1 L36

1

C1195 4.7U_0603_6.3V6K

+3V_LAN

X5R

GIGA@ 0.1U_0402_16V4Z

C

Close to Pin 3,6,9,13,29,41,45

+LAN_VDD10

+LAN_VDD10 +3VS

+3V_LAN

1 0.1U_0402_16V4Z

36

2 C1189 2 C1190 2 C1191 2 C1192 2 C1193 2 C1194

C1196 0.1U_0402_16V4Z

+LAN_EVDD10

+LAN_REGOUT

1 0.1U_0402_16V4Z

R1514 1K_0402_5%

RTL8111F-CGT_QFN48_6x6 GIGA@

B

Rising time (10%~90%)1mS
+LAN_EVDD10

2 0_0603_5%

@

2

[14] [14]

HSOP

2

C1186 1

1

PCIE_DTX_C_PRX_N1

2

[14]

1

22

1

PCIE_DTX_PRX_P1

2

2 0.1U_0402_16V7K

1

C1183 1

2

PCIE_DTX_C_PRX_P1

1

[14]

1

R1515 0_0402_5% ISOLATEB

0.1U_0402_16V4Z

1 GIGA@

0.1U_0402_16V4Z

GIGA@

0.1U_0402_16V4Z

GIGA@

0.1U_0402_16V4Z

GIGA@

0.1U_0402_16V4Z

1

ENSWREG

SA00004Y700

1 R1517 0_0402_5% @

R1516 15K_0402_5%

1

2 C1197 2 C1198 2 C1199 2 C1200 2 C1201 2 C1202 2 C1203

B

LAN_XTALI LAN_XTALO

Y4

NC

OSC

OSC

NC

2 C1205

R02

2

H: Enable internal Regular L: Disable

3

1 25MHZ_20PF_FSX3M-25.M20FDO 1 C1204

27P_0402_50V8J

1

2

27P_0402_50V8J

4

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/15

2012/07/11

Deciphered Date

Title

LAN-RTL8111F/8105E

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Thursday, February 02, 2012 Date:

Rev 0.1

Sherry and Royal

5

4

3

2

Sheet 1

32

of

55

5

4

3

2

1

Reserve gas tube for EMI go rural solution

T71 [32] [32]

@

D

MDI2+

D34 AZC099-04S.R7G_SOT23-6 1 4 I/O1 I/O3

MDI3+ [32] [32]

2

MDI3-

3

GND

VDD

I/O2

I/O4

MDI3+ MDI3-

MDI3+ MDI3-

MDI2+ MDI2-

MDI2+ MDI2-

1 2 3 4 5 6 7 8

TD+ TDCT NC NC CT RD+ RD-

TX+ TXCT NC NC CT RX+ RX-

16 15 14 13 12 11 10 9

MDO3+ MDO3MCT3

J17

CHASSIS1_GND

D

JUMP_48X40 R1521 1 2 1 2 75_0805_5% C1206 10P_0603_50V8-J

BOTHHAND_NS0013LF GIGA@

Place Close to T1,T2

R02

MDI2-

2 Spark Gap

MCT2 MDO2+ MDO2-

5

6

@

1

2

1 CHASSIS2_GND

T72 LSE-200NX3216TRLF_1206-2

Place Close to T71

[32] [32]

MDI0+ MDI0-

MDI0+ MDI0-

1 @ C

MDI1+

D35 AZC099-04S.R7G_SOT23-6 1 4 I/O1 I/O3

2

[32] [32]

C1207 0.01U_0402_16V7K

MDI1+ MDI1-

MDI1+ MDI1-

1 2 3 4 5 6 7 8

TD+ TDCT NC NC CT RD+ RD-

TX+ TXCT NC NC CT RX+ RX-

16 15 14 13 12 11 10 9

MDO0+ MDO0-

DL2 J18

GND

VDD

@

1

MCT1

2 CHASSIS1_GND

MDO1+ MDO1-

Spark Gap JUMP_48X40

MDI0+

C

BOTHHAND_NS0013LF J19

2

@

MCT0

5

@

1

2 Spark Gap

MDI0-

3

I/O2

I/O4

6

MDI1-

JUMP_48X40 JRJ1

ME@

Place Close to T72 GND GND

B

D34/D35 1'S PN:SC300001G00 2'S PN:SC300002E00

MDO0+

1

MDO0-

2

MDO1+

3

MDO2+

4

MDO2-

5

MDO1-

6

MDO3+

7

MDO3-

8

GND PR1+ GND

12 11 10 9 CHASSIS2_GND

PR1PR2+

B

CHASSIS1_GND

PR3+ PR3PR2PR4+ PR4-

SANTA_130460-3 DC231112261

Reserve for EMI go rural solution

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

LAN_Transformer Document Number

Rev 0.1

Sherry and Royal Thursday, February 02, 2012

Sheet 1

33

of

55

3

2

1

SMSC thermal sensor placed near by VRAM

C1211 2200P_0402_50V7K

1 +3VS

2

R1524 10K_0402_5% @

REMOTE1-

1

VDD

REMOTE2+ 1 2 2

C1212 0.1U_0402_16V4Z

REMOTE2-

1

REMOTE1+

2

REMOTE1-

3

REMOTE2+

4

REMOTE2-

DP1

5

Q79 MMST3904-7-F_SOT323-3

D

E

REMOTE1-

SMCLK SMDATA

DN1

ALERT#

DP2

THERM#

DN2

GND

10

EC_SMB_CK2

9

EC_SMB_DA2

EC_SMB_CK2

[14,23,37]

EC_SMB_DA2

[14,23,37]

Under mSSD

REMOTE2+ 1

8 @ C1214 100P_0402_50V8J

7 6

2 B

2

C Q80 MMST3904-7-F_SOT323-3

E

REMOTE2-

EMC1403-2-AIZL-TR_MSOP10

REMOTE1,2+/-: Trace width/space:10/10 mil Trace length:<8"

Address 1001_101xb

FAN1 Conn

C

C

2 B

2

2

U49

C1213 @ 2200P_0402_50V7K

@ C1210 100P_0402_50V8J

1

1

REMOTE1+ 1

D

Close to DDR

REMOTE1+

+3VS

1

Close U27

3

4

3

5

C

+5VS 0_0603_5% JFAN1 ME@ 2

[37] EC_TACH EC_FAN_PWM

2 C1215 10U_0603_6.3V6M

R H25 HOLEA

H17 HOLEA

ACES_85204-04001 SP02000CW00

H_2P5X3P1N

H_2P5X3P1N

FD1

R

H_2P5

CHASSIS1_GND

H_2P5

H_2P5

H_2P5N H_4P0

H_2P5

H16 HOLEA

H12 HOLEA

H_5P4X2P5

H_5P4X2P5

M/B

FD3

FD4

B

橢橢橢

M/B KB

橢橢橢

1

H_2P5

1

H_2P5

H14 HOLEA

1 H_3P0

H29 HOLEA

1

H15 HOLEA

1

H13 HOLEA

1

H8 HOLEA

1

H7 HOLEA

1

H11 HOLEA

1

H10 HOLEA

1

H6 HOLEA

1

1

H9 HOLEA

1

E

B

FD2

1

10U

1

1

1

1 2 3 4 G1 G2

1

[37]

1 2 3 4 5 6

+5VS_FAN

1

R1525 1

H_5P4X2P5

A 2P5 * 9 pcd H18 HOLEA

H19 HOLEA

H20 HOLEA

H21 HOLEA

H22 HOLEA

H23 HOLEA

G

F

H24 HOLEA

1

1

H_4P0

H_4P0

H_3P3

H_3P3

1

1

H_4P0

1

1

A

1

A

B

CPU

C

GPU

D

CHASSIS2_GND H_3P3

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification CHASSIS1_GND H_3P3

2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LAN

Fintek-Thermal IC/FAN/screw Document Number

Date: Thursday, February 02, 2012

5

4

3

2

Rev 0.1

Sherry and Royal Sheet 1

34

of

55

A

B

C

D

E

F

G

H

1

1

SATA HDD Conn. JHDD1 [13] [13] [13] [13]

SATA_DTX_C_PRX_N1 SATA_DTX_C_PRX_P1

SATA_DTX_C_PRX_N1 SATA_DTX_C_PRX_P1

SATA_PTX_R_DRX_P1 SATA_PTX_R_DRX_N1

C1217 1 C1216 1

2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

+3VS

+5VS

1 2 3 4 5 6 7

SATA_PTX_R_DRX_P1 SATA_PTX_R_DRX_N1 SATA_DTX_PRX_N1 SATA_DTX_PRX_P1

R435 1

0_0805_5% 2 +3VS_HDD

R1526 1

0_0805_5% 2 +5VS_HDD

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

2

+5VS_HDD R02

10U

2

2

1

1

1 C1218 1000P_0402_50V7K

C1219 0.1U_0402_16V4Z

2

1

+3VS_HDD

R02 C1220 @ 1U_0402_6.3V6K

2

1 C1221 10U_0603_6.3V6M

2

ME@

GND A+ AGND BB+ GND

PTH PTH NPTH NPTH

23 24 25 26

3.3V 3.3V 3.3V GND GND GND V5 V5 V5 GND RSVD GND V12 V12 V12

2

SANTA_192701-1 DC010006J00

@ C1222 0.1U_0402_16V4Z

3

3

4

4

Compal Secret Data

Security Classification 2011/06/15

Issued Date

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. HDD/ODD/BT Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

E

F

Thursday, February 02, 2012 G

Rev 0.1

Sherry and Royal Sheet

35

of H

55

3

2

R1529

C1233

C1232

C1228

4.7U_0603_6.3V6K

@

2

Place near Pin1

1

2

@

Place near Pin9 D

+3VDD_CODEC +IOVDD_CODEC

9

Vendor recommend. 2.2K

2 HDA_SDIN0 22_0402_5%

1 SDATA_IN R1536

8

LINE1-L(PORT-C-L)

SDATA-OUT

MIC1-R(PORT-B-R)

BIT-CLK

MIC1-L(PORT-B-L)

SDATA-IN

MIC2-R(PORT-F-R) MIC2-L(PORT-F-L)

10

HDA_SYNC_AUDIO

11

HDA_RST_AUDIO#

HDA_RST_AUDIO#

12

PC_BEEP 2

1 R1541

20K_0402_1%

C

JDREF

19 20

[38]

2

PLUG_IN#

39.2K_0402_1%

1 R1543

13

SENSEA

18

MIC Sense R939 place near pin13

35

CBN 2 C1239 2 C1240 2 C1241

Capless HP Sense R940 place near pin34

1 CBP 2.2U_0402_6.3V6M 1 2.2U_0402_6.3V6M 1 4.7U_0603_6.3V6K

36 34 28

SYNC

LINE2-R(PORT-E-R)

RESET#

LINE2-L(PORT-E-L)

30 31

+MIC1_VREFO_L

42 43 7

Vendor recommend. 2.2u

23 22

MIC_EXTR_C

21

MIC_EXTL_C

1 C1237 1 C1238

2

2 2.2U_0402_6.3V6M

1 1K_0402_5%

R1534

EXT_MIC

EXT_MIC

[38]

external MIC

2 2.2U_0402_6.3V6M

17 16

0110 delete R1539

15 14

PCBEEP SPK-OUT-L+ JDREF SPK-OUT-LMONO-OUT(PORT-H) SPK-OUT-RSense A SPK-OUT-R+

40

SPK_L2+

41

SPK_L1-

44

SPK_R1-

45

C

Internal Speaker

SPK_R2+

Sense-B CBN

HPOUT-R(PORT-A-R)

CBP

HPOUT-L(PORT-A-L)

CPVEE

SPDIF-OUT

LDO-CAP GPIO1/DMIC-CLK

29

24

1

DVDD1

AVDD1

AVDD2

LINE1-R(PORT-C-R)

PD#

MIC2-VREFO

GPIO0/DMIC-DATA

33

2

HPOUT_R

1

75_0402_5% 32

2

HPOUT_L

HP_OUTR

R1544 1

75_0402_5%

[38]

HP_OUTL

R1545

Headphone

[38]

48 0110 delete R1539 3

DMIC_CLK_R

2

DMIC_DATA_R

2

1 R937 1 R1548

0_0402_5% 2 0_0402_5%

DMIC_CLK

[38]

DMIC_DATA

[38]

MIC1-VREFO-R MIC1-VREFO-L PVSS1

VREF

PVSS2

AVSS1

DVSS

AVSS2 Thermal PAD

27

Place next to pin 27

26 37 49

1

C1243

6

DAPD/COMB_JACK

0.1U_0402_16V4Z

4 5

HDA_BITCLK_AUDIO

HDA_SDIN0

47

C1242 1

[13]

R1535 4.7K_0402_5% @

COMBOJACK 0_0402_5% EC_MUTE#_R 0_0402_5%

2

HDA_BITCLK_AUDIO

2

R1537 2.2K_0402_5%

1U_0402_6.3V6K

HDA_SDOUT_AUDIO

[13]

2

EC_MUTE#

2

[13]

MIC_JD

DVDD-IO

1 R1533 1 R1538 HDA_SDOUT_AUDIO

EC_MUTE#

PVDD2

2

1

38

+MIC1_VREFO_L 25

2

46

1

39

2

PVDD1 [37]

1

1

2

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z C1236

C1234

1

Power down (PD#) power stage for save power 0V: Power down power stage 3.3V: Power up power stage

[13]

2

1

Place near Pin38

U50

[13]

2

R1530 2

1 1

+5VS_PVDD 2

+3VS

0.1U_0402_16V4Z

C1231

C1230

2

1

Place near Pin25

R1531 0_0805_5% 2

4.7U_0603_6.3V6K C1235

1

+5VS

2

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

600ohms @100MHz 2A P/N: SM01000EE00

D

2 0_0603_5%

1

+3VDD_CODEC

0_0402_5%

1

0.1U_0402_16V4Z C1229

+5VDDA_CODEC

L37 1 2 FBMA-L11160808601LMA10T_2P 1

+IOVDD_CODEC

C1227 2 1

+5VDDA_CODEC

1

+3VDD_CODEC

C1226

+5VS

+3VS

10U_0603_6.3V6M

600ohms @100MHz 1A P/N: SM01000BU00

1U_0402_6.3V6K

4

0.1U_0402_16V4Z

5

2

ALC259Q-VC2-GR_QFN48_6X6 R1549 1

B

Pin Assignment

Location

Function

R1550 1

SPK-OUT (Pin40/41/44/45)

Internal

Int Speaker

R1551 1

Capless HP-OUT (Pin32/33)

External

Headphone out

MIC1(Pin21/22)

External

Mic in

2 0_0402_5%

B

HDA_RST_AUDIO# 2 0_0402_5%

HDA_SYNC_AUDIO

2 0_0402_5%

@

EMI

HDA_SDOUT_AUDIO 1

2

C1251

C1250

2

@

1

2

@

SE074102K80

G1 G2

ACES_88266-04001 SP02000K200

Combo Jack detect (normal open) R1123 47K_0402_5% 1 2

2

1

EXT_MIC

1

2

1 @

2

C1247 33P_0402_50V8J

@

PC Beep EC Beep PCH Beep

[37]

[13]

BEEP#

HDA_SPKR

1 2 C1252 0.1U_0402_16V4Z C44

R1557 1 2 33_0402_5%

1 2PC_BEEP1 C1253 0.1U_0402_16V4Z

1

PC_BEEP

A

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification 2011/07/21

Deciphered Date

2012/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

HD Audio Codec_ALC259Q-VC Size C

Document Number

3

2

Rev 0.1

Sherry and Royal

Date: Thursday, February 02, 2012 4

2

0.1U_0402_16V7K @ R1558 10K_0402_5%

D39 PACDN042Y3R_SOT23-3

Reserve for ESD request.

5

HDA_BITCLK_AUDIO 27_0402_5%

2

@

1

1

@ D38 PACDN042Y3R_SOT23-3

2 C1134

SPK_L2+_CONN 3

SPK_R1-_CONN 2

3

A

SPK_L1-_CONN

4.7U_0603_6.3V6K

MIC_JD SPK_R2+_CONN

GNDA

@

2

22P_0402_50V8J C1246

GND

5 6

1

@

1

@

1

1000P_0402_50V7K

2

1

1000P_0402_50V7K

@

1

1 2 3 4

2

22P_0402_50V8J C1245

JSPK1 ME@ 1 2 3 4

SPK_R2+_CONN SPK_R1-_CONN SPK_L1-_CONN SPK_L2+_CONN C1249

0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5%

1000P_0402_50V7K

2 2 2 2

C1248

1 1 1 1

@

1000P_0402_50V7K

R1553 R1555 R1554 R1556

1 22P_0402_50V8J C1244

wide 25MIL SPK_R2+ SPK_R1SPK_L1SPK_L2+

2

R1552

Sheet 1

36

of

55

+3VLP C1254 100P_0402_50V8J

R1577

1

R1576 2.2K_0402_5%

2

EC_SMB_DA1 2.2K_0402_5% [38] [38]

EC_SMB_CK2 EC_SMB_DA2

2

@ C1267 100P_0402_50V8J

1

2

@ C1268 100P_0402_50V8J

[42,43] [42,43] [14,23,34] [14,23,34]

For DS3

+3VS

[7]

1

2 R1581

[15,40] DRAMRST_CNTRL_EC

[29] [34]

EC_TACH 10K_0402_5% [31] [31]

[15]

[15] PM_SLP_S3# [15] PM_SLP_S5# [18] EC_SMI# [29] CMOS_ON# SLP_SUS#

2

2 DS3@ R1590

1

0_0402_5%

EC_INVT_PWM EC_TACH EC_PME# EC_TX EC_RX PCH_PWROK EC_FAN_PWM

EC_INVT_PWM EC_TACH

EC_TX EC_RX EC_FAN_PWM

1

6 14 15 16 17 18 19 25 28 29 30 31 32 34 36

EC_SMI#

PCH_PWROK [34]

77 78 79 80

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

NUM_LED#: NC

@ R1582 10K_0402_5%

R1586 [15]

SUSCLK

2

EC_RTCX1 SUSCLK_R

1

0_0402_5%

122 123

R1587 100K_0402_5%

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A

XCLKI/GPIO5D XCLKO/GPIO5E

C1271 20P_0402_50V8

97 98 99 109

1 EC_WL_WAKE#

1

R4957 2EC_WL_WAKE# 0_0402_5%

CPU1.5V_S3_GATE

2 R1571

NTC_V_R

GPIO Bus

GPIO

SPIDI/GPIO5B SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

ENBKL/GPIO40 PECI_KB930/GPIO41 FSTCHG/GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 PWR_LED#/GPIO54 BATT_LOW_LED#/GPIO55 SYSON/GPIO56 VR_ON/GPIO57 PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05 H_PROCHOT#_EC/GPXIOA06 VCOUT0_PH/GPXIOA07 GPO BKOFF#/GPXIOA08 PBTN_OUT#/GPXIOA09 PCH_APWROK/GPXIOA10 SA_PGOOD/GPXIOA11

GPI

AC_IN/GPXIOD01 EC_ON/GPXIOD02 ON/OFF/GPXIOD03 LID_SW#/GPXIOD04 SUSP#/GPXIOD05 GPXIOD06 PECI_KB9012/GPXIOD07 V18R

119 120 126 128 73 74 89 90 91 92 93 95 121 127 100 101 102 103 104 105 106 107 108

PCH_PWR_EN

PCH_PWR_EN

AOAC_ON#

AOAC_ON# SUSACK#

2 2 1

1

[40,42] [31] [15]

BATT_LOW_LED# SYSON

EC_RSMRST# EC_LID_OUT#

EC_LID_OUT# Turbo_V H_PROCHOT#_EC MAINPWON_R BKOFF# PBTN_OUT#

110 112 114 115 116 117 118

LID_SW# SUSP# PCH_HOT#_R PECI_KB9012

124

+V18R

1 0_0402_5%

@

R1591 2

R1583 2

@

1 0_0402_5% 2

R1584

43_0402_1%

1

2 2.2K_0402_5%

@1 C1319 1 BATT_TEMP C1265 1 ACIN C1266

2

NTC_V_R

@

100P_0402_50V8J

2 100P_0402_50V8J

2 100P_0402_50V8J

1

2 R1573 @

4.7K_0402_5%

+3VALW

R1641 100K_0402_5%

WLAN USB switch control

R1640 100K_0402_5%

WLAN_USB_ON#_R

LID_SW# @ KB9012A2 work around R1578 47K_0402_5%

[50]

VR_HOT#

VR_HOT#

1 R1579

2

R1580 2 1 0_0402_5%

Turbo_V [42] PROCHOT [42] MAINPWON [42,44]

1 0_0402_5%

ACIN [15,23,43] EC_ON [44] ON/OFF [38] LID_SW# [38] SUSP# [10,40,45,46,47,49] PCH_HOT# [14] H_PECI [18,6]

H_PROCHOT#

0_0402_5%

D

S

2

H_PROCHOT#_EC

G Q82 2N7002H_SOT23-3

BKOFF# [29] PBTN_OUT# [15] PCH_APWROK [15] SA_PGOOD [48]

ACIN EC_ON

R1569 1

2 2.2K_0402_5%

+3VLP

[15] [18]

@

TP_DATA

+3VALW

R1634 100K_0402_5%

ENBKL [29] DPWROK_EC [15] WLAN_USB_ON# [31]For BATT_CHG_LED# [38]

PWR_LED# [38] BATT_LOW_LED# [38] SYSON [40,45,46] VR_ON [50] PM_SLP_S4# [15]

R1567 1

PCH_PWR_EN

For DS3 WLAN_USB_ON#_R R1595 2 BATT_CHG_LED#

TP_CLK

R1572 100K_0402_1% @

[10,40]

ME_FLASH [13] NTC_V [42]

1 0_0402_5%

+3VS

+3VALW

EC_GPIO4D

CPU1.5V_S3_GATE

SPI Device Interface SPI Flash ROM

[31]

TP_CLK [38] TP_DATA [38]

[42,6]

1

2

C1269 47P_0402_50V8J

+3VALW

R1585 10K_0402_5%

1

2

C1270 4.7U_0603_6.3V6K

R1588

2 0_0402_5% 1 2 R1589

KB9012QF A3 LQFP 128P_14X14

EMC Request

S IC KB9012QF A3 LQFP 128P KB CONTROLLER

@

Issued Date

EC_PME#

1

3

Q83 @ 2N7002_SOT23

1

2011/06/15

[32]

PCI_PME#

[17]

+3VALW

2

Compal Secret Data

Security Classification

LAN_WAKE#

1

0_0402_5% @

SYSON ECAGND

PN : SA00004OB20

2

EC_VDD/AVCC

EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD/VCC EC_VDD0 EC_VDD/VCC

67

9 22 33 96 111 125

EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 SM EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47

1

1

KSO16 KSO17

1

R1575 2.2K_0402_5%

CPU1.5V_S3_GATE/GPXIOA00 WOL_EN/GPXIOA01 HDA_SDO/GPXIOA02 VCIN0_PH/GPXIOD00

R5118 10K_0402_5%

EC_MUTE# [36] USB_ON# [38,39]

USB_ON# EC_GPIO4D TP_CLK TP_DATA

10K_0402_5%

1

EC_SMB_CK1 2.2K_0402_5%

PS2 Interface

2

2

2

EC_MUTE#/GPIO4A USB_EN#/GPIO4B CAP_INT#/GPIO4C EAPD/GPIO4D TP_CLK/GPIO4E TP_DATA/GPIO4F

+3VALW

[15]

1

R1574

1

1 R1565

1

+3VS

SUSWARN# EC_MUTE#

83 84 85 86 87 88

2

+3VALW

R01 R1564 33K_0402_5%

+3VALW

S

2 47K_0402_5% KSO2

For DS3

D

2 47K_0402_5% KSO1

@

DA Output KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

68 70 71 72

2 G

@

R1570 1

DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D IREF/GPIO3E CHGVADJ/GPIO3F

1

R1568 1

2

10K_0402_5%

2

KSI[0..7]

USB_ON# 1

BRDID

1

[38] +3VALW

R1566

2

KSI[0..7]

R1562 100K_0402_1%

R1561 10K_0402_5% @

2

KSO[0..15]

[42]

EC_FAN_PWM

MP PVT DVT EVT

V V V

+3VALW +5VALW

[42,43]

BRDID

max

1

KSO[0..15] [38]

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

BATT_TEMP

VAD_BID 0 V 0.289 0.538 0.875

V V V

+3VS

BATT_TEMP ADP_I

typ

V AD_BID 0 V 0.250 0.503 0.819

V V V

2

1

EC_RST# EC_SCI# BATT_LEN#

BATT_TEMP/GPIO38 GPIO39 ADP_I/GPIO3A GPIO3B GPIO42 IMON/GPIO43

BEEP# [36] NOVO# [38] ACOFF [43]

1

C1264 0.1U_0402_16V4Z

EC_SCI# BATT_LEN#

AD Input

CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D

63 64 65 66 75 76

BEEP# NOVO# ACOFF

min

2

[18] [42]

2

PWM Output

21 23 26 27

VAD_BID 0 V 8.2K +/- 5% 0.216 18K +/- 5% 0.436 33K +/- 5% 0.712

0.1U_0402_10V6K C1272

47K_0402_5%

12 13 37 20 38

GPIO0F BEEP#/GPIO10 GPIO12 ACOFF/GPIO13

AGND/AGND

2

R1563

[17] CLK_PCI_EC [17,31,32] PLT_RST#

GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC & MISC LPC_AD0

R695 0

0 1 2 3

U51

69

10_0402_5%

100K +/- 5%

Board ID 2

ECAGND

1

+3VALW

1 @ R1560

2

GND/GND GND/GND GND/GND GND/GND GND0

2

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

1 2 3 4 5 7 8 10

2

1

[18] GATEA20 [18] KBRST# [13] SERIRQ [13,31] LPC_FRAME# [13,31] LPC_AD3 [13,31] LPC_AD2 [13,31] LPC_AD1 [13,31] LPC_AD0

2

3.3V +/- 5%

Vcc R694

+3VALW +EC_VCCA

1

2

2

@ C1263 22P_0402_50V8J

2

2

1

C1259 1000P_0402_50V7K

2 ECAGND 2 L39 FBM-11-160808-601-T_0603

1

2

1

C1261 1000P_0402_50V7K

1000P_0402_50V7K

2

1

C1258 0.1U_0402_16V4Z

C1262 0.1U_0402_16V4Z

+EC_VCCA C1260

1

C1257 0.1U_0402_16V4Z

1

1

C1256 0.1U_0402_16V4Z

1

C1255 0.1U_0402_16V4Z

+3VALW

2

11 24 35 94 113

L38 FBM-11-160808-601-T_0603

1

1

2

3

1 +3VALW

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. BIOS & EC I/O Port

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev 0.1

Sherry and Royal

Thursday, February 02, 2012

Sheet

37

of

55

KSI[0..7]

KSI[0..7]

KSO[0..17]

KSO[0..17]

2

+3VALW

1

R1592 100K_0402_5%

[37]

NOVO#

[37]

ON/OFF

[37] [37]

KSO16

C1277 1

2 @ 100P_0402_50V8J

KSO17

C1278 1

2 @ 100P_0402_50V8J

KSO2

C1275 1

2 @ 100P_0402_50V8J

KSO1

C1279 1

2 @ 100P_0402_50V8J

KSO15

C1280 1

2 @ 100P_0402_50V8J

KSO7

C1276 1

2 @ 100P_0402_50V8J

KSO6

C1281 1

2 @ 100P_0402_50V8J

KSI2

C1282 1

2 @ 100P_0402_50V8J

KSO8

C1283 1

2 @ 100P_0402_50V8J

KSO5

C1284 1

2 @ 100P_0402_50V8J

KSO13

C1285 1

2 @ 100P_0402_50V8J

KSI3

C1286 1

2 @ 100P_0402_50V8J

KSO12

C1287 1

2 @ 100P_0402_50V8J

KSO14

C1288 1

2 @ 100P_0402_50V8J

KSO11

C1289 1

2 @ 100P_0402_50V8J

KSI7

C1290 1

2 @ 100P_0402_50V8J

KSO10

C1291 1

2 @ 100P_0402_50V8J

KSI6

C1292 1

2 @ 100P_0402_50V8J

KSO3

C1293 1

2 @ 100P_0402_50V8J

KSI5

C1294 1

2 @ 100P_0402_50V8J

KSO4

C1295 1

2 @ 100P_0402_50V8J

KSI4

C1296 1

2 @ 100P_0402_50V8J

KSI0

C1297 1

2 @ 100P_0402_50V8J

KSO9

C1298 1

2 @ 100P_0402_50V8J

KSO0

C1299 1

2 @ 100P_0402_50V8J

KSI1

C1300 1

2 @ 100P_0402_50V8J

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 KSO16 KSO17

D40 2

NOVO#

1

NOVO_BTN#

3

ON/OFF

DAN202UT106_SC70-3

2

+3VLP

R1593 100K_0402_5%

GND1 GND2 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

28 27

JKB1 ACES_88514-02601-071

1

ON/OFFBTN#

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

ME@ J16 1

2

R1596 1 0_0402_5%

2

ON/OFF

SHORT PADS

+3VS

JTP1

2A/Active Low

ME@

+5VALW

C1301 8 7

0.1U_0402_16V4Z

6 5 4 3 2 1

TP_CLK TP_DATA SMB_CLK_S3 SMB_DATA_S3

@ D42 PSOT24C_SOT23-3 1

@

1

2

@

1

6 5 4 3 2 1

[37,39]

U55 1 2 3 4

USB_ON#

R02

GND VOUT VIN VOUT VIN VOUT EN FLG

W=80mils

8 7 6 5

USB_OC4#

G547I2P81U_MSOP8

470P_0402_50V7K 2

ACES_88514-00601-071 SP010014M00

2

+USB2_VCCA

LED Board

@

+3VALW +5VALW

PWR_LED# LID_SW#

2

NOVO_BTN# ON/OFFBTN# 3

[37] [37]

NOVO_BTN# PWR_LED# LID_SW# ON/OFFBTN#

8 7 6 5 4 3 2 1

8 7 6 5 4 3 2 1

G2 G1

+5VALW

ME@ 10 9

ACES_51524-0080N-001 SP01001A900

[37] [37]

BATT_LOW_LED# BATT_CHG_LED#

PWR_LED# BATT_LOW_LED# BATT_CHG_LED#

6 5 4 3 2 1

JLED1 ME@ 8 6 G2 7 5 G1 4 3 2 1

[36] [36]

ACES_51524-0060N-001 SP010014M10

D43 @ PJSOT24C 3P C/A SOT-23

[17] [17]

USB20_P8 USB20_N8

[17] [17]

USB20_P9 USB20_N9

[17] [17]

USB20_P10 USB20_N10

DMIC_CLK DMIC_DATA

+3VS

+3VS 0.1U_0402_10V6K C1306

IO Board

Power Board

JPWR1

[17]

1 C1321

1

2

0.1U_0402_10V6K C1307

SMB_CLK_S3 SMB_DATA_S3

0.1U_0402_10V6K C1305

2

[12,14,31] [12,14,31]

C1303 @ 100P_0402_50V8J 3

2

1

0.1U_0402_10V6K C1304

1

@ C1302 100P_0402_50V8J

2

TP_CLK TP_DATA

+USB2_VCCA

C1320 0.1U_0402_16V7K 1 2

@

+USB2_VCCA

1 JCR1 ME@

2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

DMIC_CLK DMIC_DATA

[36] [36] [36]

PLUG_IN# HP_OUTL HP_OUTR

PLUG_IN# HP_OUTL HP_OUTR

[36]

EXT_MIC

EXT_MIC

1

[37] [37]

GND GND

25 26

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GND1 GND2 ACES_88514-02401-071 SP010015W00

Compal Secret Data

Security Classification Issued Date

2011/06/15

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title Size C Date:

Compal Electronics, Inc. ROM/KBD/PWR/CR/LED/TP Conn. Document Number

Rev 0.1

Sherry and Royal Thursday, February 02, 2012

Sheet

38

of

55

5

4

3

2

1

D

D

0120 Swap

Intel_PCH_USB2.0

R1605

1

2 0_0402_5%

WCM-2012-900T_4P [17] [17]

C

1

USB20_P1

1

4

USB20_N1

2

4 L43 @ 1

3

R1609

[17]

USB3_RX2_N

[17]

USB3_RX2_P

U2DP2

3

U2DN2 C

2 0_0402_5%

R1608

Intel_PCH_USB3.0

2

USB3@ 1 2 0_0402_5%

+USB3_VCCA

WCM-2012-900T_4P

1

1

2

2

U3RXDN2

W=80mils JUSB1

4

3 U3RXDP2 4 3 L44 @ 1 2 R1612 0_0402_5% USB3@ 1

R1613

[17]

USB3_TX2_N

[17]

USB3_TX2_P

C1309 0.1U_0402_16V7K 1 2 U3TXDN2_L

1

1

4

2

U3TXDP2 U3TXDN2 U2DP2 U2DN2 U3RXDP2

2 USB3@ 0_0402_5%

U3RXDN2

WCM-2012-900T_4P

U3TXDP2_L

C1310 0.1U_0402_16V7K

1

2

4 L45 @

3

1 R1616

2

U3TXDN2

3

U3TXDP2

9 1 8 3 7 2 6 4 5

SSTX+ VBUS SSTXD+ GND DSSRX+ GND SSRX-

LP2

GND GND GND GND

10 11 12 13

TAITW_PUBAU1-09FNLSCNN4H0 ME@

2 0_0402_5% USB3@

B

B

Place TX AC coupling Cap (C843~C850). Close to connector

2A/Active Low +5VALW

@

+USB3_VCCA

D44

U3RXDN2 9 10

1

1U3RXDN2

U3RXDP2 8

9

2

2U3RXDP2

U3TXDN2 7

7

4

4U3TXDN2

U3TXDP2 6

6

5

5U3TXDP2

3

3

D45

3 C1308 0.1U_0402_16V7K 1 2 [37,38]

USB_ON#

U52

1 2 3 4

R02

W=80mils

8 7 6 5

GND VOUT VIN VOUT VIN VOUT EN FLG G547I2P81U_MSOP8

[17]

C1311 220U_6.3V_M

+

GND

VDD

I/O1

I/O3

6

U2DP2 0113 EMI request

U2DN2 8

1

I/O4

+USB3_VCCA

2 USB_OC0#

@

I/O2

1

5

4

AZC099-04S.R7G_SOT23-6

1 C1312

YSCLAMP0524P_SLP2510P8-10-9

470P_0402_50V7K

2

2

For EMI request

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/15

Deciphered Date

2012/07/11

Title

USB3.0/Left USB Ports

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev 0.1

Thursday, February 02, 2012 1

Sheet

39

of

55

A

B

C

+5VALW TO +5VS +5VALW

D

E

+3VALW TO +3VS

+5VS

+3VALW

+5VALW

+3VS

U53

2 PCH_PWR_EN

[15,37]

SLP_SUS#

R5534 1 2 0_0402_5%

1 2 0_0402_5% DS3@ R5537

+3VALW

2

C5529

1

1.5VS_GATE 1 1

2 0.1U_0402_16V4Z

2

1 47K_0402_5%

C1329 0.1U_0402_16V4Z

1

+5V_PCH

OUT

2MM QH6

2

2

G

1

0131 Add PD 10K PCH_PWR_EN#

2

1 @

2

3

R1594 10K_0402_5%

3

AO3413_SOT23 1

D

1

3

J21

RH228 20K_0402_5%~D

IN

CH57 0.1U_0402_10V7K~D

2

1

GND

SYSON

3

SYSON

@

@

2

S

R1639 @ 100K_0402_5%

2

2

0.1U_0402_25V6

3

R5533 2

1

2

1

1 3

PCH_PWR_EN#

+5VALW

@ Q100 DTC124EKAT146_SC59-3 [37,45,46]

IN

GND

2

SUSP#

1

0_0402_5%

C1328 S

1 2 SUSP G Q96 2N7002_SOT23 @

1

3

[10,37,45,46,47,49]

SYSON#

OUT

Q99 DTC124EKAT146_SC59-3

2 R1635 D

1

2

2

1

SUSP

@ R1638 100K_0402_5%

1

SUSP

Q98

1

2

100K_0402_5% R1633

SUSP# 2 G 2N7002_SOT23

1 @ R1637 100K_0402_5%

R1636 220K_0402_5%

[10,45,46]

+5VALW

1

2

+5VALW

3

R1631 470_0603_5% @

D

+3VALW

S

+RTCBATT

2

Q5510 AO3413_SOT23

1

1 C1327 1U_0402_6.3V6K

2

2

C1326 10U_0603_6.3V6M 10U

For Intel S3 Power Reduction.

J20

R5510 20K_0402_5%~D

2

1 2

1 C1325 10U_0603_6.3V6M

2

2

2 SUSP G Q95 2N7002_SOT23

S

3

3

[10,37]

2

1

1 1 2

1 2 3

1 2 3

D

2 SUSP G Q94 2N7002_SOT23 @

1

1 CPU1.5V_S3_GATE

1 2MM

D

S

2 1 @ R1630 0_0402_5%

2

+1.5VS

G

S

3

R1629 22_0603_5%

D

2 SYSON# G Q93 2N7002_SOT23 @

+3V_PCH @

S

S

D

2 SUSP G Q92 2N7002_SOT23 @

R1628 470_0603_5% @

Q91 PMV65XP_SOT23-3~D

G

D

R1627 470_0603_5% @

+1.5V_IO

1

C1323 0.01U_0402_25V7K

2

@

D

R1626 470_0603_5% @

R5529 100K_0402_5%

+0.75VS

S

2

+1.05VS_VTT

1

1

+1.5V_IO

Q5527

C5528 0.1U_0402_10V7K~D

3

S

+1.5V_IO to +1.5VS +1.8VS

S SB570020110 2N7002E-T1-E3_SOT23-3

2 R1623 0_0402_5%

Q89 2N7002_SOT23

S

D

2 G

1

D

2 G

SUSP

1

[37,42]

1

2 SUSP G Q86 2N7002_SOT23 @

1

3

1

PCH_PWR_EN#

2 1 C1322 0.01U_0402_25V7K

1

2

82K_0402_5% Q88 2N7002_SOT23

3

S R1621 470K_0402_1%

15VS_GATE_R

D

R1618 470_0603_5% @

2

3

5VS_GATE 2 R1622

2 G

SUSP

S

R5545 100K_0402_5%

D

+VSB

2 SUSP G Q85 2N7002_SOT23 @

1

1

2

R1620 150K_0402_5%

2

1

1

D

2

C1318 1U_0402_6.3V6K

1 2

R1617 470_0603_5% @

C1317 10U_0603_6.3V6M

3

10U

+VSB

1

1

1 C1316 10U_0603_6.3V6M

2

1 C1315 1U_0402_6.3V6K

4

2

C1314 10U_0603_6.3V6M

1 2

2

4

1

1

2

C1313 10U_0603_6.3V6M

1

DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5

1

U54 DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification 2011/06/15

2012/07/11

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

DC Interface Rev 0.1

Sherry and Royal

Thursday, February 02, 2012

Sheet E

40

of

55

5

4

3

2

1

VIN

1 2

PC104 1000P_0402_50V7K

1 2

PC103 100P_0402_50V8J

2

2

1

PL101 SMB3025500YA_2P 1 2

PC102 100P_0402_50V8J

PF101 7A_24VDC_429007.WRML 1 2 APDIN1

1

APDIN

PC101 1000P_0402_50V7K

D

JDCIN1 ACES_87302-0401-003 1 1 2 2 3 3 4 4 5 GND 6 GND

D

C

C

+3VLP

+

2

1

PR131 560_0603_5% 1 2

PR132 560_0603_5% 1 2

PD109 RB751V-40_SOD323-2 2 1

1

@ MAXEL_ML1220T10

2

PR127 0_0402_5% +RTCBATT

1

JRTC2

2

+CHGRTC

-

RTCVREF

PD108 RB751V-40_SOD323-2

RTC Battery

B

B

A

A

Compal Secret Data

Security Classification Issued Date

2010/01/25

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. PWR DCIN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

C38-G series Chief River Schematic0.1

Date:

5

4

3

2

Thursday, February 02, 2012

Sheet 1

41

of

55

5

4

VMB2

2

1

VMB PL201 SMB3025500YA_2P 1 2

BATT+

2

PC201 1000P_0402_50V7K

D

PC202 0.01U_0402_25V7K

For KB930 --> Keep PU201 circuit (Vth = 1.25V) For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206 PH201, PR205, PR211,PQ201,PR208,PR212

PH1 under CPU CPU thermal botten protection side : at 93 +-3 degree C EC_SMB_DA1

[37,43]

Recovery at 56 +-3 degree C VL

+3VALW

NTC_V_2

6

+3VLP

Turbo_V_2 2 @ PR227 0_0402_5% PR232 2

1

@ PR231 0_0402_5% 1

27.4K_0402_1%

2

ADP_OCP_2 1

2

PR210 5

PR230 2

1

@ 47K_0402_1% 2

1

MAINPWON

C

2

OTP_N_002

[37,44]

0_0402_5%

90W(DIS) : PR205=4.42K PR210=27.4K 65W(UMA) : PR205=402(SD034020080) PR210=5.11K

[37]

Turbo_V

PR213 0_0402_5%

PR233 2

100K_0402_1%_NCP15WF104F03RC PH201 1 2 2 1

3

PR212 0_0402_5% 1 2 @

PROCHOT

OT2 RHYST2

7

G718TM1U_SOT23-8

2 ADP_OCP_1 G S SSM3K7002FU_SC70-3

[37]

OT1 TMSNS2

8

PR211

4

GND RHYST1

1

PQ201

3

VCC TMSNS1

OTP_N_003

2 1

PR208 D

2

2

2

H_PROCHOT#

1

[37,6]

PU201 1

C

@

10K_0402_1%

+3VS

PC203 0.1U_0603_16V7K

2 1 PR206 12.7K_0402_1%

A/D 1

BATT_TEMP [37]

PR205 4.42K_0402_1%

1 2 PR204 10K_0402_5%

ADP_I

2 1 PR207 21.5K_0402_1%

+EC_VCCA [37,43]

2

1 2 PR203 6.49K_0402_1%

[37,43]

100K_0402_1%

1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 GND 9 GND @ SUYIN_200082GR007G201ZR

EC_SMB_CK1

1

JBATT2

1

2

2 1 PR202 100_0402_1%

2 1 PR201 100_0402_1%

1

1 1 2 2 3 EC_SMCA 3 4 EC_SMDA 4 5 5 6 6 7 7 8 GND 9 @ GND SUYIN_200082GR007G201ZR

1

PF201 12A_65V_451012MRL 1 2

JBATT1

D

3

1

1 PR209 10K_0402_1%

@ PR235 0_0402_5% 2 1 PR234 0_0402_5%

ECAGND

+3VALW

[37]

NTC_V

47K_0402_1%

B

B

S

VL

A

RTCVREF

PR225 10K_0402_1% @

SPOK

S [37,40]

PCH_PWR_EN

2

1 @ PR229

1

PR224 1K_0402_5% 2

0_0402_5% 2

1 PR228 0_0402_5%

[37]

1

1 [44]

1

2 PR226 100K_0402_1%

2 G 3

PR223 10K_0402_1% 2 1

2VREF_8205

1

1

PQ203 D 2N7002KW_SOT323-3

2

1

1

+3VLP

2

1 2

PC206 0.1U_0603_25V7K

2

1 2

+VSBP

@ PR222 100K_0402_1%

D

3

PU202A LM393DG_SO8

1

2

2 G

PC205 0.22U_0603_25V7K

1 PQ202 D 2N7002KW_SOT323-3

PR220 22K_0402_1% 1 2

S

2 G PC207 1U_0402_6.3V6K

-

1

1 P O

2 1 PR216 100K_0402_1%

2

2 1

BATT_OUT [43]

3

2

+

3

B+ PR215 100K_0402_1%

8 3

PR221 221K_0402_1%

2

PQ205 TP0610K-T1-E3_SOT23-3

+3VALW

PR214 100K_0402_1%

PR218 10M_0402_5% 1

PR219 10K_0402_1% 1 2

G

PR217 768K_0402_1%

4

2

1

2

2

VMB2

+3VLP

PC204 0.01U_0402_25V7K

1

P2

PQ204 2N7002W-T/R7_SOT323-3

+VSBP

PJ201 @ JUMP_43X39 1 2 1 2

+VSB

A

BATT_LEN#

Compal Secret Data

Security Classification Issued Date

2010/01/25

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. PWR-BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

C38-G series Chief River Schematic0.1

Date:

5

4

3

2

Thursday, February 02, 2012

Sheet 1

42

of

55

5

4

3

2

1

B+

P3 P2 PQ301 AO4407A_SO8

PQ302 AO4423_SO8

1 2 3

PC307 2200P_0402_50V7K

PC306 4.7U_0805_25V6-K 1 2

2 1

2

2

PC304 5600P_0402_25V7K

PQ303 AO4407A_SO8

PC305 4.7U_0805_25V6-K 1 2

PL301 1UH_MNR-4018-1R0N-F_3A_30%

2

3

1

2

1

DISCHG_G

VIN

SRN

BM

17

PD303 16

2

2

REGN

4 1

1

PR324 PC314 2.2_0603_5% 0.047U_0603_16V7M 1 2 2 1

BST_CHG

2

2

1

15

14

PR328 10_0603_5%

13 1 2

11

RB751V-40_SOD323-2 PC376 1U_0603_25V6K

BQ24727VDD

DL_CHG

PC373 0.1U_0603_25V7K 2 1

2 1

2

3

1 CHG

4

2

3

PR322 4.7_1206_5%

BTST

PR326 100K_0402_1%

1

DH_CHG

16251_SN 2

ILIM

18

C

PL302 10UH_PCMB063T-100MS_4A_20% PR320 0.01_1206_1%

LX_CHG HIDRV

SA000051W00

SCL

1U_0603_25V6K

19

PACIN

SRP

BATT+

SRN

PC372 10U_0805_25V6K 2 1

PHASE

2 G S

2

IOUT PU301 SDA BQ24727RGRR_VQFN20_3P5X3P5

2N7002W -T/R7_SOT323-3

PC371 10U_0805_25V6K 2 1

BQ24727VCC1

1

PC311 0.1U_0603_25V7K 2 1

5 6 7 8 4

PC313 20

PQ310 AO4466L_SO8

21

1

ACN TP

PR319 10_1206_5% 2

1

2 ACP

3

4 CMPIN

CMPOUT



VCC

B

2ACOFF-1

1

1

2

D

PC377 680P_0603_50V7K

10

PD301

1DISCHG_G-1 1

PQ309 P2

PQ312 AO4466L_SO8

PR323 1 2 316K_0402_1%

PD302 1SS355_SOD323-2 2

PC310

3 2 1

9

1

3

PR310 2 1 10K_0603_1%

2

5 6 7 8

EC_SMB_CK1

PR306 200K_0402_1%

1

3 2 1

[37,42]

PQ306 DTC115EUA_SC70-3

0.1U_0603_25V7K

LODRV

7

100P_0603_50V8 8

ACDET

6.8_0603_5% 2 1 12 PR327

3

S

2

0.1U_0603_25V7K

PR313 @ @ 1 2 4.7M_0603_1%

5

PC370 0.1U_0603_25V7K

EC_SMB_DA1

3

2 1

D

PC312 1 2

2N7002KW_SOT323-3

PQ313 2 G

BATT_OUT

6

[37,42]

+3VALW

1

ADP_I

@

64.9K_0603_1%

PR321 1 2ACOFF-12 10K_0402_5%

PC309

39.2K_0402_1%

1

@

2

SRP

[37,42]

2

@ PR312 2

ACOK

PR315 2.2K_0402_5% 1 2 PR316 2.2K_0402_5% 1 2

PR314 2 1 390K_0603_1%

PR317 1

PR325 0_0402_5%

[42,43]

PR309 2 @

VIN

1

ACOFF

[42,43]

1

[37]

1

S

2

PQ311 DTC115EUA_SC70-3

1

ACON

+3VALW

ACPRN

3

1 4

5

PR308 150K_0402_1%

2 P2-2 3

PQ307B

PR318 47K_0402_1% 1 2

PACIN

PQ308 2N7002KW _SOT323-3 2 BATT_OUT G

D

2N7002KDW-2N_SOT363-6

1 C

1 2

3 6 PQ307A 2N7002KDW -2N_SOT363-6

PACIN

[43]

PR307 20K_0402_1%

100K_0402_1%

DTC115EUA_SC70-3

PC308

GND

1

+3VALW

0.1U_0603_25V7K

1

P2-1

PR305 47K_0402_1%

1

1

2

ACN

2

2

D

PR304 200K_0402_1% 1 2

ACP

PQ305

8 7 6 5

1SS355_SOD323-2

1

2

PC301 0.1U_0603_25V7K 2 1 PR303 200K_0402_1%

3

2

2

1 PR301 47K_0402_5%

1 DTA144EUA_SC70-3

2

PC303 4.7U_0805_25V6-K 1 2

1

PQ304

D

CHG_B+

SH00000Q100 4

4

PR302 0.01_1206_1% 1

PC315 @ 10U_0805_25V6K

8 7 6 5

PC302 @ 10U_0805_25V6K

1 2 3

4

1 2 3

4

8 7 6 5

VIN

B

0V

1

CHGVADJ

PC374 0.1U_0603_25V7K

2

4V

2

Vcell

1

CHGVADJ=(Vcell-4)/0.10627

4.2V

1.882V

4.35V

3.2935V

@ PC375 0.1U_0603_25V7K

BQ24727VDD PR337 10K_0402_1% 1 2 PR336 10K_0402_1%

PR335 47K_0402_1%

[43]

PQ316

1

ACPRN

D

3

2 G

A

ACIN

[15,23,37]

PACIN

S

1 PR339 2

2

VCHLIM need over 95mV

2

IREF=0.254V~3.048V

2N7002KW_SOT323-3

IREF=1.016*Icharge

1

1

CC=0.25A~3A

12K_0402_1%

A

For disable pre-charge circuit.

2010/01/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/07/11

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

CHARGER Document Number

Rev 0.1

C38-G series Chief River Schematic Thursday, February 02, 2012

Sheet 1

43

of

55

5

4

3

2

1

Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205

PJ402

2

+3VALW P

2

1

1

+3VALW

PC401 1U_0603_10V6K

@ JUMP_43X118

1

D

PJ403

2

+5VALW P

2

D

RT8205_B+ PJ401

PR404 19.6K_0402_1% 1 2

1

+5VALW

RT8205_B+

5 6 7 8

PC410 0.1U_0603_25V7K 2 1

PR408 PC413 2.2_0603_5% 0.1U_0603_25V7K 2 1 2 BST_5V 1

21

UG_5V

20

LX_5V

19

LG_5V

3 2 1

22

1 5 6 7 8

2 PC422 0.1U_0603_25V7K

5

2VREF_8205 4

1

2

PC421 4.7U_0805_10V6K

1 2 1

RT8205_B+

PQ405B 2N7002KDW -2N_SOT363-6

2

1

1 2 3 2 1

TPC8A03-H_SO8

PC420 1U_0603_10V6K 2 1

VL

+5VALWP

+

4

Typ: 175mA

PC419 680P_0603_50V7K

RT8205EGQW _W QFN24_4X4

PR410 4.7_1206_5%

PL402 4.7UH +-20% PCMC063T-4R7MN 5.5A 1 2

1 2

3

6

ENTRIP2

C

TPC8065-H_SO8

PQ402

PC409 2200P_0402_50V7K 2 1

SPOK [42]

18

17

23

PQ404

LGATE1

NC

LGATE2 VREG5

PHASE1

VIN

UGATE1

PHASE2

13

PC408 4.7U_0805_25V6-K 2 1

1 ENTRIP1

3

4

2 FB1

REF

FB2

UGATE2

24

B+

ENTRIP1

PQ405A 2N7002KDW -2N_SOT363-6

TONSEL

VFB=2.0V

PC407 4.7U_0805_25V6-K 2 1

ENTRIP1

ENTRIP2

5

6

BOOT1

PR411 499K_0402_1% 1 2

B

PC417 150U_B2_6.3VM_R45M

2

B

+3.3VALWP OCP(min)=5.81A +5VALWP OCP(min)=8.44A

PR414 100K_0402_1% 2 1

VL

[37] EC_ON

PGOOD

BOOT2

4

1 2 3

2

12

4

VREG3

EN

PQ403 AO4712_SO8

PC415 150U_B2_6.3VM_R45M

PC418 680P_0603_50V7K 2 1

+

LG_3V

PR412 100K_0402_1%

1

8 7 6 5

PR409 4.7_1206_5% 2 1

PL401 4.7UH +-20% PCMC063T-4R7MN 5.5A 1 2

PR406 66.5K_0402_1% 2

VO1

16

1 2 3

PR407 2 1 2 BST_3V 9 2.2_0603_5% PC412 UG_3V 10 0.1U_0603_25V7K 11 LX_3V

1

VO2

GND

8

SKIPSEL

7

+3VALWP

P PAD

1

15

4

25

ENTRIP2

AO4466L_SO8

PU401

1

PQ401

PR405 130K_0402_1% 1 2

2

8 7 6 5

PC411 4.7U_0805_10V6K

+3VLP PC406 2200P_0402_50V7K 2 1

C

PR403 20K_0402_1% 1 2

14

1

1

PC404 4.7U_0805_25V6-K 2 1

2

@ JUMP_43X118

PC403 4.7U_0805_25V6-K 2 1

2

PR402 30K_0402_1% 1 2

1

Typ: 175mA PC402 0.1U_0603_25V7K 2 1

PC405 0.1U_0603_25V7K 2 1

B+

PR401 13K_0402_1% 1 2

2

JUMP_43X118

@

1

PR418 2.2K_0402_5% 2 1

PR413 0_0402_5% 2 1

2

PQ406 DTC115EUA_SC70-3 A

3

1

2 2 1 PR417 40.2K_0402_1%

A

PC423 4.7U_0603_6.3V6M

[37,42] MAINPWON

Compal Secret Data

Security Classification 2010/01/25

Issued Date

@

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. 3VALWP/5VALWP

Size Document Number Custom

C38-G series Chief River Schematic

Date:

Thursday, February 02, 2012

Sheet 1

44

of

55

Rev 0.1

A

B

C

D

@PJ501 @ PJ501 1

VTT_REFP On

S3

Lo

Hi

On

On

Lo

Lo

Off

Off

0.75VSP On Off (Hi-Z)

+1.5VP

PQ503 TPCA8065-H_PPAK56-8-5

PJ5025 @ JUMP_43X39

B+

2

JUMP_43X118

1.05VS_B+

3 2 1

1

2

LX_1.5V

1

1

Off

1

4

UG_1.5V

S4/S5

1

On

PC501 4.7U_0805_25V6-K

1.5VP

2

Hi

1

S5

Hi

2

S3

S0

5

STATE

PC509 4.7U_0805_25V6-K

1.05VS_B+

1

2

Note: S3 - sleep ; S5 - power off 2

PR507 PC502 2.2_0603_5% 0.1U_0603_25V7K 1 2 BST_1.5V-1 1 2

BST_1.5V

1 VDD

13

1

3 2 1

11

2 1 PR502 5.1_0603_5%

+3VALW

2 1 2

+5VALW 2

PC511 1U_0603_10V6K

@

PGOOD_1.5V

S

PJ505 2

+1.5VP

@

2

1

1

+1.5V_IO

JUMP_43X118

2

3

PC505 330U_D2_2.5VY_R15M

12

FB=0.75V To GND = 1.5V To VDD = 1.8V

1

D

PR508 5.76K_0402_1%

[10,40,46] SUSP

+ 2

PC510 @ 680P_0402_50V7K

PR510 5.9K_0402_1% 2 1

2 1

PQ501@ 2N7002KW _SOT323-3 2 G

1

PR501 887K_0402_1% 2 1 1.05VS_B+

@ PC508 0.1U_0402_16V7K

2

PC512 1U_0402_16V6K

1

[37,40,46] SYSON

PR505 11K_0402_1% 2 1

PQ502 TPCA8057-H_PPAK56-8-5

14

10

8 S5_1.5V

PR504 0_0402_5% 1 2

9

7

6

S3_1.5V

PR503 0_0402_5% 1 2

4

LG_1.5V

PR506 @ 4.7_1206_5%

1

PGOOD

TON

S3

S5

VDDQ

15

2

,45,46,47,49] SUSP#

+1.5VP

5

16 PHASE

17 UGATE

18

VDDP

FB

1

CS

RT8207MZQW _W QFN20_3X3

VTTREF

5

2

PGND



2

GND

4

PC507 0.033U_0402_16V7K

LGATE

VTTSNS

3

+1.5VP



2 1 PR509 10K_0402_5% PC503 1U_0603_10V6K 2 1

2

+VTT_REFP

19

VTTGND

BOOT

PAD

1

VLDOIN

20

PU501 21

VTT

1 2

PC504 10U_0805_25V6K

2

1

PC506 10U_0805_25V6K

+0.75VSP

PL502 1UH_PCMC063T-1R0MN_11A_20% 1 2

PJ506 2 @

2

1

1

+1.5V

JUMP_43X118

3

3

PJ507 1

+0.75VSP

1

2

PR514 1M_0402_5%

2

1

PC517 22U_0805_6.3VAM

1 2

PC516 22U_0805_6.3VAM

SY8033BDBC_DFN10_3X3

PR512 20K_0402_1%

2

+0.75VS

+1.8VSP PC514 68P_0402_50V8J 2 1

FB=0.6Volt

1

1

6

2

PJ503 2

+1.8VSP

2

@

1

1

+1.8VS

JUMP_43X118

1.8VSP max current=4A 1.8VSP_FB 1

2

0_0402_5%

1.8VSP_LX

3

2

FB EN

TP

EN_1.8VSP

1

2

2

SVIN

11

PR513 1

PC518 @ 0.1U_0402_10V7K

[10,37,40,45,46,47,49] SUSP#

LX

1 2

2

5

LX

PVIN

2

8

PC513 22U_0805_6.3VAM

PVIN

PC515 PR511 680P_0603_50V7K 4.7_1206_5%

9

NC

10

1.8VSP_VIN

NC

1

1

1

7

2

JUMP_43X118 1

@

PG

PJ504 2

+5VALW

PL501 1UH_PH041H-1R0MS_3.8A_20% 1 2

4

PU502

1

JUMP_43X39 @

PR515 10K_0402_1%

4

2

4

Compal Secret Data

Security Classification Issued Date

2010/01/25

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. PWR-+1.5VP/+1.8VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

C38-G series Chief River Schematic

Date:

A

B

C

Thursday, February 02, 2012 D

Sheet

45

of

55

A

B

C

D

@

VTT_REFP On

S3

Lo

Hi

On

On

0.75VSP On Off (Hi-Z)

+1.5VP_DDR3L

PQ504 TPCA8065-H_PPAK56-8-5

Lo

Lo

Off

Off

Off

1

PJ509 2

B+

2

JUMP_43X118

PJ508 LX_1.5V_DDR3L

JUMP_43X39

3 2 1

1

1

S4/S5 1

1

4

UG_1.5V_DDR3L @

1

On

PC519 4.7U_0805_25V6-K

1.5VP

2

Hi

1

S5

Hi

2

S3

S0

5

STATE

PC520 4.7U_0805_25V6-K

1.5V_B+_DDR3L

1

2

Note: S3 - sleep ; S5 - power off 2

PR516 PC521 2.2_0603_5% 0.1U_0603_25V7K 1 2 BST_1.5V-1_DDR3L 1 2 BST_1.5V_DDR3L

13

3 2 1

PR518 11K_0402_1% 2 1

2

1 +

1 2

14

PQ505 TPCA8057-H_PPAK56-8-5

5

16

11

2 1 PR519 5.1_0603_5%

+5VALW

1

+3VALW

2

PC528 1U_0603_10V6K

PGOOD_1.5V_DDR3L

PJ510 2 @

2 1

D

FB=0.75V To GND = 1.5V To VDD = 1.8V

2

1

1

JUMP_43X118 PJ511

2

+1.5VP_DDR3L

@

2

+1.5V 1

1

JUMP_43X118

S 1

1

3

[10,40,45] SUSP

PC524 330U_D2_2.5VY_R15M

2

PC525 680P_0402_50V7K

12

2

PHASE

4

PR524 10K_0402_1% 2 1

1

1 2

LG_1.5V_DDR3L

PR517 4.7_1206_5%

PR523 887K_0402_1% 2 1 1.5V_B+_DDR3L

PC530 0.1U_0402_16V7K PQ506 2N7002KW _SOT323-3 2 G

+1.5VP_DDR3L

1 PR522 0_0402_5% 1 2

VDD

15

2 1 PR520 10K_0402_5% PC527 1U_0603_10V6K 2 1

FB 6

PR521 0_0402_5% @ 1 2

PC529 1U_0402_16V6K

17

VDDQ

PC526 0.033U_0402_16V7K

CS VDDP

+1.5VP_DDR3L

[37,40,45,46] SYSON

UGATE

BOOT

VTTREF

2

,40,45,47,49] SUSP#

18

19

20

RT8207MZQW _W QFN20_3X3

8 S5_1.5V_DDR3L S5

2

1

5

GND

PGND

PGOOD

4

VTTSNS

10

+VTT_REFP_DDR3L

LGATE

TON

3

VTTGND

9

2

PAD

VLDOIN

1

VTT

PU503 21

7 S3_1.5V_DDR3L S3

1 2

PC523 10U_0805_25V6K

1 2

PC522 10U_0805_25V6K

+0.75VSP_DDR3L

PL1 1UH_PCMC063T-1R0MN_11A_20% 1 2

PJ512

PR526

PR525

DDR3L_EN#

S

2

2

+0.75VS

3

2

D

1

JUMP_43X39 @

2

PQ507 2N7002KW _SOT323-3 1 2 2 0_0402_5% G PR527 PC531 @ 0.1U_0402_16V7K 1

[18]

1

3

@ PR528 0_0402_5% 1 2

3

[37,40,45,46] SYSON

2

49.9K_0402_1%

1

+0.75VSP_DDR3L

12.7K_0402_1%

DDR3L_EN#=high DDR3L_EN#=low

=> =>

1.5V 1.35V

4

4

Compal Secret Data

Security Classification Issued Date

2010/01/25

Deciphered Date

2012/07/11

Title

Compal Electronics, Inc. PWR-+1.5VP/+1.8VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

C38-G series Chief River Schematic

Date:

A

B

C

Thursday, February 02, 2012 D

Sheet

46

of

55

5

4

3

2

1

D

D

10

TPCA8057-H_PPAK56-8-5

2

DL_1.05VS_VCCP

PR720

2

10_0402_5% 0.01UF_0402_25V7K @

1

2

10_0402_1%

PC721 1U_0603_10V6K

1 2

3 2 1

PGND 8

7

TRIP 6

+5VALW

1

2

9

2

1

1

5

PC720

2

GND

V5 COMP

VSNS

PC715 4.7U_0805_25V6-K 2 1

C

+1.05VS_VTTP

PC718 330U_X_2VM_R9M

PQ704

DL

PR721 75K_0402_1% 2 1

1

PC712 4.7U_0805_25V6-K 2 1

PC711 0.1U_0402_25V6 2 1

1

TPS51219RTER_QFN16_3X3

4

PR719

VCCIO_SENSE

5

DH_1.05VS_VCCP

0_0402_5%

[9]

PL2 1UH_PCMC063T-1R0MN_11A_20% 1 2

PC719 PR717 1000P_0603_50V7K 4.7_1206_5%

11

LX_1.05VS_VCCP

3 2 1

12

5

DH

GSNS

4

PC714 2200P_0402_50V7K 2 1

13

4

SW

REFIN

3

1.05VS_B+

BST

14

MODE

EN

15

16

1 2

2 PC717 0.01UF_0402_25V7K

PGOOD

PAD

17

10.7K_0402_1% PR715 2

1

VREF

PC713 0.1U_0603_25V7K 1 2

1.05VS_B+

1

2

12K_0402_1%

PR718

1

1

1

VSSIO_SENSE_L

PR716 2

[9]

PC716 0.1U_0402_25V6 2 1

C

PU702

PQ703 TPCA8065-H_PPAK56-8-5

PR714 2.2_0603_5% 1 2 BST_1.05VS_VCCP

1

PR712 2

100K_0402_1%

PR711 100K_0402_1% 2

1 2

PR713 0_0402_5% 1 2

+V1.05S_VCCP_PW RGOOD

+1.05VS_VCCPP OCP(min)=20.75A

+3VS

PC710 .1U_0402_16V7K

2 PR710

1 [48]

@ 10K_0402_1%

PR709 60.4K_0402_1% 1 2

[10,37,40,45,46,49] SUSP#

1 +

2

PC722 1000P_0402_50V7K PR722

B

1

B

2

1

2

10_0402_1% PC723 1000P_0402_50V7K

PJ705

2

2

1

1

@ +1.05VS_VTTP

JUMP_43X118 PJ706 2 1 2 1

@

+1.05VS_VTT

JUMP_43X118

A

A

Compal Secret Data

Security Classification 2010/01/25

Issued Date

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

Title

Compal Electronics, Inc. PWR +1.05VS_VCCPP/

Size Document Number Custom

C38-G series Chief River Schematic

Date:

Thursday, February 02, 2012

Sheet 1

47

of

55

Rev 0.1

4

3

+3VS PR602 100K_0402_5% 1

SW

24

PC620

PL601 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% 1 2

7

PC612 22U_0805_6.3V6M 1 2

@

PC611 22U_0805_6.3V6M 1 2

PC604 1000P_0603_50V7K

@

PC609 22U_0805_6.3V6M 1 2

8

@

PC608 22U_0805_6.3V6M 1 2

PR607 4.7_1206_5% 9

+VCCSAP PC607 0.1U_0402_10V7K 2 1

1

10

@

6

VREF

3

1

COMP

JUMP_43X118

MODE

VIN VOUT

+VCCSA_PWR_SRC

SLEW

+VCCSA_PWR_SRC

+VCCSA_PHASE

1

SW

5

1

11

PR606 PC603 0_0603_5% 0.22U_0603_16V7K 2+VCCSA_BT_1 1 2

VIN

4

1

+VCCSA_BT 1

VIN

GND

@

2

12

2

SW

PJ601 2

+VCCSA

1

[47]

PC605 22U_0805_6.3V6M 1 2

SW TPS51463RGER_QFN24_4X4

23

1

13 EN BST

PGND

22

1

+V1.05S_VCCP_PWRGOOD

PGND

21

2

2

JUMP_43X118

D

PC610 2200P_0402_50V7K 2 1

1

10U_0805_6.3V6M PC616

10U_0805_6.3V6M PC615

2

@

The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability.

PR605 0_0402_5% 1 2

+VCCSA_EN

SW

2

C

2

0.1U_0603_25V7K PC614 1 2

2200P_0402_50V7K PC613

+3VALW

1

+VCCSA_VID0

+VCCSA_VID1

PGND

20

@

PJ602 2

+VCCSAP

[10]

PC606 22U_0805_6.3V6M 1 2

19

V5FILT

V5DRV

PU601

PGOOD

PC602 2.2U_0603_10V7K 1 2

14

17

15

1

18

2 PR604 10_0402_1% 2 1

PC601 1U_0603_10V6K

+VCCSA_PWRGD

+5VALW

1

2

16

D

1

+VCC_SAP TDC 4.2A Peak Current 6A OCP current 7.2A

[10]

H_VCCSA_VID0 PR603 1K_0402_5% 2 1

VID0

output voltage adjustable network

SA_PGOOD

VID1

[37]

H_VCCSA_VID1

0.033U_0402_16V7K

VCCSA Vout 0.9V 0.85V 0.775V 0.75V

2

VID[1] 0 1 0 1

+VCCSA_PWRGD

VID [0] 0 0 1 1

2

PR601 1K_0402_5% 2 1

2

5

TP

25

C

@

PR608 2

1

33K_0402_5% PR609 100_0402_5% 2 1 2

1

2

1

PR610 5.1K_0402_1%

PR611 0_0402_5% 2 1

PR612 @ 0_0402_5%

+VCCSA_SENSE

[10]

2

PC618 3300P_0402_50V7K

1

0.22U_0402_10V6K

PC619 0.01U_0402_25V7K 1 2

PC617 2 1

B

B

A

A

Compal Secret Data

Security Classification Issued Date

2010/01/25

Deciphered Date

2012/07/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PWR +VCCSAP Size C Date:

5

4

3

2

Compal Electronics, Inc. Document Number

C38-G series Chief River Schematic Thursday, February 02, 2012

Sheet 1

48

of

55

Rev 0.1

A

B

C

+VGA_COREP

D

@ 2

VGA_CORE_B+

PJ801 2

1

1

B+

JUMP_43X118

2

GPU_VID0

PR824 0_0402_5% 1 2

[23]

GPU_VID1

GPU_VID1

PR825 0_0402_5% 1 2

3 2 1 16

1

1

2

1

2

1

2

PC814 10U_0603_6.3V6M

2

PC813 10U_0603_6.3V6M

+

2@

PC812 10U_0603_6.3V6M

1

PC811 470U_D2_2VM_R4.5M

+

PC810 470U_D2_2VM_R4.5M

2 PC815 680P_0603_50V7K

1

2

1

2

PC809 470U_D2_2VM_R4.5M

1 PQ802 TPCA8057-H 1N PPAK56-8

3 2 1

PC816 0.1U_0603_25V7K 2 BOOT2_2_VGA1

+

EN 10

VID1

VID0

9

LGATE2_VGA

+VGA_COREP Iocp=32.5A

PJ802 2

+VGA_COREP

Seymour

2

1

1

+VGA_CORE

@ JUMP_43X118

GPU_VID1

GPU_VID0

Core Voltage Level

1

1

0.9V

1

0

1.0V

0

1

1.05V

0

0

1.12V

2

@ PR813 33K_0402_5% 2

1

PR808 2.2_0603_5% 2 1

11 BOOT2_VGA

1 PR806 4.7_1206_5%

2

8

7

VREF 1

6

97.6K_0402_1% 2

12

2

1

1

@ JUMP_43X118

VRON_VGA

+1.5V_IO +5VALW

2

1

1

+1.0VGS

JUMP_43X79 @

2

PC819 1U_0402_6.3V6K

2

2

PC818 0.1U_0402_16V7K

2

+VGA_PCIEP

PJ804 JUMP_43X79

2

0_0402_5%

3

PJ805

@

1

PXS_PWREN

4

UGATE2_VGA

1

PXS_PWREN

PR811

GPU_VID0

PR815 [17,24,49]

13

1

SUSP#

PC808 1U_0603_10V6K

2

[10,37,40,45,46,47]

14

PJ803

[23]

PR814 @ 0_0402_5% 1 2

3

MODE BST

2 PX_MODE

17

SW

V0

1 1

DRVH

TPS51518RUKR_QFN20_3X3

V1

10K_0402_1%

VGA_PWRGD

GND

1 V2

PGOOD

4

1 1 2

DRVL

+VGA_COREP

+5VALW

1

[18,22]

15

PC817 0.1U_0402_10V7K

PR809 7.68K_0402_1%

V3

+3VS

PR812 0_0402_5% 1 2

18 PC807 1

V5IN

2

21 PR807 5.11K_0402_1%

3

5

PR810

2

GSNS

PL801 0.36UH_PCMC104T-R36MN1R17_30A_20% 1 2

5

2 PR805 11.8K_0402_1%

2

21

100K_0402_1%

1

TRIP

1

VSNS

PAD

PU801 PR804

4

PR803 41.2K_0402_1%

SLEW

20

21

10P_0402_25V8J

PC805 4.7U_0805_25V6-K

5 2 1 4700P_0402_25V7K 19 1 2

PC801

PR801 0_0402_5% 1 2

2

PQ801 TPCA8065-H_SOP-ADV8-5

10P_0402_25V8J 1 2

PC806 2

2

PC802 0.1U_0402_25V6 2 1

1 PR802 0_0402_5%

PC804 4.7U_0805_25V6-K 2 1

1

PC803 2200P_0402_50V7K 2 1

1

1 PXS_PWREN

1

2

8

PR816 40.2K_0402_1%

EN

1

FB VIN

+VGA_PCIEP

3 2 9

PR817 1.15K_0402_1%

APL5912-KAC-TRL_SO8

PR818 20K_0402_1% 2

VGA_PCIE

1.0V

1.1 V

PR819

4.53K

3K

PC821 0.01U_0402_25V7K

PR819 4.53K_0402_1% 2

@

PC822 0.1U_0603_25V7K 2 1

1

PXS_PWREN

4

PC823 22U_0603_6.3V6K 2 1

VOUT VOUT

[17,24,49]

PC820 4.7U_0805_6.3V6K

1

PR823 10K_0402_5% 1 2

5

1

GPU_VID1

VIN

2

PR821 10k_0402_5% 1 2

POK

2

PU802 7

1

@

+3VS

PD801

RB751V-40_SOD323-2 1 2

6

@

2

PR822 10K_0402_5% 1 2

VCNTL

GPU_VID0

GND

@ PR820 10k_0402_5% 1 2

+3VS

4

4

Compal Secret Data

Security Classification Issued Date

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title Size Date:

A

B

C

Compal Electronics, Inc. PWR-VGA_CORE/VGA_PCIE Document Number

Rev 0.1

Thursday, February 02, 2012 D

Sheet

49

of

55

2

1

PL901 HCB4532KF-800T90_1812 1 2

+CPU_CORE [9]

VCCSENSE

[9]

VSSSENSE

PC917 10U_0805_25V6K 2 1

PC916 10U_0805_25V6K 2 1

3

2 1 PR915 1_0402_5%

C

PC928 10U_0805_25V6K 2 1

PC926 10U_0805_25V6K 2 1

PC927 10U_0805_25V6K 2 1

3

B

+CPU_CORE

1

4

2

PR945 1_0402_5%

PR944 3.65K_0603_1% VSUM- 2

5

1

1 VSUM+

LGATE1

MDU1511RH_POWERDFN56-8-5

VSUM-

4

3 2 1

4

PQ905

@ PC939 330P_0402_50V7K 2 1

2 1

+CPU_CORE: VID1=0.9V IccMax=33A Icc_TDC=25A Icc_Dyn=28A OCP~40A

1

PC940 0.01UF_0402_25V7K

@ PR947 10_0402_1%

Compal Secret Data

Security Classification Issued Date

2009/12/01

2012/07/11

Deciphered Date

Title

PWR-CPU_CORE

Date:

4

3

A

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

+VGFX_CORE

PL903 0.36UH_VMPI1004AR-R36M-Z03_30A_20%

PC936 680P_0402_50V7K 2 1 2 1 PR938 4.7_1206_5%

5

PQ906

LGATE1

1 PR936

12

2

Rds(on) typ=2.6m Ω max=3.2m Ω

10K_0402_1%_ERTJ0EG103FA

PC938 2 1

4

2

2

2

A

4

PC931 0.22U_0603_16V7K

Close Phase 1 choke

2

1 @ PR946 10_0402_1%

PR937 2.2_0603_5% 1 1 BOOT1 2

PH904

2

PC937 150P_0402_50V8J 1 2 1 PR943 137K_0402_1%

PHASE1

0.1U_0402_16V7K

PR942 1.91K_0402_1% 2 1

2.61K_0402_1%

1 11K_0402_1% 2 PR940

1

1

1 PR941 499_0402_1%

PC934 0.1U_0603_16V7K PC932 0.047U_0402_16V8J 1 2

PC935 68P_0402_50V8J 2 1

2

PC933 470P_0402_50V7K 2 1 2

@ PC930 10P_0402_50V8J 2 1

2

PR935 42.2K_0402_1% 2 1

4

UGATE1



PQ904

3 2 1

PQ903

+3VS

MDU1511RH_POWERDFN56-8-5

1.91K_0402_1% 1

5

PR933 2

[15]

3 2 1

VGATE

5

PR932 0_0402_5% 1 2

MDU1516URH_POWERDFN56-8-5

CPU_B+

+5VS

PC925 10U_0805_25V6K 2 1

2

ISL95836HRTZ-T_TQFN40_5X5~D

MDU1516URH_POWERDFN56-8-5

1 BOOT1

1

For ULV 17W 1+1 CPU_CORE LL= -2.9mΩ, GFX_CORE LL= -3.9mΩ, L DCR=1.1mΩ

PC921 1U_0603_10V6K

2 UGATE1

PR939 475_0402_1%

PR934 2K_0402_1% 2 1

3 2 1

1

1 LGATE1 PHASE1

VSUM+

1

Rds(on) typ=2.6m Ω max=3.2m Ω

PR919 1_0603_5%

2

PR918 0_0603_5%

B

PC929 470P_0402_50V7K 2

2

40 39 38 37 36 35 34 33 32 31 ISUMNG RTNG FBG COMPG PGOODG PWM2G LGATE1G PHASE1G UGATE1G BOOT1G

11 12 13 14 15 16 17 18 19 20

TP

@

VSUMG-

PC919 0.22U_0603_16V7K 4 PR916 2.2_0603_5%

BOOT1G

30 29 28 27 26 25 24 23 22 21

@

2 PR914 3.65K_0603_1%

BOOT1G

BOOT2 UGATE2 PHASE2 LGATE2 VCCP VDD PWM3 LGATE1 PHASE1 UGATE1

+

2

+VGFX_CORE: VID1=1.23V IccMax=33A Icc_TDC=21.5A Icc_Dyn=20.2A OCP~40A

1 PR913 4.7_1206_5%

PQ902

UGATE1G

PC922 1U_0603_10V6K 2 1

PR930 27.4K_0402_1%

41

ISUMPG ISEN1G ISEN2G NTCG SCLK ALERT# SDA VR_HOT# VR_ON NTC

2

1

PL902 0.36UH_VMPI1004AR-R36M-Z03_30A_20%

3 2 1

@ PC924 0.1U_0402_16V7K

1 2 3 4 5 6 7 8 9 10

PR931 3.83K_0402_1%

2

1

2

+1.05VS_VTT

PH903 470K_0402_5%_ TSM0B474J4702RE 2 1 2 1

1

@

ISEN2G NTCG SCLK ALERT# SDA

1

@

2

@ PC923 47P_0402_50V8J

2 PR926 0_0402_5% 1 2 PR927 130_0402_1% 1 2 PR928 75_0402_5% 1 2 PR929 54.9_0402_1%

VR_SVID_CLK VR_SVID_ALRT# [9] VR_SVID_DAT [37] VR_HOT# [37] VR_ON

1

[9] [9]

+5VS

PH902

2

+

PC920 680P_0402_50V7K 2 1 2

2

PHASE1G

ISEN3/FB2 ISEN2 ISEN1 ISUMP ISUMN RTN FB COMP PGOOD BOOT1

PR921 0_0402_5% 1 2 1 1 2 470K_0402_5%_ TSM0B474J4702RE 1 2 PR922 0_0402_5% 1 2 PR923 0_0402_5% PR924 0_0402_5% 1 2 PR925 0_0402_5%

PR920 3.83K_0402_1% 1 2

@

5

LGATE1G

LGATE1G

PR917 27.4K_0402_1% 2 1

2

1

VSUMG+ 1

PHASE1G

MDU1516URH_POWERDFN56-8-5

5 3 2 1

+5VS

+5VS PU901

C

4

MDU1511RH_POWERDFN56-8-5

1 1 2

PQ901 UGATE1G

PC911 10U_0805_25V6K 2 1

CPU_B+

2 1 PR906 2.74K_0402_1%

2

2 1 1.91K_0402_1%

PR912 @ 0_0402_5% 1 2

PWMG2 PR911

VSUMG+

2 1 PR910 154K_0402_1%

PC913 0.047U_0402_16V8J 1 2

PC918 0.1U_0603_25V7K 1 2

PC912 0.022U_0402_16V7K 1 2

PR909 11K_0402_1% 1 2

PR908 2.61K_0402_1% 1 2 1

0.1U_0402_16V7K PC910 2 1

@

+

D

PR907 2K_0402_1%

PC914 330P_0402_50V7K

1

PC908 470P_0402_50V7K 2 1 2 1 PR903 499_0402_1%

PC909 137K_0402_1% 150P_0402_50V8J PR905 1 2 2 1

+3VS

2

PC915 10U_0805_25V6K 2 1

PC907 68P_0402_50V8J 2 1

PR904 475_0402_1% 2 1

2

PH901 10K_0402_1%_ERTJ0EG103FA VSUMG-

+

2 2 PC906 0.01UF_0402_25V7K

1 @ PR902 10_0402_1%

D

1

PC903 15U_D2_25VM_R90

@ PC902 1000P_0402_50V7K

1 1

2

1

10_0402_1%

CPU_B+

1

@ PR901 VCC_AXG_SENSE VSS_AXG_SENSE

[10] [10]

1

2

+VGFX_CORE

PC904 33U_D2_25VM_R60

B+

PC905 15U_D2_25VM_R90

3

PC901 33U_D2_25VM_R60

4

2

5

2

C38-G series Chief River Schematic

Thursday, February 02, 2012

Sheet 1

50

of

55

Rev 0.1

1

1

1

1

PC278 10U_0603_6.3V6M

2

PC277 10U_0603_6.3V6M

2

PC276 10U_0603_6.3V6M

2

PC263 10U_0603_6.3V6M

PC248 10U_0603_6.3V6M 2 1

2

PC291 330U_D2_2V_Y

1

1

1

1

1

PC280 10U_0603_6.3V6M

2

PC281 10U_0603_6.3V6M

2

PC282 10U_0603_6.3V6M

2

PC283 10U_0603_6.3V6M

2

PC279 10U_0603_6.3V6M

2

PC353 1U_0402_6.3V6K 2 1 PC352 1U_0402_6.3V6K 2 1 PC351 1U_0402_6.3V6K 2 1 PC334 1U_0402_6.3V6K 2 1 PC333 1U_0402_6.3V6K 2 1 PC332 1U_0402_6.3V6K 2 1 PC331 1U_0402_6.3V6K 2 1 PC330 1U_0402_6.3V6K 2 1 PC329 1U_0402_6.3V6K 2 1 PC328 1U_0402_6.3V6K 2 1 PC327 1U_0402_6.3V6K 2 1 PC354 1U_0402_6.3V6K 2 1 PC356 1U_0402_6.3V6K

PC326 1U_0402_6.3V6K 2 1 PC324 1U_0402_6.3V6K 2 1 PC323 1U_0402_6.3V6K 2 1 PC322 1U_0402_6.3V6K 2 1 PC321 1U_0402_6.3V6K 2 1 PC289 1U_0402_6.3V6K 2 1 PC288 1U_0402_6.3V6K 2 1 PC287 1U_0402_6.3V6K 2 1 PC286 1U_0402_6.3V6K 2 1 PC285 1U_0402_6.3V6K 2 1 PC284 1U_0402_6.3V6K 2 1 PC355 1U_0402_6.3V6K 2 1 PC357 1U_0402_6.3V6K

1

PC255 330U_D2_2V_Y

PC256 330U_D2_2V_Y

PC241 22U_0805_6.3V6M PC259 22U_0805_6.3V6M

PC260 22U_0805_6.3V6M

PC261 22U_0805_6.3V6M

PC262 22U_0805_6.3V6M

PC358 22U_0805_6.3V6M

2

1

1

1

1

1

1

2

PC246 10U_0603_6.3V6M

2

PC245 10U_0603_6.3V6M

2

PC244 10U_0603_6.3V6M

2

PC243 10U_0603_6.3V6M

2

PC242 10U_0603_6.3V6M

2

PC247 10U_0603_6.3V6M

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 PC320 2.2U_0402_6.3V6M

2

1

1

1

1

1

1

2

PC367 1U_0402_6.3V6K

2

PC366 1U_0402_6.3V6K

2

PC365 1U_0402_6.3V6K

2

PC364 1U_0402_6.3V6K

2

PC363 1U_0402_6.3V6K

2

PC235 1U_0402_6.3V6K

PC234 1U_0402_6.3V6K 2 1

PC233 1U_0402_6.3V6K 2 1

PC232 1U_0402_6.3V6K 2 1

PC231 1U_0402_6.3V6K 2 1

PC230 1U_0402_6.3V6K 2 1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 PC319 2.2U_0402_6.3V6M

2

PC264 22U_0805_6.3V6M

Date:

1

PC258 22U_0805_6.3V6M

2

2

PC318 2.2U_0402_6.3V6M

2012/07/12

2

1

PC317 2.2U_0402_6.3V6M

Compal Secret Data

1 PC270 22U_0805_6.3V6M

3

Deciphered Date

2

+

2

2

PC254 22U_0805_6.3V6M

2011/06/24 PC272 330U_D2_2V_Y

1 PC269 22U_0805_6.3V6M

2

+

2

2

PC253 22U_0805_6.3V6M

Issued Date

1

1 PC268 22U_0805_6.3V6M

Security Classification PC271 330U_D2_2V_Y

2

2

PC252 22U_0805_6.3V6M

+ +

1 PC267 22U_0805_6.3V6M

2 1

2

2

PC251 22U_0805_6.3V6M

2

1 PC266 22U_0805_6.3V6M

1 1

2

PC316 2.2U_0402_6.3V6M

2

2

PC250 22U_0805_6.3V6M

4

2

1 1

PC275 2.2U_0402_6.3V6M

2

1 PC240 2.2U_0402_6.3V6M

2

1 1

PC229 2.2U_0402_6.3V6M

2

1 PC239 2.2U_0402_6.3V6M

2 1

1

PC228 2.2U_0402_6.3V6M

2 1

PC265 22U_0805_6.3V6M

5

+

1

PC238 2.2U_0402_6.3V6M

2 1

3

PC227 2.2U_0402_6.3V6M

+ PC237 2.2U_0402_6.3V6M

1 1

PC226 2.2U_0402_6.3V6M

1 PC249 22U_0805_6.3V6M

B

1

D

PC236 2.2U_0402_6.3V6M

C

4

PC225 2.2U_0402_6.3V6M

2

5 2 1

+CPU_CORE

+VGFX_CORE

For BOT side

@

A

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CPU_CORE_CAP Rev 0.1

Thursday, February 02, 2012 1

Sheet 51 of 55

D

+CPU_CORE

@

For TOP side C

+1.05VS_VTT +CPU_CORE

1

2

PC273 330U_D2_2V_Y

B

A

5

4

3

2

Version change list (P.I.R. List) Item

1

Page 1 of 1 for PWR

Reason for change

PG#

Modify List

Date

Phase

1 D

D

2 3 4 5 6 7 8 C

C

9 10 11 12 13

14 B

B

15 16 17 A

A

2009/01/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PIR (PWR) Rev

C38-G series Chief River Schematic0.1

Date:

5

4

3

2

Thursday, February 02, 2012

Sheet 1

52

of

55

5

4

3

2

1

COMPAL CONFIDENTIAL

3 3

3

10

V

B4 4

EC

PQ2

PCH_RSMRST#_R B7

A4

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_SUS#

B6

PLT_RST#

SYSON

7

16

CPU

V

+1.5V PU501

V

V V

PU702 +V1.05S

V

PU602 +V1.05S_VCCP

SA_PGOOD

V

9

C

8a

(DIS)

U38 +5VS

8b

B

(DIS)

U39 +3VS

8a

DGPU

Q8 +1.5VS PU701 +0.75VS

13 VR_ON

SVID

DGPU_PWR_EN

PU601 +VCC_SA

B

13

DGPU_PWROK

8

SUSP#,SUSP

VGATE

12

6

SYSON#

14

11

PM_DRAM_PWRGD

H_CPUPWRGD

15

V

ON/OFF

PCH

5

PBTN_OUT#

SYS_PWROK

V

A5

EC_ON

V

51ON#

V V

B3 C

PCH_PWROK

V

V

V

+5VALW

V

B2

B+

B7

V

B1

A5

V V

+3VALW

V

PU401

+3V_PCH +5V_PCH

B5

V

B+

10

V

PU301

A3

VV

V V

A2

V

BATT MODE

BATT

VIN

V

A1

D

PCH_PWROK

AC MODE

V

D

MODEL NAME: Power Sequence Block Diagram LA-7981P PCB NAME: REVISION: 2011/07/13 DATE:

SVID

PU901 +VCC_CORE

A

A

14 VGATE

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. Power sequence

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 0.1

Sherry and Royal

Date:

5

4

3

2

Thursday, February 02, 2012

Sheet 1

53

of

55

5

4

3

2

Version change list (P.I.R. List) Item

D

1

Page 1 for HW PIR

Reason for change

PG#

Modify List

Date

Phase

Initial

1

DVT D

2 3 4 5 6 7 8 C

C

9 10 11 12 13 14 15 16 B

B

17 18 19 20 21 22 23 A

A

Compal Secret Data

Security Classification Issued Date

2011/06/15

2012/07/11

Deciphered Date

Title

Compal Electronics, Inc. HW-PIR1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Rev 0.1

Sherry and Royal

Thursday, February 02, 2012

Sheet 1

54

of

55

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