Design And Implementation Of A Sub-wavelength All-optical Logic Gates

Republic of Iraq Ministry of Higher Education and Scientific Research Baghdad University College of Engineering Department of Electrical Engineering

Design and Implementation of a Sub-Wavelength All-Optical Logic Gates A Thesis Submitted to the College of Engineering University of Baghdad in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electrical Engineering (Electronic & Communications Engineering)

BY Saif Hasan Abdulnabi Abbas (B.Sc. 2012, M.Sc. 2015) Supervised By Assist. Prof. Dr. Mohammed Nadhim Abbas April

Shaaban

2019

1440

‫بسم اهلل الرمحن الرحيم‬ ‫ومن يتق اهلل جيعل له خمرجا ويرزقه من حيث ال حيتسب ومن يتوكل على اهلل فهو‬ ‫حسبه ان اهلل بالغ امره قد جعل اهلل لكل شيئ قدرا‬ ‫صدق اهلل العلي العظيم‬ ‫سورة الطالق‬ ‫اآلية ‪3-2‬‬

SUPERVISOR CERTIFICATE I certify that the preparation of the thesis entitled “Design and Implementation of a Sub-Wavelength All-Optical Logic Gates” by “Saif Hassan Abdulnabi” was made under my supervision at the Department of Electrical Engineering, College of Engineering, University of Baghdad in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering/Electronic and Communications Engineering.

Signature: Name: Assis. Prof. Dr. Mohammed Nadhim Abbas Date:

/ 4 /2019

DEDICATION

To the hope of world To my lord and Moulay Imam Al-Muntadher Al-Mahdi (Allah hastened his Faraj Sharif)

i

ACKNOWLEDGEMENTS In the beginning, Thanks are to The Mighty Allah for giving me the great willingness and strength to do this work. I pray to Allah to help me in the service of the Messenger of Allah Muhammad (peace be upon him and his family) and his good and pure family I would like to express my gratitude to my supervisor Assist. Prof. Dr. Mohammed Nadhim Abbas for his support and assistance during the whole phases of my research. His assistance has contributed essentially in finishing this work. Special thanks to my parents, who with thanks them have reached me to this stage and I pray to Allah Almighty to help me to serve them. Special thanks to my wife and children who have borne all sorts of difficulties until I come to this stage and pray to Allah Almighty to help me to serve them. Special thanks are to all people who provided me with any kind of help during this work.

ii

ABSTRACT Though photonics displays an attractive solution to the speed limitation of electronics, decreasing the size of bulky photonic components is one of the major problems with the implementation of photonic integrated circuits. Plasmonic circuits (Plasmonic waveguides in this work), which tightly confine electromagnetic waves at the metaldielectric or dielectric-metal interface, can be a potential solution to fill the gaps in the electronics (large bandwidth and ultra-high speed) and photonics (diffraction limit due to miniaturization size). In this thesis, Nano-ring insulator-metal-insulator (IMI) plasmonic waveguides has been used as a new configuration to propose, analyze, design, simulate, and perform all-optical logic gates and all-optical combinational logic functions. By using the Finite Element Method (FEM) in COMSOL Multiphysics, package software (5.3), the structures of the proposed plasmonic logic gates and logic functions are designed and numerically simulated using perfect matching layer as an absorbing boundary condition with two dimensions (2-D) structure. The materials of the proposed structure for plasmonic logic gates are silver and Teflon. The stripes and two Nano-rings are represented as silver material, while the remaining part of the structure is a Teflon material. The same material and structure are used in the proposed plasmonic combinational logic functions, but the Perfect Electric Conductor (PEC) material is included as a perfect mirror between two sub-structures of the proposed plasmonic logic gates. The analyzed gates are NOT, OR, AND, NOR, NAND, XOR, and XNOR and the analyzed combinational logic functions are HalfAdder, Half-Subtractor, Comparator One-Bit, and Full-Adder. The operation principle of these gates and functions is based on the constructive and destructive interferences between the input signal(s) and iii

control signal(s). Numerical simulations show that a transmission threshold (0.25) which allows achieving all proposed seven plasmonic logic gates in one structure as well as achieving all proposed four plasmonic combinational logic functions in one structure exists. This work uses the same structure with the same dimensions at 1550 nm wavelength for all proposed plasmonic logic gates and combinational logic functions. However, in some states, the transmission of the proposed plasmonic logic gates and logic functions exceeds 100%, for example, in NOT gate (112.3%), in OR gate (175%), in NAND gate (112.3%), and in XNOR gate (175%) as well as in Comparator one-bit (174%), and in Full adder (112% and 174%). Furthermore, the proposed structures of the plasmonic logic gates and functions are designed with a very small area (400nm × 400nm) and (850nm × 400nm), respectively. Finally, the proposed works (plasmonic logic gates and plasmonic combinational logic functions) are considered fundamental building blocks in photonic integrated circuits and all-optical signal processing systems to pave the way to achieve ultra-high-speed optical chip circuits and all-optical computers.

iv

LIST OF CONTENTS DEDICATION …………………………………………………………...i ACKNOWLEDGEMENTS …………………………………………......ii ABSTRACT …………………………………………………………….iii LIST OF CONTENTS …………………………………………………...v LIST OF ABBREVIATIONS ……………………………………….......x LIST OF FIGURES …………………………………………………….xii LIST OF SYMBOLS…………………………………………………...xix LIST OF TABES………………………………………………………xxv CHAPTER ONE INTRODUCTION 1.1 Background ……………………………………………………….....1 1.2 Literature Survey …………………………………………………….3 1.3 Objectives of the Thesis ……………………………………………10 1.4 Contributions of the Thesis ………………………………………...11 1.5 Thesis Outline ………………………………………………………14 CHAPTER TWO THEORETICAL CONCEPTS 2.1 Introduction ………………………………………………………...15 2.2 Brief History of Plasmonics…………………………….…………..15 2.3 Definition and Excitation of Plasmonic …………………………….16 2.4 The Importance of Plasmonic ………………………………………19 2.4.1 Limitations of Electronics ……………………………………19 2.4.2 Limitation of Photonics ………………………………………21 2.5 Advantages and Disadvantages of Plasmonics …..............................25 v

2.5.1 Advantages of Plasmonics ……………………………………25 2.5.2 disadvantages of plasmonics …………………………………25 2.6 The Principles Theory of Plasmonic………………………………..26 2.6.1 Surface Plasmon Polariton at Single Metal/Insulator Interface.27 2.6.2 Principles of SPPs Excitations…………………………………29 2.6.3 Basic Properties of Surface Plasmon Polaritons (SPPs)……….29 2.7 Plasmonic Waveguides……………………………………………...30 2.7.1 Insulator-Metal-Insulator Plasmonic Waveguide……………..31 2.7.2 Metal-Insulator-Metal Plasmonic Waveguide………………...33 2.7.3 Comparison between IMI PWs and IMI PWs………………...35 2.8 Applications of Plasmonics…………………………………………36 2.9 Perfect Electric Conductor (PEC)…………………………………...39 2.9.1Properties of PEC………………………………………………39 2.9.2 Graphene as a PEC…………………………………………….39 2.10 The Principle Operation of Logic Gates and Combinational Logic Functions………………………………………………………………..41 2.10.1Conventional Logic Gates…………………………………….41 2.10.1.1 NOT Logic Gate……………………………………..41 2.10.1.2 OR Logic Gate……………………………………….42 2.10.1.3 AND Logic Gate……………………………………..42 2.10.1.4 NOR Logic Gate……………………………………..43 2.10.1.5NAND Logic Gate……………………………………44 2.10.1.6 XOR Logic Gate……………………………………..44 2.10.1.7 XNOR Logic Gate…………………………………...45 2.10.2 Combinational Logic Functions………………………………46 2.10.2.1 Half-Adder Combinational Logic Circuit…………...46 2.10.2.2 Half-Subrtactor Combinational Logic Circuit……….46 2.10.2.3 Comparator One-Bit Combinational Logic Circuit….47 vi

2.10.2.4 Full-Ader Combinational Logic Circuit……………..48 CHAPTER THREE DESIGN OF THE PROPOSED STRUCTURES 3.1 Introduction ………………………………………………………...49 3.2 The Proposed Structure of the Proposed Plasmonic Seven Logic Gates ………………………………........................................................49 3.2.1 The Assignment of Ports for Each Proposed Plasmonic Logic Gate……………………………………………………………………...53 3.3 The Proposed Structure of the Proposed Plasmonic Four Combinational Logic Functions ………………………………………..54 3.3.1 The Assignment of Ports for Each Proposed Plasmonic Combinational Logic Function………………………………………….58 3.4 Concept of Constructive and Destructive Interferences ……………62 3.5 Validation of Structure Parameters………………………………….64 3.5.1 Validation of the Metal Used…………………………………..65 3.5.2 Validation of the Dielectric Used……………………………...66 3.5.3 Validation of the Inner Radius of the Nano-Ring……………...67 3.5.4 Validation of the Outer Radius of the Nano-Ring……………..67 3.5.5 Validation of the Length of the Side Stripes…………………..68 3.5.6 Validation of the Width of the Stripes…………………………69 3.5.7 Validation of the Coupling Distance…………………………..70 3.5.8 Validation of IMI over MIM Plasmonic Waveguides…………71

CHAPTER FOUR SIMULATION RESULTS AND DISCUSSION FOR THE PROPOSED PLASMONIC LOGIC GATES 4.1 Introduction …………………………………………………….......73 4.2 The Proposed Plasmonic Logic Gates ……………………………...74 vii

4.2.1 Plasmonic NOT Logic Gate…………………………………..74 4.2.2 Plasmonic OR Logic Gate…………………………………….77 4.2.3 Plasmonic AND Logic Gate…………………………………...80 4.2.4 Plasmonic NOR Logic Gate…………………………………...83 4.2.5 Plasmonic NAND Logic Gate…………………………………86 4.2.6 Plasmonic XOR Logic Gate…………………………………...89 4.2.7 Plasmonic XNOR Logic Gate…………………………………92 4.3 The Comparison between the Proposed Plamonic Logic gates and the Previous Works…………………………………………………………95 CHAPTER FIVE SIMULATION RESULTS AND DISCUSSION FOR THE PROPOSED PLASMONIC COMBINATIONAL LOGIC CIRCUITS 5.1 Introduction …………………………………………………….......98 5.2 The Proposed Plasmonic combinational logic functions …………...99 5.2.1 Plasmonic Half-Adder Combinational Logic Circuit…………99 5.2.2 Plasmonic Half-Subtractor Combinational Logic Circuit…...103 5.2.3Plasmonic

Comparator

One-Bit

Combinational

Logic

Circuit………………………………………………………………….107 5.2.4 Plasmonic Full-Adder Combinational Logic Circuit………...111 5.3 The Comparison between the Proposed Plamonic Combinational Logic Functions and the Previous Works……………………………...115

CHAPTER SIX CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORKS 6.1 Conclusions ……………………………………………………….117 6.2 Suggestions for Future Works……………………………………..120

viii

REFERENCES ………………………………………………………122 APPENDIX (A): Description of SPPs in Metallic Nanostructures with Electromagnetic Fields………………………………………………...A-1 A.1 The Optical Properties of Metals………………………………….A-1 A.2 Maxwell’s Equations and Electromagnetic Wave Propagation......A-5 APPENDIX (B): The Polarization of Incident Light…………………B-1 B.1 Polarization of Incident Light……………………………………..B-1 B.2 Existence of SPPs in Which Mode………………………………..B-3 APPENDIX (C): SPPs Excitations Mechanisms…………..................C-1 C.1 SPPs Excitations Mechanisms…………………………………….C-1 APPENDIX (D): Parameters Performance of Plasmonic WaveguidesD-1 D.1 Definition of Confinement, Propagation Length, Quality Factor and Figure of Merit………………………………………………………...D-1

ix

LIST OF ABBREVIATIONS 2-D

Two Dimensions

3-D

Three Dimensions

AD

Anno Domini

ALU

Arithmetic Logic Unit

CMOS

Complementary Metal Oxide Semiconductor

CPML

Convolutional Perfectly Matched Layer

DMD

Dielectric-Metal-Dielectric

DWs

Dialectic Waveguides

EM

Electromagnetic

FDTD

Finite Difference Time Domain

FEM

Finite Element Method

FoM

Figure of Merit

ICs

Integrated Circuits

ILT

Inequality Less Than

IMT

Inequality More Than

IMI

Insulator-Metal-Insulator

LSP

Localized Surface Plasmon

LRSPPs

Long-Range Surface Plasmon Polaritons

LSPRs

Localized Surface Plasmon Resonances x

MIM

Metal-Insulator-Metal

MDM

Metal-Dielectric-Metal

MZI

Mach–Zehnder Interferometer

NSOM

Near Field Scanning Optical Microscopy

NIR

Near-Infrared

PEC

Perfect Electric Conductor

PTFE

Polytetrafluoroethylene

PWs

Plasmonic Waveguide

Q-factor

Quality Factor

TIR

Total Internal Reflection

TM

Transverse Magnetic

SOI

Silicon-On-Insulator

SPs

Surface Plasmons

SPP

Surface Plasmon Polariton

SPPs

Surface Plasmon Polaritons

SRSPPs

Short-Range Surface Plasmon Polaritons

xi

LIST OF FIGURES Figure (1.1) (a) The proposed structure for realization NAND and XNOR plasmonic logic gates for [25]. (b) The proposed structure for realization of XOR plasmon logic gate for [25]……………………………………………………...4 Figure (1.2) the proposed structure for [28]……………………………………..4 Figure (1.3) the proposed structure for [28]……………………………………..5 Figure (1.4) (a) The proposed structure for NOT plasmonic logic gate for [27]. (b) The proposed structure for AND and NOR plasmonic logic gates for [27]…..6 Figure (1.5) The proposed structure for [29]…………………………………….6 Figure (1.6) The proposed structure for [30]…………………………………….7 Figure (1.7) The proposed structure for [31]…………………………………….7 Figure (1.8) The proposed structure for [32]………………………………….....8 Figure (1.9) (a) The proposed structure for half-adder plasmonic combinational logic function for [33]. (b) The proposed structure for full-adder plasmonic combinational logic function for [33]…………………………………………...9 Figure 1.10. The proposed structure for [34]…………………………………….9 Figure (2.1) Lycurgus Cup of the fourth century under different lighting conditions……………………………………………………………………...16 Figure (2.2) Incident electromagnetic wave on a dielectric-metal interface……18 Figure (2.3) Schematic describing surface plasmon resonance of metallic nanoparticle……………………………………………………………………18 xii

Figure (2.4) Propagation of Surface Plasmon Polariton (SPP) waves………….18 Figure (2.5) Plasmonics and other devices operating speeds and sizes………...24 Figure (2.6) Dispersion relation for SPPs on a single interface for a lossy metal.28 Figure (2.7) Schematic diagram of the IMI. The red lines in the two panels are the characteristic electric field profile in the two metal slab waveguides with a core thickness of z = d. The anti-symmetric mode, corresponding to the solution of L+; the symmetric mode, corresponding to the solution of L-. The wave propagates along x direction…………………………………………………...32 Figure (2. 8) The propagation length and the modal index of the IMI waveguide mode…………………………………………………………………………...33 Figure (2.9) Schematic diagram of the MIM…………………………………...34 Figure (2.10) The propagation length and the modal index of the MIM waveguide mode versus the insulator thickness d………………………………………….34 Figure (2.11) Main areas of applications of plasmonics………………………..37 Figure (2.12) Cascaded logic gates for NOR gate. (a) Schematic illustration of logic gate NOR built by cascaded OR and NOT gates. (b) Optical image of the designed Ag nanowire structure……………………………………………….38 Figure (2.13) Plasmonic AND logic gate and plasmonic half-adder combinational logic circuit performing by changing the phase of input states. (a) Optical image of the designed nanowire structure. (b) , (c), and (d) Optical image of the designed nanostructure at different cases of phases in inputs……………38 Figure (2.14) Graphene optical properties……………………………………..40

xiii

Figure (2.15) (a) The standard logic symbol, and (b) The truth table of NOT logic gate…………………………………………………………………………….41 Figure (2.16) (a) The standard logic symbol, and (b) The truth table of OR logic gate…………………………………………………………………………….42 Figure (2.17) (a) The standard logic symbol, and (b) the truth table of AND logic gate…………………………………………………………………………….43 Figure (2.18) (a) The standard logic symbol, and (b) The truth table of NOR logic gate…………………………………………………………………………….43 Figure (2.19) (a) The standard logic symbol, and (b) The truth table of NAND logic gate………………………………………………………………………44 Figure (2.20) (a) The standard logic symbol, and (b) The truth table of XOR logic gate…………………………………………………………………………….45 Figure (2.21) (a) The standard logic symbol, and (b) The truth table of XNOR logic gate………………………………………………………………………45 Figure (2.22) (a) The conventional half-adder logic diagram. (b) The truth table of half-adder logic circuit……………………………………………………...46 Figure (2.23) (a) The conventional half-subtractor logic diagram. (b) The truth table of half-subtractor logic circuit……………………………………………47 Figure (2.24) (a) The conventional comparator one-bit logic diagram. (b) The truth table of comparator one-bit logic circuit………………………………….47 Figure (2.25) (a) The conventional full-adder logic diagram. (b) The truth table of full-adder logic circuit………………………………………………………48

xiv

Figure (3.1) The proposed structure for the proposed plasmonic seven logic gates…………………………………………………………………………...50 Figure (3.3) (a) The assigned ports for the proposed plasmonic NOT logic gate. (b) The assigned ports for the proposed plasmonic OR and XOR logic gates. (c) The assigned ports for the proposed plasmonic AND logic gate. (d) The assigned ports for the proposed plasmonic NOR, NAND, and XNOR logic gates………56 Figure (3.4) The proposed structure for the proposed plasmonic four combinational logic functions…………………………………………………57 Figure (3.5) The proposed structure of the proposed plasmonic half-adder combinational logic function…………………………………………………..60 Figure (3.6) The proposed structure of the proposed plasmonic half-subtractor combinational logic function…………………………………………………..60 Figure (3.7) The proposed structure of the proposed plasmonic comparator onebit combinational logic function……………………………………………….61 Figure (3.8) The proposed structure of the proposed plasmonic full-adder combinational logic function…………………………………………………..62 Figure (3.9) Concept of constructive and destructive interferences…................63 Figure (3.10) Validation of the metal used in the proposed structure…………..65 Figure (3.11) Validation of the dielectric used in the proposed structure………66 Figure (3.12) Validation of the inner radius of the Nano-ring of the proposed structure………………………………………………………………………..67 Figure (3.13) Validation of the outer radius of the Nano-ring of the proposed structure………………………………………………………………………..68 xv

Figure (3.14) Validation of the length of the side stripes of the proposed structure………………………………………………………………………..69 Figure (3.15) Validation of the stripes width of the proposed structure………...70 Figure (3.16) Validation of the coupling distance of the proposed structure…...71 Figure (3.17) Validation of IMI over MIM PWs of the proposed structure…….72 Figure (4.1) The transmission spectrum of the proposed plasmonic NOT logic gate for different states, according to its truth table…………………………….75 Figures (4.2 (a and b)) The magnetic field distribution of logic 1and logic 0 output, respectively for the proposed plasmonic NOT logic gate………………76 Figure (4.3) The transmission spectrum of the proposed plasmonic OR logic gate for different states, according to its truth table…………………………………78 Figures (4.4 (a, b, c, and d)) The magnetic field distribution of logic 00, 01, 10 and 11 input states, respectively for the proposed plasmonic OR logic gate…...79 Figure (4.5) The transmission spectrum of the proposed plasmonic AND logic gate for different states, according to its truth table…………………………….81 Figures (4.6 (a, b, c, and d)) The magnetic field distribution of logic 00, 01, 10 and 11 input states, respectively for the proposed plasmonic AND logic gate…82 Figure (4.7) The transmission spectrum of the proposed plasmonic NOR logic gate for different states, according to its truth table…………………………….84 Figure s (4.8 (a, b, c, and d)) The magnetic field distribution of logic 00, 01, 10 and 11 input states, respectively for the proposed plasmonic NOR logic gate…85 Figure (4.9) The trans mission spectrum of the proposed plasmonic NAND logic gate for different states, according to its truth table…………………………….87 xvi

Figure s (4.10 (a, b, c, and d)) The magnetic field distribution of logic 00, 01, 10 and 11 input states, respectively for the proposed plasmonic NAND logic gate.88 Figure (4.11) The tran smission spectrum of the proposed plasmonic XOR logic gate for different states, according to its truth table…………………………….90 Figures (4.12 (a, b, c, and d)) The magnetic field distribution of logic 00, 01, 10 and 11 input states, respectively for the proposed plasmonic XOR logic gate…91 Figure (4.13) The transmission spectrum of the proposed plasmonic XNOR logic gate for different states, according to its truth table…………………………….93 Figures (4.14 (a, b, c, and d)) The magnetic field distribution of logic 00, 01, 10 and 11 input states, respectively for the proposed plasmonic XNOR logic gate..94 Figure (5.1) The trans mission spectrum of the proposed plasmonic half-adder combinational logic function for different states, according to its truth table…100 Figures (5.2 (a, b, c, and d)) The magnetic field distribution for four input states, respectively for the proposed plasmonic half-adder function………………...101 Figure (5.3) The transmission spectrum of the proposed plasmonic halfsubtractor combinational logic function for different states, according to its truth table…………………………………………………………………………..104 Figures (5.4 (a, b, c, and d)) The magnetic field distribution for four input states, respectively for the proposed plasmonic half-subtractor function……………105 Figure (5.5) The trans mission spectrum of the proposed plasmonic comparator one-bit combinational logic function for different states, according to its truth table…………………………………………………………………………..108 Figures (5.6 (a, b, c, and d)) The magnetic field distribution for four input states, respectively for the proposed plasmonic comparator one-bit function………..109 xvii

Figure (5.7) The transmission spectrum of the proposed plasmonic full-adder combinational logic function for different states, according to its truth table…112 Figures (5.8 (a, b, c, d, e, f, and g)) The magnetic field distribution for seven input states, respectively for the proposed plasmonic full-adder function………….113 Figure (A.1) Definition of a planar waveguide geometry. The waves propagate along the x-direction in a cartesian coordinate system……………………….A-8 Figure (B.1) S-Polarization…………………………………………………...B-1 Figure (B.2) P-polarization…………………………………………………...B-2 Figure (B.3) Geometry for SPP propagation at a single interface between a metal and a dielectric………………………………………………………………..B-3 Figure (B.4) Flowchart for describing the equations, which is SPP dependent on it……………………………………………………………………………...B-6 Figure (C.1) Prism coupling: (a) Kretschmann, (b) Otto configuration……...C-1 Figure (C.2) Grating coupling of a light with wave vector k impinging on a metal grating surface of period a……………………………………………………C-3 Figure (C.3) Excitation with a near-field scanning optical microscopy (NSOM) probe………………………………………………………………………….C-4 Figure (C.4) Diffraction on surface features………………………………….C-4 Figure (C.5) Excitation with highly focused optical beams………………….C-5

xviii

LIST OF SYMBOLS R

Resistance of conductor

𝜌

Electric resistivity

𝜀0

Permittivity of free space

𝜀𝑑

Permittivity of dielectric material

𝐿

Length of conductor

𝑙

Length of plate

𝑊

Width of conductor

𝑤

Width of plate

𝑇

Thickness of conductor

𝑑

Distance between plates

C

Capacitance

𝛽

Propagation Constant

𝑘𝑥

Wave number in x-direction

𝑘𝑦

Wave number in y-direction

𝑘𝑧

Wave number in z-direction

𝜀𝑐

Permittivity of core material

𝜔

Angular frequency

c

Speed of light xix

𝑛𝑐

Core refractive index

𝜆0

Wavelength in vacuum

𝑑𝑥

Fundamental mode size in x-direction

𝑑𝑦

Fundamental mode size in y-direction

𝜀𝑚

Permittivity of metal

K

Wave number

𝑘𝑑

Dielectric wave number

𝑘𝑚

Metal wave number

𝑘0

Free space wave number

d

Metal and dielectric thickness

neff

Effective refractive index

L+

Anti-symmetric mode

L-

Symmetric mode

F

Gate function

X

Output of the logic gates

A

First input of all logic gates

B

Second input of all logic gates

Ā

Complement first input

xx

∑

Output sum for half-adder and full-adder

Cout

Output carry for half-adder and full-adder

Ci

Input carry in for full-adder

D

Output Difference in half-subtractor

B

Output Borrow in half-subtractor

A=B

Output Equality in comparator one-bit

A
Inequality less than

A>B

Inequality more than

Ls

Length of the middle and side stripes

w

Width of stripes

a

Inner radius of Nano-ring

b

Outer radius of Nano-ring

d

Coupling distance between stripes and Nano-rings

λspp

Surface plasmon polariton resonance wavelength

D

Diameter of outer Nano-ring

m

Mode number

Ex

Electric field component of TM mode (x-component)

Ey

Electric field component of TM mode (y-component)

Hz

Magnetic field component of TM mode (z-component)

xxi

T

Transmission

Pout

Output optical power

Pin

Input optical power for single port

Pout|ON

Output optical power in ON state

Pout|OFF

Output optical power in OFF state

m

Interference order

λinc

Incident wavelength

θ

Phase of incident wave

Tthresh.

Transmission threshold (0.25)

QLSPR

Quality factor for localized surface plasmon resonance

QSPP

Quality factor for surface plasmon polariton

LSPP

Propagation length for surface plasmon polariton

𝑘𝑠𝑝𝑝 𝑖𝑚

Imaginary part of propagation constant (𝛽)

𝜀2 𝜀(𝜔)

Permittivity of the dielectric material Complex dielectric function

𝜎

Conductivity

𝑛(𝜔)

Complex refractive index

𝑛𝑟𝑒 (𝜔)

Real part of complex refractive index

𝑘𝑖𝑚 (𝜔)

Imaginary part of complex refractive index

𝜔𝑝

Plasma frequency

xxii

𝑬

Electric field

𝑫

Displacement

𝑯

Magnetic field

𝑩

Flux density

𝜌ext

The external charge

𝐉ext

Current density

∇

Curl

P

Polarization

M

Magnetization

μ0

Magnetic permeability of the vacuum

μr

Magnetic permeability of the vacuum

𝐻𝑥

Magnetic field component (x-component)

𝐸𝑧

Electric field component (z-component)

𝐻𝑦

Magnetic field component (y-component)

𝐴𝑑

Amplitude of electric and magnetic fields in the dielectric

𝐴𝑚

Amplitude of electric and magnetic fields in the metal

𝐾𝑑

Component of wave vector in the dielectric

𝐾𝑚

Component of wave vector in the metal

𝛽𝑥

Propagation constant in x-direction

𝑧

Distance in z-direction

Z

The evanescent decay length of the fields xxiii

𝐾𝑧

Component of wave vector in the z-direction

𝜃𝑐

Critical angle

𝑛1

The refractive index of the first dielectric

𝑛2

The refractive index of the first dielectric

𝛿

Skin depth of the medium

𝜀𝑝𝑟𝑖𝑠𝑚

Permittivity of prism paterial

n

Integer number more than 1.

G

The reciprocal vector of the grating

a

Period of grating surface in grating coupling mechanism

xxiv

LIST OF TABLES Table 2.1. Comparison between IMI plasmonic waveguides and MIM plasmonic waveguides……….............................................................................................35 Table 3.1. Assigning input signals to ports of the outputs of the proposed plasmonic full-adder combinational logic function……………………………61 Table 4.1. Operation of the transmission for the proposed plasmonic NOT logic gate…………………………………………………………………………….76 Table 4.2. Calculation of the contrast ration for the proposed plasmonic NOT logic gate………………………………………………………………………76 Table 4.3. Operation of the transmission for the proposed plasmonic OR logic gate…………………………………………………………………………….79 Table 4.4. Calculation of the contrast ration for the proposed plasmonic OR logic gate…………………………………………………………………………….80 Table 4.5. Operation of the transmission for the proposed plasmonic AND logic gate…………………………………………………………………………….82 Table 4.6. Calculation of the contrast ration for the proposed plasmonic AND logic gate………………………………………………………………………83 Table 4.7. Operation of the transmission for the proposed plasmonic NOR logic gate…………………………………………………………………………….85 Table 4.8. Calculation of the contrast ration for the proposed plasmonic NOR logic gate………………………………………………………………………86

xxv

Table 4.9. Operation of the transmission for the proposed plasmonic NAND logic gate…………………………………………………………………………….88 Table 4.10. Calculation of the contrast ration for the proposed plasmonic NAND logic gate………………………………………………………………………89 Table 4.11. Operation of the transmission for the proposed plasmonic XOR logic gate…………………………………………………………………………….91 Table 4.12. Calculation of the contrast ration for the proposed plasmonic XOR logic gate………………………………………………………………………92 Table 4.13. Operation of the transmission for the proposed plasmonic XNOR logic gate………………………………………………………………………94 Table 4.14. Calculation of the contrast ration for the proposed plasmonic XNOR logic gate……………………………………………………………………....95 Table 4.15. Comparison between the proposed plasmonic logic gates and previous works………………………………………………………………...95 Table 5.1. Operation of the transmission for the proposed plasmonic half-adder combinational logic function…………………………………………………101 Table 5.2. Calculation of the contrast ration for the proposed plasmonic halfadder combinational logic function…………………………………………..102 Table 5.3. Operation of the transmission for the proposed plasmonic halfsubtractor combinational logic function……………………………………...105 Table 5.4. Calculation of the contrast ration for the proposed plasmonic halfsubtarctor combinational logic function……………………………………...106

xxvi

Table 5.5. Operation of the transmission for the proposed plasmonic comparator one-bit combinational logic function…………………………………………109 Table 5.6. Calculation of the contrast ration for the proposed plasmonic comparator one-bit combinational logic function…………………………….110 Table 5.7. Operation of the transmission for the proposed plasmonic fuul-adder combinational logic function…………………………………………………114 Table 5.8. Calculation of the contrast ration for the proposed plasmonic fulladder combinational logic function…………………………………………..114 Table 5.9. Comparison between the proposed plasmonic combinational logic functions and previous works………………………………………………...115 Table A.1. The quality factors and SPP propagation lengths for four common plasmonic metals……………………………………………………………..A-2

xxvii

Chapter One

Introduction

CHAPTER ONE INTRODUCTION 1.1 Background In the rapid improving photoelectric technology process, using optical waveguides to transmit and receive a signal is one of the best ways to increase the internet bandwidth (capacity) and speed. The confinement process of relatively high optical intensity in a small guiding space (ranging about a few tens of nanometers) is achieved by waveguide structures. Much of the recently published scientific research has paved the way for the use of this technique (optical waveguides) in many applications, especially in optical communications systems and in photonic integrated circuit. Utilizing optical devices in these two applications has many advantages like higher communication bandwidth and higher transmission speed in optical communications systems and nanometer scale size, high capacity, ultrahigh speed information processing, security to electromagnetic interference, low power consumption, and overcoming the diffraction limit in photonic integrated circuits. Sub-wavelength devices mean plasmonic devices. The study of plasmonic is a brunch of Optoelectronics/Nanophonics Engineering. All-optical devices based on Surface Plasmon Polaritons (SPP) have been the topic of comprehensive research in recent years. All-optical SPP devices have extensively motivated new actions to overcome the major semiconductor electronic devices performance limitations which suffer from ingrained delay and high heat generation as well as to overcome the problem of photonics devices, that is, the diffraction limit. Therefore, the utilization of the aforementioned devices enabled manipulating light on a sub-wavelength scale; that is the reason why named the plasmonic is named a subwavelength [1]. SPPs are the interaction of electromagnetic waves and the free electrons of metals, propagating on the metal-dielectric or dielectric1

Chapter One

Introduction

metal interfaces [2-3]. It is a collective wave where billions of electrons oscillate in synchronization at optical frequencies. Plasmons can travel along nanoscale wires. Different passive and active plasmonic devices, such as Nano-cavities [4], Bragg reflectors [4], splitters [5], resonators [6], couplers [7], modulators [8], multi/demultiplexers [9], stub waveguides [5], hybrid plasmonic waveguides [10], switches [11-12], and logic gates [13-18], have been realized so far. On the subject of all-optical logic gates, several studies have been proposed, analyzed, and investigated, for example, single semiconductor optical amplifiers [19], hybrid plasmonic-photonic crystal nanobeam cavities [18], two-photon absorption in silicon waveguides [20], silicon micro-ring resonators[21-22], cross-phase modulation [23], and nanophotonic plasmonics [24]. Recently, many all-optical plasmonic structures provided nanoscale logic gates [25-29]. Each Nano logic gate has a different way to realize the function of the gates, a different number of logic gates, different types of logic gates, different values of resonance frequencies, different geometries, different materials of the structure, and different values of transmission. On the other hand, many all-optical plasmonic structures provided combinational logic functions [30-34]. The differences in these researches is the same differences in the proposed plasmonic logic gates in [25-29]. This thesis offers the largest number of plasmonic logic gates (seven plasmonic logic gates) in the same structure and the largest number of combinational logic functions (four plasmonic combinational logic functions) in the same structure. The materials, structure parameters, resonance frequency and transmission threshold in both structures (plasmonic logic gates structure and plasmonic combinational logic functions structure) are the same. The two structures are constructed with Nano-rings resonator and Insulator-MetalInsulator (IMI) plasmonic Nano-waveguides. The plasmonic logic gates proposed, analyzed and realized are NOT, OR, AND, NOR, NAND, XOR, and 2

Chapter One

Introduction

XNOR. On the other hand, the plasmonic combinational logic functions proposed, analyzed, and realized are Half-Adder, Half-Subtractor, Comparator One-Bit, and Full-Adder. The simulation results obtained by COMSOL Multiphysics 5.3 package software are based on Finite Element Method (FEM). In the future, these devices will be the gateway to the Nano-photonic integrated circuits applications and all-optical signal processing systems.

1.2 Literature Survey Because of the significance of all-optical logic gates and its functions based on sub-wavelength structure (i.e. plasmonic structure) that overcome the limitations of electronics and photonics devices, it has become a topic of interest for many researchers and papers recently. Since the plasmonic logic gates and plasmonic combinational logic functions regard the fundamental blocks in Nanophotonic integrated circuits and all-optical signal processing systems, many papers published different proposed plasmonic structures to realize logic gates and combinational logic functions optically. Some of these papers, which suggested performing this objective, are listed here: In October 2012, Alireza Dolatabady, et al. published a paper in plasmonic logic gate field entitled “All Optical Logic Gates Based on Two Dimensional Plasmonic Waveguides with Nanodisk Resonators”. They used MetalInsulator-Metal (MIM) plasmonic waveguides and Nano-disk resonator to realize NOT, NAND, XOR, and XNOR gates [25]. These gates are realized in two structures as shown in Figure 1.1(a) and 1.1(b). In this work, the size of the proposed structure is 1220 nm × 1120 nm and the maximum transmission reached to 42% at XOR gate. In April 2017, they proposed “All-optical logic gates in plasmonic metal–insulator–metal nanowaveguide with slot cavity resonator”. They used Metal-Insulator-Metal (MIM) plasmonic waveguides with slot cavity resonator to realize NOT, OR, and XOR gates. In this work [28], 3

Chapter One

Introduction

the transmission is improved over their previous paper [25] the structure of these gates is shown in Figure 1.2. In this work, the size of the proposed structure is 760 nm × 600 nm and the maximum transmission reached to 80% at OR gate.

(a)

(b)

Figure (1.1) (a) The proposed structure for realization NAND and XNOR plasmonic logic gates for [25] (b) The proposed structure for realization of XOR plasmon logic gate for [25]

Figure (1.2) The proposed structure for [28]

4

Chapter One

Introduction

In August 2013, Yaw-Dong Wu, et al. proposed “ Novel All-optical Logic Gates Based on Micro-ring Metal-insulator-metal Plasmonic Waveguides ”. They used micro-ring MIM plasmonic waveguides used as a structure to realize NOT logic gate as shown in Figure 1.3 [26]. In this work, the size of the proposed structure is large (2.4 𝜇m × 3 𝜇m) and the maximum transmission reached to 65.35%.

Figure (1.3) The proposed structure for [28] In September 2015, Najmeh Nozhat, et.al. proposed “All-optical logic gates based on nonlinear plasmonic ring resonators”. The proposed plasmonic logic gates in this work is based on square ring resonator MIM plasmonic waveguides structures. The proposed plasmonic logic gates are NOT, AND, and NOR gates. These gates are realized in two structures as shown in Figure 1.4 (a) and (b) [27]. The size of the two structures are 750 nm × 900 nm and 1.5 𝜇m × 1.8 𝜇m for NOT gate and for AND and NOR gate, respectively. The maximum transmission reached to 70% and 90% for both structure, respectively.

5

Chapter One

Introduction

In 2019, Zihua Liu, et al. proposed “Design of a multi-bits input optical logic device with high intensity contrast based on plasmonic waveguides structure”. Ring resonator MIM plasmonic waveguides structure is used to realize AND and NOR logic gates for 2 and 3 bit inputs as shown in Figure 1.5 [29]. The size of the proposed structure is more than 3 𝜇m × 2 𝜇m and the maximum transmission reached to 84.06% at AND gate.

(a)

(b)

Figure (1.4) (a) The proposed structure for NOT plasmonic logic gate for [27] (b) The proposed structure for AND and NOR plasmonic logic gates for [27]

Figure (1.5) The proposed structure for [29]

6

Chapter One

Introduction

In January 2015, Hamed Razavi, et al. proposed “ Design and Analysis of Plasmonic Half-Adder Based on Metal Slot Waveguide”. A nanoscale plasmonic half-adder architecture as a simple plasmonic processor has been introduced and verified based on interference of surface plasmon polariton (SPP) modes as shown in Figure 1.6 [30].

Figure (1.6) The proposed structure for [30] In December 2015, Tobias Birr, et al. proposed “Ultrafast surface plasmonpolariton logic gates and half-adder”. An optical half-adder has been achieved on footprint of only 10 μm × 28μm, integrating several cascaded SPP waveguide components and logic gates as shown in Figure 1.7 [31].

Figure (1.7) The proposed structure for [31] 7

Chapter One

Introduction

In June 2016, M. Janipour, et al. proposed “Plasmonic Adder/Subtractor Module Based on a Ring Resonator Filter”. A plasmonic adder-subtractor module based on a Metal-Insulator-Metal (MIM) ring resonator is proposed as a building block for arithmetic operations of integrated photonic circuits as shown in Figure 1.8 [32]. The size of the proposed structure is more than 1260 nm × 1260 nm.

Figure (1.8) The proposed structure for [32] In 2017, Jingya Xie, et al. proposed “Ultracompact all-optical full-adder and half-adder based on nonlinear plasmonic nanocavities”. Experimentally realized low-power ultra-compact chip-integrated all-optical logic half-adder and full-adder in X-shaped plasmonic microstructures covered with a nonlinear nanocomposite layer, and etched in plasmonic integrated circuits directly as shown in Figures 1.9(a) and 1.9(b) [33]. The logic operations were realized based on signal-light induced plasmonic Nano-cavity modes shift. The size of the proposed structure is less than 15 𝜇m × 15 𝜇m. In December 2017, Santosh Kumar, et al. proposed “All-optical bit magnitude comparator device using metal–insulator–metal plasmonic waveguide”. A compact design of a one-bit magnitude comparator using a 8

Chapter One

Introduction

nonlinear plasmonic MZI has been designed as shown in Figure 1.10. [34]. The size of the proposed structure is 17 𝜇m × 3 𝜇m.

(a)

(b)

Figure (1.9) (a) The proposed structure for half-adder plasmonic combinational logic function for [33] (b) The proposed structure for full-adder plasmonic combinational logic function for [33]

Figure (1.10) The proposed structure for [34]

9

Chapter One

Introduction

1.3 Objectives of the Thesis The main objectives of this thesis are listed in the two points below: 1. To propose, design, analyze, simulate and achieve a nanoscale integrated all-optical NOT, OR, AND, NOR, NAND, XOR, and XNOR logic gates in the same structure, in the same resonance frequency operating at 1550 nm wavelength, and in the same transmission threshold based on Nanoring Insulator-Metal-Insulator (IMI) plasmonic waveguides. 2. To propose, design, analyze, simulate and achieve a nanoscale integration all-optical combinational logic functions such as half-adder, halfsubtractor, comparator one-bit, and full-adder in the same structure, in the same resonance frequency, and in the same transmission threshold based on Nano-ring Insulator-Metal-Insulator (IMI) plasmonic waveguides. For mentioned, the structure of plasmonic combinational logic function in objective 2 consistes of two structures of objective 1 separated by 50 nm perfect mirror material. Thus, the resonance frequency and the transmission threshold in both objectives are the same. In both structures (plasmonic logic gates structure and plasmonic combinational logic functions structure), they are illuminated by a plane wave with a wavelength ranging from (800 nm - 2000 nm). However, the resonance wavelength for both objectives is the same (i.e. 1550nm). This wavelength is chosen because it is the best choice for optical communications applications [35].

10

Chapter One

Introduction

1.4 Contributions of the Thesis The most significant contributions in this thesis can be summarized as follows: 1. The proposed structure based on Plasmonic technique to overcome the diffraction limit results in a Nano-scale structure and a miniaturized photonic integrated circuit. 2. The proposed plasmonic logic gates structure is the smallest structure in size compared with previous related works. 3. The proposed plasmonic combinational logic functions structure is the smallest structure in size compared with previous related works. 4. Proposed, designed, analyzed, simulated, and achieved largest number of plasmonic logic gates (seven logic gates) in the same structure, in the same resonance wavelength, and in the same transmission threshold. 5. Proposed, designed, analyzed, simulated, and achieved largest number of plasmonic combinational logic functions (four combinational logic functions) in the same structure, in the resonance wavelength, and in the same transmission threshold. 6. According to the knowledgeof the researcher, so far, there is no theoretical or experimental demonstration of logic gates or combinational logic functions structure that satisfies the requirements of ultra-small feature size, seven plasmonic logic gates in one structure, and four plasmonic combinational logic functions in one structure. In this thesis, these requirements were achieved. 7. The transmission was enhanced (exceeding 100% in some states for some proposed plasmonic logic gates (such as NOT gate, OR gate, NAND gate, and XNOR gate) and in some proposed plasmonic combinational logic functions (such as comparator one-bit and full11

Chapter One

Introduction

adder)). According to the knowledge of the researcher, so far, no previous work has met this requirement. 8. Using the same structure to perform a number of functions gives flexibility in reusing for performing more than one gate or one function and reducing the cost (manufacturing in one time with the same dimensions and shape). 9. Using the same resonance frequency gives immunity from the crosstalk and interference phenomenon from other frequencies and, in some cases, the nanophotonic device gives inefficient in performance when using more than resonance frequency. In addition, the device becomes costly if it needs multiple resonance frequency. 10.Using the same transmission threshold avoids a mismatch between the logic gates if they are used together to build a complete photonic integrated circuit. For example, if two different transmission thresholds (e.g. 0.25 and 0.5) for two combinational logic functions are used, the decision for logic 1 and logic 0 becomes very hard . 11.IMI technique is used in the proposed structures to ensure getting the following properties: a. High propagation length. b. Low propagation loss. c. Low coupling loss. d. High quality factor. e. High figure of merit properties. These properties will be discussed in Section 2.7.3 in Chapter Two and will be explained in Appendix (D). 12. For the first time according to the knowledge of the researcher, so far, the proposed plasmonic logic gates were designed and excited at 1550 nm wavelength. That is regarded the best choice in optical 12

Chapter One

Introduction

communications, making possible compatibility between the proposed structure and optical communications systems in future. 13. This work issued two general structures; the first proposed plasomnic logic gates structure is regarded as a general structure for performing any function for logic circuits, which have one-input/one output and two-inputs/one-output at 0.25 transmission threshold in addition to perform the proposed seven plasmonic logic gates. While the second proposed plasomnic combinational logic function structure is regarded as a general structure for performing any function for logic circuits which have one-input/one-output, one-input/two-outputs, twoinputs/one-output, and two-inputs/two-outputs at 0.25 transmission threshold in addition to perform the proposed seven plasmonic logic gates and the proposed four plasmonic combinational logic functions 14. The plasmonic full-adder combinational logic function is achieved without the needing for their internal logic gates.

13

Chapter One

Introduction

1.5 Thesis Outlines This thesis is structured as follows:  Chapter Two introduces the theoretical concepts of the main topics in the thesis.  Chapter Three introduces the proposed design structures and validation parameters of the proposed plasmonic logic gates structure and the proposed plasmonic combinational logic functions structure. In addition, the concept of constructive and destructive interferences, which is the basic principle of the operation of the proposed plasmonic logic gates and the proposed plasmonic logic functions, will be presented.  Chapter Four includes the simulation results and discussion for the proposed plasmonic logic gates based on its proposed structure in Chapter Three.  Chapter Five demonstrates the simulation results and discussion for the proposed plasmonic combinational logic functions based on its proposed structure in Chapter Three.  Chapter Six presents the conclusions of the work and the suggestions for future works.

14

Chapter Two

Theoretical Concepts

CHAPTER TWO THEORETICAL CONCEPTS

2.1 Introduction This chapter presents a brief review of the substantial background of the theoretical concepts of the main topics in this thesis. In this chapter, Section 2.2 introduces a brief history of plasmonics. Section 2.3 presents the definition and the excitation of plasmonic. The importance of plasmonic is presented in Section 2.4. Section 2.5 includes the advantages and disadvantages of plasmonics. The theoretical principles of plasmonic are demonstrated in Section 2.6. Plasmonic waveguides will be introduced in Section 2.7, including the characteristic properties of SPPs sustained at a multilayer systems, including IMI or (Dielectric-Metal-Dielectric (DMD)) and MIM or (Metal-Dielectric-Metal (MDM)) SPPs waveguides, as well as a comparative study between the types of SPPs waveguides. Applications of plasmonic and SPPs waveguides applications will be presented in Section 2.8. Theory of Perfect Electric Conductor (PEC) and the metal on which it is represented is introduced in Section 2.9. Finally, the principle operation of logic gates and of combinational logic functions is demonstrated in Section 2.10.

2.2 Brief History of Plasmonics Long before the onset of Plasmonic research, the realization of Plasmonics was used by artists to create different colors in the artwork and glass artifacts, where nanoparticles of gold and silver were used in various sizes and shapes on glass to form beautiful colors, such as the famous cup of Lycurgus in the fourth century Anno Domini (AD) as shown in Figure 2.1. The cup appears green when exposed to light from the outside as shown in Fig. 2.1 (a), and appears in red 15

Chapter Two

Theoretical Concepts

when the light is illuminated from inside the cup as shown in Figure 2.1 (b), When the light falls incidentally on the other corner, it can be of other color shades as shown in Figure 2.1 (c). The oscillating electromagnetic (EM) field of the falling light oscillates the free electrons of the metals, blocking or screens light from penetrating more than a fraction of its wavelength in the metal. The frequency with which these electrons oscillate on the surface of metallic nanoparticles often results in light scatter [36]. Richie first described in 1957 Surface plasmon polaritons (SPPs) which theoretically investigated spectra of low-energy plasma loss of electrons moving through the thin metal [36].

(a)

(b)

(c)

Figure (2.1) Lycurgus Cup of the fourth century under different lighting conditions [37]

2.3 Definition and Excitation of Plasmonic The term ‘Plasmonic’ is derived from (plasma of electronic), but the term Plasmonics’ refers to (applications of plasmonic). The study of Plasmonic is a branch of Optoelectronics/Nanophonics Engineering. It studies how the electromagnetic (EM) field can be confined over a dimension of the order or smaller than the wavelength (this is a reason why it is called a sub-wavelength 16

Chapter Two

Theoretical Concepts

technique). Thus, Plasmonic is a technology in which confinement of light occurs. It is a new interesting field, which merged the powers of both electronics and photonics. The development of nanofabrication techniques helps to increase applications of plasmonic nanostructures [38]. Plasmonic is quasi-particles or a collective wave where billions of electrons oscillates in synchronization at optical frequencies resulting from strong exchange of energy between electromagnetic wave and excitation in a material e.g. photon-electron coupling. When electromagnetic waves are incident on a dielectric-metal or metal-dielectric interface (as shown in Figure 2.2), it will accelerate electrons and lead to induce polarization, which creates restoring, force which causes an oscillation of the free electron of the metal as shown in Figure 2.3. This oscillation is quantized and free electrons oscillation is quantization of plasma oscillations and it's called a plasmon [39]. In this case, electromagnetic surface waves are excited and propagate along the interface as shown in Figure 2.4 [40]. These surface waves are evanescently conned in the perpendicular direction and are known as Surface Plasmon Polariton (SPP) waves [41]. SPP waves in metallic waveguides and metal nanostructures open the possibility to confine and guide optical waves on the nanometer scale [40].

17

Chapter Two

Theoretical Concepts

Figure (2.2) Incident electromagnetic wave on a dielectric-metal interface

Figure (2.3) Schematic describing surface plasmon resonance of metallic nanoparticle [42]

Figure (2.4) Propagation of Surface Plasmon Polariton (SPP) waves

18

Chapter Two

Theoretical Concepts

2.4 The Importance of Plasmonic The importance of plasmonic is understood by knowing the limitations of electronics and photonics technologies. 2.4.1 Limitations of Electronics It is doubtless that the request for faster processing and information transfer is timeless. Because of our constant need for faster, smaller and more efficient devices, electronic devices have moved toward nanoscale devices. Recently it is standard to produce ultra-fast transistors in the nanoscale range, and an illustrious example of that is the Intel microprocessor [43-44]. The major component in Integrated Circuits (ICs) is interconnects because they dole out signals, power, and clock to the other components on the IC. As the size of the components is reduced to nanoscale, the performance of the IC becomes highly dependent on interconnects. However, unlike transistors, where functionality improves with diminishing size, interconnect efficiency reduces, thus limiting the speed of digital circuits and electronic devices [45]. Because the interconnects are made of copper material and their size decreases to the nanometer, delays increase due to an increase in the effective resistance, capacitance, cross talk, and radiation [43-45]. Over and above, the time constant affects the interconnect line, which is the product of the resistance and capacitance of the line [47]. It is apparent from the resistance and capacitance given in Equations (2.1) and (2.2), respectively that as the size of the conductor reduces its resistance increases [47]. R= C=

𝜌𝐿

(2.1)

𝑊𝑇 𝜀0 𝜀𝑑 𝑙 𝑤

(2.2)

𝑑

Where 𝜌 is the electrical resistivity, 𝜀0 and 𝜀𝑑 are the permittivity of free space and the dielectric material, respectively. 𝐿 and 𝑙 are the length of the 19

Chapter Two

Theoretical Concepts

conductor and plate, respectively. 𝑊 and 𝑤 are the width of the conductor and plate, respectively. 𝑇 and 𝑑 are the thickness of the conductor and distance between the plates, respectively. It is shown that when an interconnect is scaled down to the nanoscale, R increases due to its inverse proportionality relation with 𝑊 , and C increases due to the decrease in 𝑑. Therefore, copper interconnects are limited by their bandwidth and capacity. Thus, this will place a constraint on the number of components that can be put on a chip. Because electronics deal with charge flow (electrons), when the frequency of electronic pulse increases, the electronic device becomes hot and the wires become very loose. Thus, the principle of ‘high frequency, high data transfer rate’ cannot be applied and cannot transmit a huge amount of data. In addition, the second obstacle is when the size of electronic wires decreases, increasing resistance. This causes the delay time effect. Instead of using a chip with a processing core, multiple processing cores chips were introduced to increase the performance [48]. However, as these chips are reduced in size to nanometer and the number of cores is increased, the wires connecting these cores kinked the connection since they take a large area of the chip. Moreover, a large fraction of power gets lost in the connecting wires, leading to reduction. This happens, especially, in low power devices. From this, it is known that there are limits to how far cores are placed. On the other hand, the fundamental building blocks of Arithmetic Logic Unit (ALU) is a logic gates. These logic gates become unreliable in operation due to the lower speed in transition between logic 0 and logic 1 in electronics. Thus an alternative method must be used especially when the speed and data rate are extremely high. However, appearance of photonic integrated circuit has

20

Chapter Two

Theoretical Concepts

solved this problem dramatically, which can deal with the function of each element optically. For example, dielectric photonic interconnects due to their compatibility with Complementary Metal Oxide Semiconductor (CMOS) electronics [48-49]. The photonic interconnects offer various solutions to limitations mentioned in electronics. These interconnects give as high bandwidth and low loss interconnects between optics and electronics [49], leading to a better processing of distributed components and cores, better performance in operation, higher speed and bandwidth, and lower losses than electronic interconnects. 2.4.2 Limitation of Photonics Photonics is the science that combines optics and electronics, and involves the generation, emission, transmission, modulation, amplification, detection, and all forms of manipulating light [45]. Dielectric optical interconnects have higher speed and bandwidth at minimum power consumption compared to electronic interconnects. However, this comes at a cost of 1000 times larger optical interconnects than their electronic counterpart [45]. Large optical devices have stimulated the need of miniaturized devices in scale of sub-micrometer and nanometer in order to take benefits of their high capacity. It is proposed to use miniaturized optical devices and interfaces because of their ability to carry 1000 times the capacity of electronic circuits [43-44, 46-51]. It seems that optical networks are founded for large-scale digital signal communication. The scalability of these networks has revolutionized the next generation integratedon-chip optical communications [45]. The advances in modern day technology and the improvement of fabrication techniques simplified the realization of optical devices. A number of silicon-oninsulator devices (SOI) have been proposed for high density photonics integrated circuits. This is partly due to their high refractive index contrast and for their 21

Chapter Two

Theoretical Concepts

excellent optical properties at optic fiber communication frequencies [45]. A Mach-Zehnder electro-optic modulator is a type of SOI device. The function of this optical device is convert to the electrical signal to an optical signal. This is accomplished by encoding an optical wave with a high-speed electronic signal. It is demonstrated that optical modulation rates up to 10 Gbps are obtained with low power consumption [45]. A grating coupler using the conventional SOI has been proposed in [52]. This device promises a coupling loss below 1 dB, and an ease of integration in photonic circuits [45]. Another device, the ring resonator filter using photonic wires [53], was tested experimentally and fabricated. Moreover, in [54] a resonant coupling type polarization splitter is demonstrated. It uses photonic crystals utilizing the photonic band-gap effect and micro-cavities. It is not easy to design a waveguide using photonic crystals due to their reduced size and high index contrast. Moreover, these crystals incur high losses compared to photonic wires [55]. The signal interconnects represent the target defiance that limits the speed of the digital system. Nonetheless, the size mismatch between nanoscale electronic circuits and the optical devices has limited electronic and optical integration [46, 50]. When the dimensions of optical components become close to half the wavelength of light, optical diffraction occurs limiting the propagation of light, and limiting the scalability and dimensions of the optical devices [43, 46, 50]. This is due to the three Dimensions (3D) nature of waves propagating in a

dielectric 2

𝛽 +

𝑘𝑥2

+

𝑘𝑦2

material.

= 𝜀𝑐

It

is

derived

𝜔2

from

Equation

(2.3)

[56]. (2.3)

𝑐2

22

Chapter Two

Theoretical Concepts

Where 𝛽 is propagation constant, 𝑘𝑥 and 𝑘𝑦 are wave number in x and y directions, respectively, 𝜀𝑐 is dielectric constant of the core material, 𝜔 is angular frequency, and 𝑐 is speed of light which is 3*108 m/sec. For a 3-D wave propagating in a dielectric waveguide with dielectric constant 𝜀𝑐 > 0, propagation constant 𝛽=𝑘𝑧 , and frequency 𝜔, both transverse phase constants 𝑘𝑥 and 𝑘𝑦 are real. This produces an upper limit on 𝑘𝑥 and 𝑘𝑦 such that 𝑘𝑥 and 𝑘𝑦 ≤ (𝜔⁄𝑐)√𝜀𝑐 = 2𝜋𝑛𝑐 ⁄𝜆0 . Where 𝑛𝑐 is the core refractive index, and 𝜆0 is wavelength in vacuum. In terms of the upper limit in above, a lower limit is created on the fundamental mode size of the propagating wave which is depicted in Equation (2.4) [57]. 𝑑𝑥 , 𝑑𝑦 ≥ (𝜆0 ⁄2𝑛𝑐 )

(2.4)

Where 𝑑𝑥 and 𝑑𝑦 are the fundamental mode size of the propagating wave in 𝑥 and 𝑦 directions, respectively. This makes the dielectric photonic components once or twice orders of magnitude larger than their electronic counterparts. Moreover, photonic devices depend on frequency and have a narrow bandwidth, depending on the device configuration, limiting their usage and efficiency. These limitations comes from the diffraction limit phenomenon which resulted from using photonic devices with a size smaller than the order of operating. This phenomenon results in more power dissipated. Thus, huge amount of data cannot be sent along with miniaturization. As a result, miniaturization process to nanometer dimensions of the photonic device is inefficient and impossible to realize in practice especially when the photonic device operating in terahertz frequencies range (𝜆 is more than 1000 nm). Therefore, it is necessary to find a technology or a circuit at the nanoscale dimensions that fill the gap between the two technologies (Electronics 23

Chapter Two

Theoretical Concepts

and Photonics), and carry both optical and electrical signals, hence improving efficiency and cutting down on the chip’s power dissipation. Plasmonic or SPPs are the solution for this problem. Thus, plasmonic can act as the bridge between photonics (broad bandwidth) and electronics (nanometer miniaturization) for communication as shown in Figure 2.5. Plasmonics have the high data rate capability offered by optics. They operate at frequencies in the light and near infrared regions, thus giving them the high capacity

afforded

by

optics.

Furthermore,

plasmonics

gratifies

the

miniaturization of device size dimensions offered by electronics, which makes it compatible with the present planar manufacturing techniques such as silicon-oninsulator (SOI) and complementary metal-oxide-semiconductor (CMOS) technologies. Therefore, plasmonics has the potential of providing a wide array of sub-wavelength optical components integrated together on the same structure or chip to pave and produce the future covenant of computers “all-optical computers”. As a result, this answers the question why we need plasmonics.

Figure (2.5) Plasmonics and other devices operating speeds and sizes [58] 24

Chapter Two

Theoretical Concepts

2.5 Advantages and Disadvantages of Plasmonics [59] The advantages and disadvantages of plasmonics technology are demonstrated in the next two sub-sections. 2.5.1 Advantages of Plasmonics 1. Several orders of magnitude field enhancement (Enhanced Transmission). 2. Field confinement in several nanometers. 3. It is regarded as Nanophotonic device (Reduced Device Footprint). 4. Dependent of environment. 5. Tunable. 6. Efficient coupling. 7. Highly dispersive. 2.5.2 Disadvantages of Plasmonics 1. Short-range propagation length (maximum propagation length reaches to some millimeters). 2. Lossy. 3. Thermal effect. 4. Nanofabrication techniques limits structure dimensions (some structures impractical). 5. Difficult to simulate. 6. More cost than photonic devices.

25

Chapter Two

Theoretical Concepts

2.6 The Principles Theory of Plasmonic The term plasmonic represents to a main topic in nanophotonics, which has been devoted to the study of optical phenomena resulting from the interaction of electromagnetic fields with the conduction electrons in metals [60]. Two benefits of photon-electron interactions at insulator-metal interfaces are sub diffraction field confinement and field enhancement. This requires nanoscale structures with plasmon resonance at different ranges in the electromagnetic spectrum. Furthermore, in order to achieve high enhancement levels, plasmonic elements must have a high quality factor (Q-factor). For a recent summary of the plasmonics field, the presence of surface plasmons strongly depends on the dielectric constants (permittivity) of the metal 𝜀𝑚 and requires negative real part of the complex dielectric constant, Re (𝜀𝑚 ) < 0 as well as Im (𝜀𝑚 ) << - Re (𝜀𝑚 ). When Q-factors are high, i.e. small damping requires small imaginary parts of

𝜀𝑚 . Gold, silver and copper meet these requirements in the visible and near infrared range. Silver and gold are the most common materials in plasmon confirmed optics and spectroscopy [61]. In some cases, electromagnetic waves cannot be transmitted through a metal when their frequencies are smaller than the Plasmon frequency. The plasmons that confine at metal-dielectric interface are called Surface Plasmons (SPs). When light is coupled to these SPs under certain conditions, it improves evanescent electromagnetic fields, called surface plasmon polaritons (SPPs). This is a first type of SPs whose longitudinal waves propagate at the metaldielectric interface and exponentially decay away from the boundary into the surrounding materials. These waves travel parallel to the direction of propagation; so they cannot be excited by a transverse waves. The most effective way to excite a plasmon is to use electrons, i.e. when light excites the electrons, 26

Chapter Two

Theoretical Concepts

they will pass through a thin metal layer and lose some energy. This loss in energy is used to excite SPP [62]. The second type of SPs is a Localized Surface Plasmon (LSP). LSP is nonpropagating waves resulting when the electron oscillation is confined in three dimensions [63]. These waves induce resonances that can be observed as peaks in dispersion in the scattering and absorption cross-sections spectra. The spectral position of the resonances depends on several factors: the metal permittivity, the permittivity of the surrounding dielectric, and the size and shape of the metallic nanostructure [60]. In case of a spherical nanoparticle, the curved surface of the nanoparticle creates a restoring force on the electrons to result in a localized resonance. This kind of resonance can be excited by direct light irradiation [64]. The interaction of metallic nanostructures with electromagnetic fields, and characteristics of SPPs can be described by a classical form of Maxwell‘s equations which help to obtain the wave equation and all the optical properties of SPPs. Appendix (A) gives the highlight of these fundament. 2.6.1 Surface Plasmon Polariton at Single Metal/Insulator Interface Surface plasmon polaritons (SPPs) are evanescent electromagnetic waves propagating along the interface of metal and insulator materials due to collective electron oscillations along with an external optical field. SPPs special type of electromagnetic waves along with electron density oscillations allow nanoscale confinement of electromagnetic radiation. Surface plasmon polaritons propagated around a metal angle with a limited curve radius, using a onedimensional model similar to the scattering of a potential finite-depth well. They obtained expressions of reflection and transmission coefficients in the short wavelength limit, as well as an upper bound for the transmittance. In some cases, 27

Chapter Two

Theoretical Concepts

the propagation on non-planar surfaces may result in lower losses than flat surfaces, contrary to expectations [65]. Because of the linearity of the homogeneous Helmholtz’s equations as shown in Appendix (A), the problem of the wave incident can be divided into a two part planar surface an S-polarized wave and a polarized P-wave [66]. Appendix (B) will show the polarization effect of the incident light. Figure (2.6) displays the dispersion characteristics of SPPs using the complex dielectric permittivity of the silver metal obtained from [67].

Figure (2.6) Dispersion relation for SPPs on a single interface for a lossy metal [45]

28

Chapter Two

Theoretical Concepts

2.6.2 Principles of SPPs Excitations The SPP dispersion curve lies completely down that of free space light in the dielectric, such that 𝛽 > K. Therefore, direct excitation of SPPs by light beams is impossible unless special coupling mechanism to achieve phase matching is employed. In this way, it is possible to excite SPPs. Many methods are found to excite SPPs. These will be discussed in Appendix (C). 2.6.3 Basic Properties of Surface Plasmon Polaritons (SPPs) [37] The following points give basic properties of SPPs that are: 1. SPPs are Electromagnetic (EM) waves have infrared or visible frequency which can propagate along a metal–insulator or insulator-metal interface. 2. SPP contains the longitudinal and transverse components of the EM field. 3. SPPs contain the electric and magnetic fields components, similarly as a plane EM wave. 4. SPP spreads simultaneously in two environments, namely dielectric and metal. 5. SPP’s electric field is correlats with electric conduction (free) charges. 6. Electric field of SPP is normal and its magnetic field is parallel to the insulator-metal interface for high conductivity metals. 7. Force lines of electric field are designed to meet boundary conditions; that is, the electric field is normal for perfect metals. 8. Oscillations of surface conduction charges in dense surface give a significant enhancement of near optical field concentrated near the metal surface. 29

Chapter Two

Theoretical Concepts

9. Plasmon's behavior varies from the normal rules of photons. 10.Plasmons are active for controlling the electromagnetic waves in a nanometer scale. 11.The power transferred by the SPP is concentrated in the ultra-thin area in nanometers scale and the phenomena can exceed the diffraction limit.

2.7 Plasmonic Waveguides Fiber optics communications have revolutionized information transmission due their excellent functionality to transmit huge data over long distances with large bandwidth. However, the short-distance data transfer capability on chipintegrated electronic circuitry was limited in speed due to the time delay of nanoscale metal connections. The use of light waves as information carriers on nano-chip circuits can address the problem of reducing the rate of data transmission of electronic circuits. The conventional dielectric waveguides (DWs) that guide a light within a high refractive index area surrounded by a lowintensity beam are subject to the principle of total internal reflection through Snell’s law. However, the diffraction limit of light in optical photonic waveguides has been an impediment to miniaturized photonic waveguides; this means that light waves cannot be compressed into a domain with a dimension smaller than half their wavelength in that medium. Fortunately, nano-plasmincs was able to overcome the diffraction limit of light by using SPPs waves that previously discussed. One of the SPPs-based applications that have received great research attention over the past decade are plasmonic waveguides (PWs), which enable the conversion of light on the sub-wavelength scale into SPPs at the metal-dielectric or dielectric-metal interface overcoming the diffraction limit. PWs are favorable candidates to develop the next generation of ultra-small devices that have the advantages of both the large bandwidth operation of

30

Chapter Two

Theoretical Concepts

photonics and real nanoscale, paving the way for the future integration of highcapacity photonics and electronics devices on a scale similar to electronics. Different waveguide structures and giometries have been proposed for SPPs with a view to exploit the unique features of SPPs waveguides in nanometer scale. In spite of the interesting features of PWs, there is one main problem facing them, which is the tradeoff between loss and confinement. The two types of PWs mostly used in recent applications: insulator-metal-insulator (IMI) or dielectricmetal-dielectric (DMD) plasmonic waveguide and metal-insulator-metal (MIM) or metal-dielectric-metal (MDM) plasmonic waveguide are demonstrated in this section. Also their advantages, disadvantages, and comparison between them are introduced in this section. 2.7.1 Insulator-Metal-Insulator Plasmonic Waveguide IMI or DMD is formed by placing a thin metallic film with width less than 50 nm between two dielectric materials of the same or different refractive indices. This is similar to a combination of two dielectric / metal interfaces, where the field degrades heavily inside the metal from one interface to another. This results in the guiding of two leaky waves [56, 68]. The dispersion relation Equations 2.77 (a) and 2.77 (b) for Transverse Magnetic (TM) mode in the waveguide is given by [40, 69]. IMI structures include metal films or stripes, which are used to guide long range symmetrical SPPs (LRSPPs). The propagation distance is in tens of microns or even millimeters [45]. However, reducing the thickness or width of the stripe of the metal results in decreased localization of the mode [50], and a shortened propagation length [50], respectively. On the other hand, shortrange anti-symmetrical SPPs (SRSPPs) have higher localization but shorter propagation distances, and are better suited for integrated circuits [50]. IMI PWs including their propagation length and modal index of the IMI waveguide mode are shown in Figures (2.7) and (2.8), respectively. IMI configuration was used 31

Chapter Two

Theoretical Concepts

to realize a Mach-Zehnder interferometer, a polarization splitter, and micro-ring cavities. 𝜀𝑚 𝑘𝑑 + 𝜀𝑑 𝑘𝑚 tanh ( 𝜀𝑚 𝑘𝑑 + 𝜀𝑑 𝑘𝑚 coth (

𝑘𝑚 2 𝑘𝑚 2

d) = 0

(2.5 (a))

d) = 0

(2.6 (b))

Where d is thin metal thickness. 𝑘𝑑 = (𝛽 2 + 𝜀𝑑 𝑘0 2 )1/2

(Dielectric wave number)

(2.7)

𝑘𝑚 = (𝛽 2 + 𝜀𝑚 𝑘0 2 )1/2 (Metal wave number)

(2.8)

𝑘0 = 2𝜋⁄𝜆0

(2.9)

(Free space wave number)

𝛽: Propagation constant that is represented by an effective refractive index of the waveguide for (SPP) such as depicted in Equation (2.10). neff = 𝛽⁄𝑘0

(2.10)

Figure (2.7) Schematic diagram of the IMI. The red lines in the two panels are the characteristic electric field profile in the two metal slab waveguides with a core thickness of z = d. The anti-symmetric mode, corresponding to the solution of L+; the symmetric mode, corresponding to the solution of L-. The wave propagates along x direction [45]

32

Chapter Two

Theoretical Concepts

Figure (2. 8) The propagation length and the modal index of the IMI waveguide mode [70] 2.7.2 Metal-Insulator-Metal Plasmonic Waveguide The second configuration that allows subwavelength confinement and integration is the MIM or MDM geometry as shown in Figure (2.9). As the metal gap decreases, the propagation constant increases, implying a more confined mode. Although this structure has short propagation lengths compared to IMI, it is characterized by strong mode confinement, which can be easily integrated into photonics chips, and is not affected by radiation or cross-talk [68, 69]. The dispersion relation for MIM structures is given by Equation (2.11) [69]. Figure (2.10) shows the propagation length and the modal index of the MIM waveguide mode versus the insulator thickness d. At a few nanometers of insulator thickness d, the modal index of the MIM guided mode has a large value, and it decreases as the insulator thickness increases until it reaches the cutoff dielectric thickness, where the modal index of the MIM mode approaches the single interface SPP modal while the propagation length increased with increasing the thickness of dielectric. 33

Chapter Two

Theoretical Concepts

𝜀𝑑 𝑘𝑚 + 𝜀𝑚 𝑘𝑑 tanh (

𝑘𝑑 2

d) = 0

(2.11)

Where d is thin dielectric thickness.

Figure (2.9) Schematic diagram of the MIM [44]

Figure (2.10) The propagation length and the modal index of the MIM waveguide mode versus the insulator thickness d [70]

34

Chapter Two

Theoretical Concepts

2.7.3 Comparison between IMI PWs and IMI PWs To sum out the main points of the properties of each type of the explained PWs, a comparison between them achieves this goal. Table 2.1 shows the comparison between IMI PWs and MIM PWs. Table 2.1. Comparison between IMI plasmonic waveguides and MIM plasmonic waveguides Sr. No.

IMI Plasmonic Waveguides

MIM Plasmonic Waveguides

140, 68, 70, 71-80.

More propagation length

Less propagation length

240, 68, 70, 71-80.

Less confinement

More confinement

340, 68, 70, 71-80.

Less propagation loss

More propagation loss

472-74,78.

More quality factor

Less quality factor

572-74,76.

More figure of merit

Less figure of merit

680.

Easy fabrication

Fabrication is not easy

780.

Low coupling loss

More coupling loss

In addition to the above comparison, the MIM PW in dimensions below 50 nm becomes inefficient to be used in some applications such as logic gates [68]. The definitions of confinement, propagation length, quality facto, and figure of merit will be demonstrated in Appendix (D). This thesis uses IMI PWs for its advantages.

35

Chapter Two

Theoretical Concepts

2.8 Applications of Plasmonics Plasmonics is one of the most active areas of nanophotonic research and it has been called ‘the next chip enabling technology’ and ‘the next big thing in nanotechnology’ because of its potential to be useful for many applications [81]. Fig. 2.11 demonstrates some areas where SPP can be useful. This thesis briefly focuses on the plasmonic waveguide applications to highlight the used application (Plasmonic Logic Gates) in this thesis. SPP waveguides have a unique ability to focus and manipulate light in regions with deep wavelengths, making them particularly useful for the future design of nanophotonics ICs and devices. Specific functional plasmonic components and devices use SPP waveguides to apply their desired function(s) such as plasmonic sensor and plasmonic modulators [82]. This thesis focuses on plasmonic logic gates application for the significance of this application in future integrated circuits. For an integrated plasmonic circuits or devices which include electronic components and SPP components, the router (plasmonic logic gates and functions) is necessary as a bus for signal processing. In the electronic circuit, along with the on / off states, a third states is needed without input, so signals can be exchanged without disturbing the other components. The suitable options for the router in plasmonic circuits are the metal nanowires because they can simultaneously support different SPP wavelengths and can handle them independently [83]. Especially, by changing the light polarization, the status elements and field distributions can be dealt within nanowires, providing a way to control the routing of plasmons in nanowires such as Figure 2.12 (a)) and (2.12 (b). The SPP router can be implemented with a nanowire network by using the different phase variation of SPP interference [84-85]. As shown in Figure (2.13), SPPs are launched at the two ends of the input (in I1 and I2), and can determine 36

Chapter Two

Theoretical Concepts

the plasmon routing between the two ends of the output (in O1 and O2). Plasmon optical power can be transmitted to O1 station for certain input phases. By changing the light polarization at the ends of the input, increasing the phase difference may occur, leading to the transfer of optical power from O1 to O2. As a result, this simple nanostructure can function as a binary AND logic gate and a binary half-adder combinational logic circuit by defining a transmission threshold for the logic 0 and logic 1 states [84].

Figure (2.11) Main areas of applications of plasmonics [81]

37

Chapter Two

Theoretical Concepts

Figure (2.12) Cascaded logic gates for NOR gate [84] (a) Schematic illustration of logic gate NOR built by cascaded OR and NOT gates (b) Optical image of the designed Ag nanowire structure

(a)

(b)

(c)

(d)

Figure (2.13) Plasmonic AND logic gate and plasmonic half-adder combinational logic circuit performed by changing the phase of input states [85] (a) Optical image of the designed nanowire structure. (b) , (c), and (d) Optical image of the designed nanostructure at different cases of phases in inputs 38

Chapter Two

Theoretical Concepts

2.9 Perfect Electric Conductor (PEC) A perfect conductor or perfect electric conductor (PEC) is an ideal material showing infinite electrical conductivity or, similarly, zero resistivity [86]. Whereas there is no presence in nature for perfect electric conductors. This concept is a useful model when electrical resistance is neglected compared to other influences. For example, ideal hydromagnetic dynamics deals with fluids with perfect conductivity. Second example is the circuit diagrams; in these diagrams, there is no resistance to the wires that connect the components. Third example is the computation of electromagnetics, where parts of equations that take limited conductivity can be degraded, where PEC can be simulated faster. Recently, modern research has used the Graphene material as a PEC material, surface, or boundary condition [87-89]. 2.9.1 Properties of PEC The properties of PEC are listed in the following points: 1. It has infinite electrical conductivity or, similarly, zero resistivity. 2. It is regarded as a perfect mirror surface (i.e. reflection is 100%). 3. It is regarded unabsorbed surface (i.e. absorption is zero). 4. The real part of dielectric permittivity for PEC material is infinity. 5. The imaginary part of dielectric permittivity for PEC material is zero. 2.9.2 Graphene as a PEC Graphene is a newfangled form of carbon nanotube derived from graphite. Its 2-D structure coupled with its appropriate structural, electrical, optical and mechanical properties makes it suitable for use in many areas [89]. The electrical properties of graphene enables using it as PEC because its band structure has zero bandgap. The optical properties of graphene enables 39

Chapter Two

Theoretical Concepts

using it as an absorbance material in the visible region in the wavelength between 320 and 800 nm [89]. Nevertheless, when the wavelength exceeds 800 nm, graphene material will be a perfect reflector as shown in Figure (2.14). This thesis needs a material that perform isolation between two substructures. Graphene material can be used as a perfect mirror to do the isolation process between the two sub-structures especially, when using the 1550 nm wavelength as an operating wavelength for the proposed design to get the benefits of optical properties (absorption is zero in 1550 nm according to Figure (2.14) ) and electrical properties (it is regarded as PEC due to zero bandgap in band structure) of the graphene material.

Figure (2.14) Graphene optical properties [89]

40

Chapter Two

Theoretical Concepts

2.10 The Principle Operation of Logic Gates and Combinational Logic Functions In this section, the conventional seven logic gates (NOT, OR, AND, NOR, NAND, XOR, and XNOR) and four combinational logic functions (half-adder, half-subtractor, comparator one-bit, and full-adder) will be demonstrated. Choosing these logic gates and combinational logic functions came from operating these logic gates and combinational logic functions optically by using plasmonic waveguide in this thesis. 2.10.1 Conventional Logic Gates The principle operation for the seven conventional logic gates will be introduced in the following sub-sections. 2.10.1.1 NOT Logic Gate A NOT gate, or inverter, is used to implement the complement concept in switching algebra. The standard symbol and the truth table for a NOT gate are presented in Figure 2.15 (a) and (b), respectively. The logic value of the output of a NOT gate is simply the complement of the logic value of its input as in Equation (2.12): FNOT = X = Ā

(2.12)

(a)

(b)

Figure (2.15) (a) The standard logic symbol, and (b) The truth table of NOT logic gate 41

Chapter Two

Theoretical Concepts

2.10.1.2 OR Logic Gate The OR gate produces a logic 1 if at least one input is logic 1. Otherwise, if all inputs are logic 0, the output is logic 0. The standard symbol and the truth table for an OR gate are shown in Figure 2.16 (a) and (b), respectively. The OR operator is shown with a plus sign (+) between the variables. Thus, the OR operation is written as Equation (2.13): FOR = X = A + B

(2.13)

(a)

(b)

Figure (2.16) (a) The standard logic symbol, and (b) The truth table of OR logic gate 2.10.1.3 AND Logic Gate The AND gate produces a logic 1 when all inputs are logic 1, otherwise, the output is logic 0. The standard symbol and the truth table for an AND gate are shown in Figure 2.17 (a) and (b), respectively. The AND operator is usually shown with a dot between the variables but it may be implied (no dot). Thus, the AND operation is written as Equation (2.14): FAND = X = A ∙ B

(2.14)

42

Chapter Two

Theoretical Concepts

(a)

(b)

Figure (2.17) (a) The standard logic symbol, and (b) the truth table of AND logic gate 2.10.1.4 NOR Logic Gate The NOR gate produces a logic 1 when all inputs are logic 0, otherwise, the output is logic 0. The standard symbol and the truth table for a NOR gate are shown in Figure 2.18 (a) and (b), respectively. The NOR operator is usually shown with a plus sign (+) between their variables and a complementary symbol covering them. Thus, the operation of NOR gate is written as Equation (2.15): FNOR = X = A + B

(2.15)

(a)

(b)

Figure (2.18) (a) The standard logic symbol, and (b) The truth table of NOR logic gate

43

Chapter Two

Theoretical Concepts

2.10.1.5 NAND Logic Gate The NAND gate produces a logic 0 when all inputs are logic 1, otherwise, the output is logic 1. The standard symbol and the truth table for a NAND gate are shown in Figure 2.19 (a) and (b), respectively. The NAND operator is shown with a dot between their variables and a complementary symbol covering them. Thus, the operation of NAND gate is written as Equation (2.16): FNAND = X = A ∙ B

(2.16)

(a)

(b)

Figure (2.19) (a) The standard logic symbol, and (b) The truth table of NAND logic gate 2.10.1.6 XOR Logic Gate The XOR gate produces a logic1 output only when both inputs are at different states, otherwise, the output is logic 0. The standard symbol and the truth table for a XOR gate are shown in Figure 2.20 (a) and (b), respectively. The XOR operator is usually shown with a circled plus sign () between their variables A and B. Thus, the XOR operation is written as Equation (2.17): FXOR = X = AB + AB = A  B

(2.17)

44

Chapter Two

Theoretical Concepts

(a)

(b)

Figure (2.20) (a) The standard logic symbol, and (b) The truth table of XOR logic gate 2.10.1.7 XNOR Logic Gate The XNOR gate produces a logic1 output only when both inputs are the same states; otherwise, the output is logic 0. The standard symbol and the truth table for a XNOR gate are shown in Figure 2.21 (a) and (b), respectively. The XNOR operator is usually shown with a circled plus sign () between their variables and a complement sign covering them. Thus, the operation of XNOR gate is written as Equation (2.18): FXNOR = X = AB + AB = A  B

(2.18)

(a)

(b)

Figure (2.21) (a) The standard logic symbol, and (b) The truth table of XNOR logic gate

45

Chapter Two

Theoretical Concepts

2.10.2 Combinational Logic Functions The principle operation for the four combinational logic functions will be introduced in the following sub-sections. 2.10.2.1 Half-Adder Combinational Logic Circuit A half-adder is a combinational logic circuit with two inputs and two outputs. The two outputs are the output sum (∑) and the output carry (Cout). The first output (∑) is represented by XOR gate, while the second output (Cout) is represented by AND gate according to Figure 2.22 (a) and (b).

(a)

(b)

Figure (2.22) (a) The conventional half-adder logic diagram (b) The truth table of half-adder logic circuit 2.10.2.2 Half-Subrtactor Combinational Logic Circuit A half-subtractor is a combinational logic circuit with two inputs and two outputs. The two outputs are the Difference (D) and the Borrow (B). The first output (D) is represented by XOR gate, while the second output (B) is represented by ᾹB logic circuit according to Figures 2.23 (a) and (b).

46

Chapter Two

Theoretical Concepts

(a)

(b)

Figure (2.23) (a) The conventional half-subtractor logic diagram (b) The truth table of half-subtractor logic circuit 2.10.2.3 Comparator One-Bit Combinational Logic Circuit The basic function of a comparator is to compare the magnitudes of two binary quantities to determine the relationship of those quantities [90]. A comparator is a combinational logic circuit with two inputs, three outputs; the three outputs are the Equality (A = B), the Inequality Less Than (ILT), (A < B), and the Inequality More Than (IMT), (A > B). The first output (Equality) is represented by XNOR gate, while the second and third outputs are merged togather to be represented by XOR gate as shown in Figure 2.24 (a) and (b).

(a)

(b)

Figure (2.24) (a) The conventional comparator one-bit logic diagram (b) The truth table of comparator one-bit logic circuit 47

Chapter Two

Theoretical Concepts

2.10.2.4 Full-Ader Combinational Logic Circuit The full-adder accepts two input bits and an input carry and generates an output sum and an output carry [90]. A full-adder is a combinational logic circuit with three inputs (A, B, and Ci) and two outputs which are the output sum (∑) and the output carry (Cout) according to Figure 2.25 (a) and (b).

(a)

(b)

Figure (2.25) (a) The conventional full-adder logic diagram (b) The truth table of full-adder logic circuit

48

Chapter Three

Design of the Proposed Structures

CHAPTER THREE DESIGN OF THE PROPOSED STRUCTURES 3.1 Introduction This chapter presents the proposed design structures and validation parameters of the proposed structures for the proposed plasmonic logic gates and the proposed plasmonic combinational logic functions. In this chapter, Section 3.2 introduces the proposed structure of the proposed plasmonic seven logic gates. Section 3.3 demonstrates the proposed structure of the proposed plasmonic four combinational logic functions. Section 3.4 includes the concept of constructive and destructive interferences and their relationship with the transmission behavior of the proposed plasmonic logic gates and the proposed plasmonic combinational logic functions. Validation parameters for the proposed structures are demonstrated in Section 3.5.

3.2 The Proposed Structure of the Proposed Plasmonic Seven Logic Gates The proposed structure to simulate all-optical plasmonic logic gates (seven logic gates) is shown in Figure 3.1. The structure consists of three straight stripes and two Nano-ring resonators to construct seven logic gates based on the IMI plasmonic waveguides. The dimensions of the proposed structure are 400 nm × 400 nm, the length of the middle and side stripes (Ls) are 400 nm and 250 nm, respectively. The width (w) of these stripes is 20 nm, the radii of the Nano-ring resonator (a) and (b) are 25 nm and 50 nm, respectively, and the coupling distance (d) between the Nano-rings resonator and stripes is 7.5 nm. The materials

of

the

proposed

structure

are

silver

and

Teflon

(PolyteTraFluoroEthylene (PTFE)). In the proposed structure, stripes and two 49

Chapter Three

Design of the Proposed Structures

Nano-rings are represented as silver material, while the remaining part of the structure is a Teflon material as shown in Figure 3.1.

Figure (3.1) The proposed structure for the proposed plasmonic seven logic gates The proposed structure simulates NOT, OR, AND, NOR, NAND, XOR, and XNOR logic gates optically based on the IMI plasmonic waveguides. All seven proposed plasmonic logic gates have the same dimensions, parameters, and materials in their structures. Johnson and Christy data are used in the simulations to describe the silver permittivity while the refractive index of Teflon material is 1.375 [91]. The resonance wavelength of the Nano-ring can be determined by Equation (3.1) [27]. λspp = 4π neff D/m

(3.1)

50

Chapter Three

Design of the Proposed Structures

Where neff is the effective refractive index, D is the bigger diameter of the Nano-ring, and m is an integer number refer to the mode number (m = 1, 2, 3,….). When the mode number is equal to one, Equation (3.1) becomes Equation (3.2). λspp = 4π neff D

(3.2)

According to Eq. (1), the structure parameters and the type of materials play a role in choosing the resonance wavelength. This thesis focuses on the resonance wavelength of 1550 nm since this wavelength is the best choice in optical communications applications. The proposed structure size and shape, materials used, and the parameters of the structure help the resonance wavelength to be at this value (1550 nm). Maxwell equations are solved numerically using the two-dimensional Finite Element Method (FEM) by using COMSOL Multiphysics package software (5.3) with a convolutional perfectly matched layer (CPML) as the absorbing boundary condition of the area under simulation. The structure is excited by a TM polarized plane wave with electromagnetic field components of Ex, Ey, and Hz. The proposed structure has four ports which are the input port(s), control port(s), and an output port. These ports are decided according to the required plasmonic logic gate as shown in the next section. The SPPs are excited with launching a TM- polarized plane wave to the input port(s) and control port(s). The performance of the seven plasmonic logic gates is measured by two criteria: the first is the transmission that is a ratio between the output optical power to the single input optical power (input port or control port) as a function of wavelengths sweep. This can be done by choosing a threshold value of transmission between logic 1 (ON state) and logic 0 (OFF state) at the output in order to decide the type of states (ON or OFF). The value of transmission threshold has been chosen as 0.25 in order to achieve seven plasmonic logic gates 51

Chapter Three

Design of the Proposed Structures

in the same structure. The criterion that is chosen to decide the transmission threshold is based on [92] and using the case entitled “Requires Specificity (ReqSpec)” in [92]. The behavior of this criterion depends on user specified requirements. Note that, user requirements must be specified with care. If the model has low performance, and the requirement is too strict, this criterion is the appropriate choice for thresholding. This is according to the reference number [92]. The second criterion is the contrast or an extinction ratio between the minimum optical power of the ON state and the maximum optical power of the OFF state of the output port. Whenever the variance between the these output optical powers of these states is large, the performance of the plasmonic logic gate becomes better. These two criteria are described by Equation (3.3) [93] and Equation (3.4) [28], respectively. The proposed plasmonic logic gates depends on the transmission threshold to decide the desired logic gate . T = Pout ⁄ Pin (for ON and OFF states of the output port)

(3.3)

Where T is the transmission, Pout is the output optical power of the output port in ON state and OFF state, and Pin is the input optical power for single input port or single control port. ON ⁄ OFF contrast ratio (dB) = 10 log ((Pout|ON)min./(Pout|OFF)max.)

(3.4)

Where Pout|ON is the minimum output optical power of the output port in case of ON state (logic 1) and Pout|OFF is the maximum output optical power of the output port in case of OFF state (logic 0). The gate function for all proposed plasmonic logic gates is realized by the principle of constructive and destructive interferences between the input signal(s) and the control signal(s) and by determining the structure ports. The concept of constructive and destructive interferences will be presented in Section 3.4.

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3.2.1 The Assignment of Ports for Each Proposed Plasmonic Logic Gate Manipulation of the input port(s), control port (s), and the output port is a method of achieving the required plasmonic logic gate. In all seven proposed plasmonic logic gates, surface plasmons are excited at the wavelength of 1550 nm. This section will offer the best assigning of ports for each proposed plasmonic logic gate. The process of choosing these ports for the proposed plasmonic logic gates is done by trial and error method as an optimization method to give better transmission performance and high contrast ratio. A. The Assigned Ports for the Proposed Plasmonic NOT Logic Gate To perform NOT gate in the proposed structure, the assignment of ports is as follows: port 3 is an input port, the output port is port 4, and port 1 and port 2 are two control ports. Figure (3.3 (a)) shows the assigned ports for the proposed plasmonic NOT logic gate. The function of this gate is done by making the difference in phase between the input signal and control signals to perform the constructive and destructive interferences. The assignment of signal phase will be presented in Chapter Four. B. The Assigned Ports for the Proposed Plasmonic OR and XOR Logic Gates The assignment ports for OR and XOR logic gates are the same in the proposed structure, but the function of each one is different. This has been done by changing the phase of incident light wave. The assignment ports are as follows: input port 1 is port 1, input port 2 is port 2, output port is port 4, and the control port is port 3. Figure (3.3 (b)) shows the assigned ports for the proposed plasmonic OR and XOR logic gates.

53

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C. The Assigned Ports for the Proposed Plasmonic AND Logic Gate In AND gate structure, the assignment ports are done by choosing input port 1 as port 1, input port 2 as port 2, output port as port 3, and the control port as port 4. Figure (3.3 (c)) shows the assigned ports for the proposed plasmonic AND logic gate. D. The Assigned Ports for the Proposed Plasmonic NOR, NAND, and XNOR Logic Gates The assignment ports of these logic gates in the proposed structure are as follows: input port 1 is port 2, input port 2 is port 3, output port is port 4, and the control port is port 1. The function of each gate is performed by the principle of changing the phase of input light wave. Figure (3.3 (d)) shows the assigned ports for the proposed plasmonic NOR, NAND, and XNOR logic gates.

3.3 The Proposed Structure of the Proposed Plasmonic Four Combinational Logic Functions The proposed structure to simulate all-optical plasmonic combinational logic functions (four combinational logic functions) is shown in Figure 3.4. The structure consists of two sub-structures of dimensions 400 nm × 400 nm (each sub-structure is the proposed structure of the proposed plasmonic logic gates with all information that are mentioned previously) separated by 50 nm width of perfect mirror to do the isolation process between the two sub-structures. The perfect mirror can be realized by using graphene material [87-89]. Therefore, the dimensions of this structure become 850 nm × 400 nm. The material and all the selected dimensions in the proposed combinational logic functions are similar to those used in the proposed plasmonic logic gate structure.

54

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The proposed structure (Figure 3.4) simulates half-adder, half-subtractor, comparator one-bit, and full-adder combinational logic circuits optically based on the IMI plasmonic waveguides. In this structure, each sub-structure will perform one output of the proposed combinational logic functions isolated from the other output. The resonance wavelength of the proposed plasmonic combinational logic functions is the same as in the proposed plasmonic logic gates. It is 1550 nm.

55

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(a)

(b)

(c)

(d)

Figure (3.3) (a) The assigned ports for the proposed plasmonic NOT logic gate (b) The assigned ports for the proposed plasmonic OR and XOR logic gates (c) The assigned ports for the proposed plasmonic AND logic gate (d) The assigned ports for the proposed plasmonic NOR, NAND, and XNOR logic gates 56

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Figure (3.4) The proposed structure for the proposed plasmonic four combinational logic functions The performance of the proposed plasmonic combinational logic functions is measured by the same criteria which measure the proposed plasmonic logic gates. Thus, the transmission and contrast ratio depend on Equations (3.3) and (3.4), respectively. In addition, the value of transmission threshold has been chosen as 0.25 (same transmission threshold for proposed plasmonic logic gates) in order to achieve four plasmonic combinational logic functions in the same structure. The desired function for all proposed plasmonic combinational logic functions is achieved by the principle of constructive and destructive interferences between the input signal(s) and the control signal(s) that will be demonstrated in Section 3.4.

57

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3.3.1 The Assignment of Ports for Each Proposed Plasmonic Combinational Logic Function Determination of the input port(s), control port (s), the output port, and the type of proposed plasmonic logic gate is a method of achieving the required plasmonic combinational logic function. In all four proposed plasmonic combinational logic functions, surface plasmons are excited at the wavelength of 1550 nm. In this section, the demonstration of assigning the ports for each proposed plasmonic combinational logic function is based on the assignment process in the proposed plasmonic logic gates. A. The Assigned Ports for the Proposed Plasmonic Half-Adder Combinational Logic Circuit To perform half-adder combinational logic circuit in the proposed structure, choose the left structure as a structure to perform the output sum and choose the right structure as a structure to perform the output carry. The proposed plasmonic XOR logic gate represents the output sum. While, the output carry is represented by the proposed plasmonic AND logic gate. Figure (3.5) shows the proposed structure of the proposed plasmonic half-adder combinational logic function. B. The Assigned Ports for the Proposed Plasmonic Half-Subtractor Combinational Logic Circuit To perform half-subtractor combinational logic circuit in the proposed structure, choose the left structure as a structure to perform the Difference (first output) and choose the right structure as a structure to perform the Borrow (second output). The Difference operation is performed by the proposed plasmonic XOR logic gate, while, the Borrow operation is represented by assigning port 5 as an input port 1, port 6 as an input port 2, the output port is

58

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port 8, and the control port is port 7. Figure (3.6) shows the proposed structure of the proposed plasmonic half-subtractor combinational logic function. C. The Assigned Ports for the Proposed Plasmonic Comparator One-Bit Combinational Logic Circuit To perform comparator one-bit combinational logic circuit in the proposed structure, choose the left structure as a structure to perform the Equality (first output) and choose the right structure as a structure to perform the Inequality (merged second and third outputs as a single output). The proposed plasmonic XNOR logic gate performs the Equality operation, while, the Inequality operation is represented by the proposed plasmonic XOR logic gate. Figure (3.7) shows the proposed structure of the proposed plasmonic comparator one-bit combinational logic function. D. The Assigned Ports for the Proposed Plasmonic Full-Adder Combinational Logic Circuit To perform full-adder combinational logic circuit in the proposed structure, choose the left structure as a structure to perform an output sum (first output) and choose the right structure as a structure to perform an output carry (second output). Figure (3.8) shows the proposed structure of the proposed plasmonic full-adder combinational logic function. In this combinational logic circuit, the optimization method of assigning the input ports for each output is depicted in Table 3.1. In this table, three states changed the position in order to perform the function of the two outputs. These states are second state (001) (A B Ci), third state (010) (A B Ci), and fifth state (100) (A B Ci).

59

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Figure (3.5) The proposed structure of the proposed plasmonic half-adder combinational logic function

Figure (3.6) The proposed structure of the proposed plasmonic half-subtractor combinational logic function 60

Chapter Three

Design of the Proposed Structures

Figure (3.7) The proposed structure of the proposed plasmonic comparator onebit combinational logic function Table 3.1 Assigning input signals to ports of the outputs of the proposed plasmonic full-adder combinational logic function Assigning input signals to ports for the Sum Output (∑) Port 1 Port 2 Port 3 Ci B A Ci B A Ci B A Ci B A A B Ci Ci B A Ci B A Ci B A

Assigning input signals to ports the Output Carry (Cout) Port 5 Port 6 Port 7 Ci B A A B Ci Ci A B Ci B A Ci B A Ci B A Ci B A Ci B A

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Figure (3.8) The proposed structure of the proposed plasmonic full-adder combinational logic function

3.4 Concept of Constructive and Destructive Interferences When the peaks or troughs of two interfering waves meet, their amplitudes add together and the power increases too (it leads to transmission enhancement, and it may exceed 100%). This principle is known as constructive interference. So, what will happen when a peak of one wave meets the trough of another wave? Well, the opposite situation will happen; their amplitudes is reduced together and the power decreases too. This principle is known as destructive interference. Figure (3.9) shows the concept of constructive and destructive interferences. In the proposed works, the functions of the proposed plasmonic logic gates and the proposed plasmonic combinational logic circuits depend on the principle of the constructive and destructive interferences in addition to the assignment process of the input port(s), control port(s), and output port.

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Figure (3.9) Concept of constructive and destructive interferences On the other hand, the principle of the constructive and destructive interferences between the input light signal(s) and control light signal(s) depends on the phase of the incident light wave and the position of the input port(s) and control port(s) when the other parameters (shape, size, dimensions of the structure and materials used) remain unchanged . The constructive interference occurs when the phase of incident wave of the ports (including the control port) as well as the direction of the propagation (depends on position of the ports) are the same, while the destructive interference happens when either the phase or the direction of the propagation of incident wave of the ports is different. As a result, the phase difference leads to destructive interference between the waves [94] according to Equation (3.5) [95]: m = (4neff d cosθ) / λinc

(3.5)

Where m is interference order as an integer larger than zero, neff is an effective refractive index of the silver material, d is the thickness of the metal material, θ is the phase of the incident wave, and λinc is the incident wavelength. 63

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When θ =0°, the sign of Eq. (3.5) is positive. This means the direction of the mode is the same direction of the propagation of the wave. Thus, constructive interference occurs with the other modes which have the same phase. As a result, the transmission will be increased . When θ =45°, the sign of Eq. (3.5) is positive. This means the direction of the mode is the same direction of the propagation of the wave. Thus, constructive interference occurs with the other modes which have the same phase too, but its amount is less than When θ =0°. As a result, the transmission will be increased slightly . When θ =90°, Eq. (3.5) will be equal to zero, and neither constructive nor destructive interference will occur for this mode. The transmission is either increasing or decreasing depending on the other phases of input(s) and control light waves as well as the other parameters. When θ =180°, the sign of Eq. (3.5) is negative. This means the direction of the mode is in reverse direction of the propagation of the light wave. Thus, the destructive interference occurs with the other modes which have a different phase. As a result, the transmission will be decreased. Therefore, the phase of incident light wave and the determination of the proposed structure ports (which is an input port(s), which is a control port(s), and which is an output port) will give the function of each proposed plasmonic logic gate or each proposed plasmonic combinational logic function.

3.5 Validation of Structure Parameters Depending on the size, shape, and parameters of the proposed structure, materials and refractive index of the chosen materials, the port position, and the polarization of incident field and its phase, the transmission of the optical power is minimized or maximized. 64

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In this section, validation of the metal used, dielectric used, and structure parameters with respect to transmission behavior will be demonstrated. The validation process occurs between the mentioned parameters with respect to the transmission that is a function of wavelength. After that, choose the best metal that must be used, best dielectric that must be used, and best structure parameters which must be used based on the best transmission at 1550 nm wavelength. 3.5.1 Validation of the Metal Used By changing the metal used in the proposed structure with all parameters remaining unchanged, the transmission behavior with the desired wavelength (1550 nm) is changed (maximized or minimized) and becomes undesirable in some metals (i.e. Ti and Al). Figure (3.10) shows the validation of the metal used

Transmission

in the proposed structure.

Figure (3.10) Validation of the metal used in the proposed structure

65

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Design of the Proposed Structures

As shown in Figure (3.10), the best choice of the metal, which must be used in the proposed structure, is silver material due to its behavior of transmission at 1550 nm. 3.5.2 Validation of the Dielectric Used By changing the dielectric used in the proposed structure with all parameters remaining unchanged, the transmission behavior will be shifted to right or to left relative to the desired wavelength. Figure (3.11) shows the validation of the dielectric used in the proposed structure.

Figure (3.11) Validation of the dielectric used in the proposed structure As shown in Figure (3.11), the best choice of the dielectric, which must be used in the proposed structure, is Teflon material whose the refractive index is 1.375, which makes the resonance wavelength at 1550 nm.

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3.5.3 Validation of the Inner Radius of the Nano-Ring When changing the radius of inner Nano-ring (a) in the proposed structure with all parameters remaining unchanged, the transmission will decrease slightly when the inner radius is less than 25 nm. When the inner radius is more than 25 nm, the resonance wavelength begins slightly red shift relative to the desired wavelength by about 5 nm. Figure (3.12) shows the validation of the inner radius

Transmission

of the Nano-ring of the proposed structure.

Figure (3.12) Validation of the inner radius of the Nano-ring of the proposed structure As shown in Figure (3.12), the best choice of the inner radius value, which must be used in the proposed structure, is 25 nm, which makes the resonance wavelength at 1550 nm and gives maximum transmission at this wavelength. 3.5.4 Validation of the Outer Radius of the Nano-Ring When changing the radius of outer Nano-ring (b) in the proposed structure with all parameters remaining unchanged, the transmission will increase and the 67

Chapter Three

Design of the Proposed Structures

resonance wavelength will have light blue shift when outer radius is larger than 50 nm. When the outer radius is less than 50 nm, the transmission will decrease and the resonance wavelength will have red shift. Figure (3.13) shows the

Transmission

validation of the outer radius of the Nano-ring of the proposed structure.

Figure (3.13) Validation of the outer radius of the Nano-ring of the proposed structure As shown in Figure (3.13), the best choice of the outer radius value, which must be used in the proposed structure, is 50 nm, which makes the resonance wavelength at 1550 nm. 3.5.5 Validation of the Length of the Side Stripes When changing the length of the side stripes (Ls) in the proposed structure with all parameters remaining unchanged, the resonance wavelength will have light blue shift in regular manner when Ls is less than 250 nm. When Ls is larger than 250 nm, the resonance wavelength will have blue shift in regular manner.

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The value of the transmission in the two cases remains the same. Figure (3.14)

Transmission

shows the validation of the side stripes length of the proposed structure.

Figure (3.14) Validation of the length of the side stripes of the proposed structure As shown in Figure (3.14), the best choice of the side stripes length value, which must be used in the proposed structure, is 250 nm, which makes the resonance wavelength at 1550 nm. 3.5.6 Validation of the Width of the Stripes When changing the stripes width (w) in the proposed structure with all parameters remaining unchanged, the transmission will be increased and the resonance wavelength will have blue shift and when w is less than 20 nm. When w is larger than 20 nm, the transmission will be decreased and the resonance wavelength will have red shift. Figure (3.15) shows the validation of the stripes width of the proposed structure.

69

Design of the Proposed Structures

Transmission

Chapter Three

Figure (3.15) Validation of the stripes width of the proposed structure As shown in Figure (3.15), the best choice of stripes width value which must be used in the proposed structure is 20 nm, which makes the resonance wavelength at the desired wavelength (1550 nm). 3.5.7 Validation of the Coupling Distance The interaction between stripes and Nano-rings causes new Localized surface Plasmon Resonances (LSPRs) which are a result of the coupling between the Nano-rings resonator and stripes [96]. Furthermore, since plasmon waves couple strongly only in the near-field regime at very short distances, the coupling distance (d) must be decreased to enable this mechanism to sustain and obtain the highest improvement of the field. In the proposed structure, when changing the coupling distance (d) with all parameters remaining unchanged, the transmission will be increased or decreased. If the coupling distance increases, the transmission decreases and vice

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versa and becomes irregular when d is less than 5 nm or more than 10 nm. Figure

Transmission

(3.16) shows the validation of coupling distance of the proposed structure.

Figure (3.16) Validation of the coupling distance of the proposed structure As shown in Figure (3.16), the best choice of coupling distance value is 5 nm due to the transmission spectra. Nevertheless, when coupling distance becomes less than 7.5 nm, it becomes an unrealistic value to apply practically for the problems of cross talk and manufacturing limitations. Therefore, according to the obtained results, the optimum coupling distance between the Nano-rings resonator and stripes for the proposed structure has been chosen to be 7.5 nm. 3.5.8 Validation of IMI over MIM Plasmonic Waveguides In the proposed structure, when changing the Martials of the parts for the proposed structure from IMI to MIM, all parameters remaining unchanged. The transmission will disappear and it becomes undesirable in MIM case for the reasons mentioned in Chapter Two. Figure (3.17) shows the validation of IMI over MIM PWs of the proposed structure. 71

Design of the Proposed Structures

Transmission

Chapter Three

Figure (3.17) Validation of IMI over MIM PWs of the proposed structure

72

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

CHAPTER FOUR SIMULATION RESULTS AND DISCUSSION OF THE PROPOSED PLASMONIC LOGIC GATES 4.1 Introduction This chapter shows the simulated results to evaluate the performance of the proposed plasmonic logic gates. The proposed structures have been simulated by using COMSOL Multiphysics package software (Version 5.3) in order to perform the functions of the proposed plasmonic logic gates optically based on Nano-ring IMI plasmonic waveguide. The transmission of optical power and contrast ratio depend on the two criteria which determine the performance of the desired logic gate. The two criteria will be explained and discussed in this chapter. In all seven proposed plasmonic logic gates, the structure is illuminated by a plane wave with a wavelength ranging from (800 nm - 2000 nm). This band is used because it is the most useful band in the optical communication. The illumination of light is launched to the input port(s) (ON state) and to the control port(s). All ports (input port(s), control port(s), and outport(s)) for each proposed plasmonic logic gate were mentioned in Chapter Three. In this chapter, Section 4.2 introduces the simulation results and their discussions of the proposed plasmonic logic gates in addition to explaining the operation of each proposed plasmonic logic gate and calculating the constant ratio of each one. Section 4.3 presents a comparison between the proposed plamonic logic gates and previous works.

73

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4.2 The Proposed Plasmonic Logic Gates In this section, the simulation results of the proposed plasmonic seven logic gates (NOT, OR, AND, NOR, NAND, XOR, and XNOR) will be presented Furthermore, calculation of the contrast ratio of each gate will be presented. The function of each proposed plasmonic gate is achieved by two factors: 1. The right choice for assigning the ports in the structure (such as the input port(s), control port(s), and output port). 2. The right choice of the phase angle which makes the constructive and destructive interferences between input signal(s) and control signal(s). 4.2.1 Plasmonic NOT Logic Gate The proposed structure which performs plasmonic NOT logic gate was shown in Figure 3.3 (a). The function of this gate can be achieved by the constructive and destructive interferences between the input signal and the control signals. When the state of the input port is OFF and launching light is at the wavelength of 1550 nm to the control ports (always ON state) with a phase equal to 0°, the state of the output port is ON according to the value of transmission which is 1.123 (above transmission threshold = 0.25). In this state, the constructive interference occurs between the control signals because the phase for their signals in and the direction of propagation are the same and as a result, the transmission exceeds 100%. When launching light at the wavelength of 1550 nm to the input port with a phase equal to 90° (the state of the input port is ON) the phase of the control port 1 is changed form 0° to 180°. In this case, the destructive phenomenon will occur and the state of the output port is OFF according to the value of transmission that is 0.045 (below transmission threshold = 0.25). The transmission spectrum of the proposed plasmonic NOT logic gate is shown in Figure 4.1. Figure 4.2 (a) and (b) show the magnetic field distribution 74

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

of logic 1 and logic 0 output, respectively. The operation of the proposed

Transmission

plasmonic NOT logic gate is summarized in Table 4.1 and Table 4.2.

Figure (4.1) The transmission spectrum of the proposed plasmonic NOT logic gate for different states, according to its truth table

75

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(a)

(b)

Figure (4.2 (a and b)) The magnetic field distribution of logic 1and logic 0 output, respectively for the proposed plasmonic NOT logic gate Table 4.1. Operation of the transmission for the proposed plasmonic NOT logic gate Input State Logic 0 Logic 1

Input Port (Phase) OFF(0°) ON(90°)

Control Port 1 (Phase) ON(0°) ON(180°)

Control Port 2 (Phase) ON(0°) ON(0°)

T

Tthresh.

Output State

Output Port

1.123 0.045

0.25 0.25

Logic 1 Logic 0

ON OFF

Table 4.2. Calculation of the contrast ration for the proposed plasmonic NOT logic gate Input Optical Power for Single Port (Pin (W)) 1 1

Output Optical Power (Pout (W))

Output State

Minimum Pout |ON (W)

Maximum Pout |OFF (W)

Contrast Ratio

1.123 0.045

ON OFF

Pout |ON = 1.123

Pout |OFF = 0.045

14 dB

The calculation of contrast ration in Table (4.2) is based on Equations (3.3) and (3.4) in Chapter Three as follows: Pin is known value (1 W for each input port or control port is proposed in the simulation). The transmission value for OFF and ON states is achieved in Table 4.1. Therefore, Pout in Table (4.2) is calculated by applying Equation (3.3). When Pout is calculated for OFF output state (extract the maximum value of output optical power if more than one value 76

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of Pout exist), the name of the maximum Pout becomes Pout|OFF. The name of the minimum value of Pout becomes Pout|ON when the minimum value of Pout is calculated for ON output state. When the both values (Pout|ON and Pout|OFF) of the maximum and minimum values of Pout become known, it will be easy to apply Equation (3.4) and get the contrast ratio. The calculation of contrast ratio for all proposed plasmonic logic gates is the same way as that mentioned earlier. In the proposed plasmonic NOT logic gate, the contrast ratio is high because the output optical power in ON state is larger than the output optical power in OFF state and the variance between the values of these optical powers is large. This comes from that the transmission in the ON state is higher than the threshold value (exceed 100%) and the transmission in the OFF state is lower than the threshold value significantly (4.5%), which makes the contrast ratio high and efficient proposed gate. 4.2.2 Plasmonic OR Logic Gate The proposed structure which performs plasmonic OR logic gate was shown in Figure 3.3 (b). In the same manner of proposed plasmonic NOT logic gate, the function of the proposed OR logic can be realized. Nevertheless, in this gate, it does not need to change the phase shift between the input signal(s) and control signal in order to get the maximum transmission in three cases. In this gate, the transmission exceeds 100% (1.75) when the two input ports are in ON state and the control port is also in ON state. The enhancement of the transmission result from the constructive phenomenon between the input signals (1 and 2) and the control signal because the three signals have the same phase (0°) and the same direction of propagation. The transmission spectrum of the proposed plasmonic OR logic gate is shown in Figure 4.3. Figure 4.4 (a, b, c, and d) shows the magnetic field distribution for the four input states, respectively. 77

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The operation of the proposed plasmonic OR logic gate is summarized in Table

Transmission

4.3 and Table 4.4.

Figure (4.3) The transmission spectrum of the proposed plasmonic OR logic gate for different states, according to its truth table

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(a)

(b)

(c)

(d)

Figure (4.4 (a, b, c, and d)) The magnetic field distribution of logic 00, 01, 10 and 11 input states, respectively for the proposed plasmonic OR logic gate Table 4.3. Operation of the transmission for the proposed plasmonic OR logic gate Input State 1

Input State 2

Logic 0 Logic 0 Logic 1 Logic 1

Logic 0 Logic 1 Logic 0 Logic 1

Input Port 1 (Phase) OFF(0°) OFF(0°) ON(0°) ON(0°)

Input Control Port 2 Port (Phase) (Phase) OFF(0°) ON(0°) ON(0°) ON(0°) OFF(0°) ON(0°) ON(0°) ON(0°)

79

T

Tthresh.

0.07 0.63 0.63 1.75

0.25 0.25 0.25 0.25

Output Output State Port Logic 0 Logic 1 Logic 1 Logic 1

OFF ON ON ON

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

Table 4.4. Calculation of the contrast ration for the proposed plasmonic OR logic gate Input Optical Power for Single Port (Pin (W)) 1 1 1 1

Output Optical Power (Pout (W))

Output State

Minimum Pout |ON (W)

Maximum Pout |OFF (W)

Contrast Ratio

0.07 0.63 0.63 1.75

OFF ON ON ON

Pout |ON = 0.63

Pout |OFF = 0.07

9.5 dB

Table 4.4 shows that the contrast ratio is high because the minimum output optical power in ON states is large in comparison with the output optical power in OFF state (variance between Pout |ON and Pout |OFF is large). Therefore, the performance of the proposed plasmonic OR gate is good and efficient. 4.2.3 Plasmonic AND Logic Gate The proposed structure which performs plasmonic AND logic gate was shown in Figure 3.3 (c). The function of this gate can be realized by the constructive and destructive interference between the input signal(s) and the control signal. When input ports are in OFF-ON and ON-OFF states (control port has been ON state always), the destructive interference occurs between the input signal and control signal due to the phase difference (phase of the input signal = 180° and phase of control signal = 0°) which leads to reducing the transmission ffddddddddddby 6%. On the other hand, when both input ports are in ON state, the constructive interference occurs between the input signals. As a result, the state of the output port is ON according to the value of the transmission that is 0.72 (above transmission threshold = 0.25). In this case, the transmission does not exceed 100% (72 %) although the phase of input signals and the control signal is the same (phase = 0°) because the control port, namely, port 4 has an opposed propagation direction in comparison with input ports which cause a destructive interference with the two input signals. The transmission spectrum of 80

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Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

the proposed plasmonic AND logic gate is shown in Figure 4.5. Figure 4.6 (a, b, c, and d) shows the magnetic field distribution for four input states , respectively. The operation of the proposed plasmonic AND logic gate is summarized in Table

Transmission

4.5 and Table 4.6.

Figure (4.5) The transmission spectrum of the proposed plasmonic AND logic gate for different states, according to its truth table

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(a)

(b)

(c)

(d)

Figure (4.6 (a, b, c, and d)) The magnetic field distribution of logic 00, 01, 10 and 11 input states, respectively for the proposed plasmonic AND logic gate Table 4.5. Operation of the transmission for the proposed plasmonic AND logic gate Input State 1

Input State 2

Logic 0 Logic 0 Logic 1 Logic 1

Logic 0 Logic 1 Logic 0 Logic 1

Input Port 1 (Phase) OFF(0°) OFF(0°) ON(180°) ON(0°)

Input Port 2 (Phase) OFF(0°) ON(180°) OFF(0°) ON(0°)

Control Port (Phase) ON(0°) ON(0°) ON(0°) ON(0°)

82

T

Tthresh.

0.07 0.06 0.06 0.72

0.25 0.25 0.25 0.25

Output Output State Port Logic 0 Logic 0 Logic 0 Logic 1

OFF OFF OFF ON

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

Table 4.6. Calculation of the contrast ration for the proposed plasmonic AND logic gate Input Optical Power for Single Port (Pin (W)) 1 1 1 1

Output Optical Power (Pout (W))

Output State

Minimum Pout |ON (W)

Maximum Pout |OFF (W)

Contrast Ratio

0.07 0.06 0.06 0.72

OFF OFF OFF ON

Pout |ON = 0.72

Pout |OFF = 0.07

10.13 dB

In Table 4.6, the contrast ratio is high because the variance between Pout |ON and Pout |OFF is large. As a result, the performance of the proposed plasmonic AND gate is efficient. 4.2.4 Plasmonic NOR Logic Gate The proposed structure which performs plasmonic NOR logic gate was shown in Figure 3.3 (d). The function of this gate can be achieved by destructive interference between the input signal(s) and the control signal. When the state of the input ports is OFF and a light at a wavelength of 1550 nm is launched to the control port with phase always equal to 180°, the state of the output port is ON according to the value of transmission which is 0.2807 (above transmission threshold = 0.25). When lunching a light at the wavelength of 1550 nm to the input port 2 and to the control port (the state of the input ports is OFF-ON), but the phase of input light to input port 2 is 45°. The state of the output port in this case is OFF according to the value of transmission which is 0.07 (below transmission threshold = 0.25). When lunching a light at the wavelength of 1550 nm to input port 1 and to the control port (the state of the input ports is ON OFF), the phase of input light to the input port 1 is 45°. The state of the output port in this case is OFF according to the value of transmission also is 0.002 (below transmission threshold = 0.25). Finally, when lunching a light at the wavelength of 1550 nm to the input ports (1 and 2) and to the control port (the state of the 83

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

input ports is ON-ON), the phase of input light to the input ports (1 and 2 ) is 45° and 0°, respectively. The state of the output port in this case is OFF according to the value of transmission which is 0.05 (below transmission threshold = 0.25). In these three states, the destructive interference occurred due to the phase difference between the input signal(s) and the control signal. The transmission spectrum of the proposed plasmonic NOR logic gate is shown in Figure 4.7. Figure 4.8 (a, b, c, and d) shows the magnetic field distribution for four input states , respectively. The operation of the proposed plasmonic NOR logic gate is

Transmission

summarized in Table 4.7 and Table 4.8.

Figure (4.7) The transmission spectrum of the proposed plasmonic NOR logic gate for different t states, according to its truth table

84

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

(a)

(b)

(c)

(d)

Figure (4.8 (a, b, c, and d)) The magnetic field distribution of logic 00, 01, 10 and 11 input states, respectively for the proposed plasmonic NOR logic gate Table 4.7. Operation of the transmission for the proposed plasmonic NOR logic gate Input State 1

Input State 2

Logic 0 Logic 0 Logic 1 Logic 1

Logic 0 Logic 1 Logic 0 Logic 1

Input Input Port 1 Port 2 (Phase) (Phase) OFF(0°) OFF(0°) OFF(0°) ON(45°) ON(45°) OFF(0°) ON(45°) ON(0°)

Control Port (Phase) ON(180°) ON(180°) ON(180°) ON(180°)

85

T

Tthresh.

Output State

Output Port

0.2807 0.07 0.002 0.05

0.25 0.25 0.25 0.25

Logic 1 Logic 0 Logic 0 Logic 0

ON OFF OFF OFF

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

Table 4.8. Calculation of the contrast ration for the proposed plasmonic NOR logic gate Input Optical Power for Single Port (Pin (W)) 1 1 1 1

Output Optical Power (Pout (W))

Output State

Minimum Pout |ON (W)

Maximum Pout |OFF (W)

Contrast Ratio

0.2807 0.07 0.002 0.05

ON OFF OFF OFF

Pout |ON = 0.2807

Pout |OFF = 0.07

6 dB

In Table 4.8, the contrast ratio is moderate because the output optical power in ON state is slightly larger than the threshold value. As a result, the performance of the proposed NOR logic gate is moderate. 4.2.5 Plasmonic NAND Logic Gate The proposed structure which performs plasmonic NAND logic gate was shown in Figure 3.3 (d) also. The function of this gate can be achieved by the enhancement and suppression interference between the input signal(s) and the control signal. When the state of the input ports is OFF and launching light at the wavelength of 1550 nm to the control port with phase always equal to 0°, the state of the output port is ON according to the value of transmission whcih is 0.2807 (above transmission threshold = 0.25). In this state neither constructive nor destructive interference occurs because only one port is in ON state (control port). As a result, the transmission is slightly above the threshold. In the second state (OFF-ON state), the transmission is 0.63 (above transmission threshold = 0.25) whcih is regarded as a logic 1. In the second state, the transmission does not exceed 100% although the phase of these ports is equal. This is because the length of stripes of control port and input port 2 is unequal. In the third state (ONOFF state), the enhancement to the transmission occurs (Transmission = 1.123); that is also regarded as a logic 1. In this case, the constructive interference occurs between the input signal and a control signal, which leads to transmission, 86

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

exceeding 100%. In the fourth case (ON-ON), the transmission is 0.045 which is regarded as a logic 0. In this case, destructive interference occurred between input signals and control signal due to the difference in phase. The phase assignment for each input or control signal is shown in Table 4.9. The transmission spectrum of the proposed plasmonic NAND logic gate is shown in Figure 4.9. Figure 4.10 (a, b, c, and d) shows the magnetic field distribution for four input states , respectively. The operation of the proposed plasmonic NAND

Transmission

logic gate is summarized in Table 4.9 and Table 4.10.

Figure (4.9) The trans mission spectrum of the proposed plasmonic NAND logic gate for different states, according to its truth table

87

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

(a)

(b)

(c)

(d)

Figure (4.10 (a, b, c, and d)) The magnetic field distribution of logic 00, 01, 10 and 11 input states, respectively for the proposed plasmonic NAND logic gate Table 4.9. Operation of the transmission for the proposed plasmonic NAND logic gate Input State 1

Input State 2

Logic 0 Logic 0 Logic 1 Logic 1

Logic 0 Logic 1 Logic 0 Logic 1

Input Port 1 (Phase) OFF(0°) OFF(0°) ON(0°) ON(180°)

Input Port 2 (Phase) OFF(0°) ON(0°) OFF(0°) ON(90°)

Control Port (Phase) ON(0°) ON(0°) ON(0°) ON(0°)

88

T

Tthresh.

Output State

Output Port

0.2807 0.63 1.123 0.045

0.25 0.25 0.25 0.25

Logic 1 Logic 1 Logic 1 Logic 0

ON ON ON OFF

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

Table 4.10. Calculation of the contrast ration for the proposed plasmonic NAND logic gate Input Optical Power for Single Port (Pin (W)) 1 1 1 1

Output Optical Power (Pout (W))

Output State

Minimum Pout |ON (W)

Maximum Pout |OFF (W)

Contrast Ratio

0.2807 0.63 1.123 0.045

ON ON ON OFF

Pout |ON = 0.2807

Pout |OFF = 0.045

8 dB

In the proposed plasmonic NAND logic gate, the contrast ratio is moderate because the minimum output optical power in ON state is slightly larger than the threshold value. As a result, the performance of the proposed NAND logic gate is moderate. 4.2.6 Plasmonic XOR Logic Gate The proposed structure which performs plasmonic XOR logic gate was shown in Figure 3.3 (b). At this plasmonic logic gate (OFF-ON and ON-OFF states), the constructive interference between the input signal and the control signal is not large. However, the transmission = 0.63 which is regarded logic 1. In the fourth state (ON-ON), destructive interference occurred between input signals and the control signal due to the difference in the signal phase. Thus, the transmission diminished to 0.05 which is regarded as logic 0. The phase assignment for each input or control signal is shown in Table 4.11. The transmission spectrum of the proposed plasmonic OR logic gate is shown in Figure 4.11. Figure 4.12 (a, b, c, and d) shows the magnetic field distribution for four input states, respectively. The operation of the proposed plasmonic XOR logic gate is summarized in Table 4.11 and Table 4.12.

89

Chapter Four

Simulation Results and Discussion of the

Transmission

Proposed Plasmonic Logic Gates

Figure (4.11) The tran smission spectrum of the proposed plasmonic XOR logic gate for different states, according to its truth table

90

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

(a)

(b)

(c)

(d)

Figure (4.12 (a, b, c, and d)) The magnetic field distribution of logic 00, 01, 10 and 11 input states, respectively for the proposed plasmonic XOR logic gate Table 4.11. Operation of the transmission for the proposed plasmonic XOR logic gate Input State 1

Input State 2

Logic 0 Logic 0 Logic 1 Logic 1

Logic 0 Logic 1 Logic 0 Logic 1

Input Port 1 (Phase) OFF(0°) OFF(0°) ON(0°) ON(45°)

Input Control Port 2 Port (Phase) (Phase) OFF(0°) ON(0°) ON(0°) ON(0°) OFF(0°) ON(0°) ON(180°) ON(0°)

91

T

Tthresh.

0.07 0.63 0.63 0.05

0.25 0.25 0.25 0.25

Output Output State Port Logic 0 Logic 1 Logic 1 Logic 0

OFF ON ON OFF

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

Table 4.12. Calculation of the contrast ration for the proposed plasmonic XOR logic gate Input Optical Power for Single Port (Pin (W)) 1 1 1 1

Output Optical Power (Pout (W))

Output State

Minimum Pout |ON (W)

Maximum Pout |OFF (W)

Contrast Ratio

0.07 0.63 0.63 0.05

OFF ON ON OFF

Pout |ON = 0.63

Pout |OFF = 0.07

9.5 dB

Table 4.12 shows that the contrast ratio is high because the output optical power in ON states is large in comparison with the maximum output optical power in OFF state (variance between Pout |ON and Pout |OFF is large. Therefore, the performance of the proposed plasmonic XOR logic gate is efficient. 4.2.7 Plasmonic XNOR Logic Gate The proposed structure which performs plasmonic XNOR logic gate was shown in Figure 3.3 (d). The function of this gate can be achieved by the constructive and destructive interference between the input signal(s) and the control signal. The first state (OFF-OFF) can be achieved in the same way obtained in the first state of the proposed plasmonic NOR logic gate. In the second and the third states (OFF-ON and ON-OFF), the destructive interference happened between the input signal and control signal due to the difference in phase. Thus, the transmission is less than the threshold regarding it as logic 0. In the fourth state (ON-ON), the large constructive interference happened between input signals and control signal due to the phase of these signals is similar (phase = 0°) and the direction of propagation is the same also. This resulted in enhancing the transmission above 100% (175%) and that is regarded as logic 1. The assignment of the phase of the input signal or control signal is shown in Table (4.13). The transmission spectrum of the proposed plasmonic XNOR logic gate is shown in Figure 4.13. Figure 4.14 (a, b, c, and d) shows the magnetic field 92

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

distribution for four input states, respectively. The operation of the proposed

Transmission

plasmonic XNOR logic gate is summarized in Table 4.13 and Table 4.14.

Figure (4.13) The transmission spectrum of the proposed plasmonic XNOR logic gate for different states, according to its truth table

93

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

(a)

(b)

(c)

(d)

Figure (4.14 (a, b, c, and d)) The magnetic field distribution of logic 00, 01, 10 and 11 input states, respectively for the proposed plasmonic XNOR logic gate Table 4.13. Operation of the transmission for the proposed plasmonic XNOR logic gate Input State 1

Input State 2

Logic 0 Logic 0 Logic 1 Logic 1

Logic 0 Logic 1 Logic 0 Logic 1

Input Port 1 (Phase) OFF(0°) OFF(0°) ON(45°) ON(180°)

Input Port 2 (Phase) OFF(0°) ON(45°) OFF(0°) ON(180°)

Control Port (Phase) ON(180°) ON(180°) ON(180°) ON(180°)

94

T

Tthresh.

Output State

Output Port

0.2807 0.07 0.002 1.75

0.25 0.25 0.25 0.25

Logic 1 Logic 0 Logic 0 Logic 1

ON OFF OFF ON

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

Table 4.14. Calculation of the contrast ration for the proposed plasmonic XNOR logic gate Input Optical Power for Single Port (Pin (W)) 1 1 1 1

Output Optical Power (Pout (W))

Output State

Minimum Pout |ON (W)

Maximum Pout |OFF (W)

Contrast Ratio

0.2807 0.07 0.002 1.75

ON OFF OFF ON

Pout |ON = 0.2807

Pout |OFF = 0.07

6 dB

In the proposed plasmonic XNOR logic gate, notable the contrast ratio is moderate because the minimum output optical power in ON state is slightly larger than the threshold value. As a result, the performance of the proposed XNOR logic gate is moderate.

4.3 The Comparison between the Proposed Plamonic Logic gates and Previous Works The proposed plasmonic logic gates are compared to previous works as depicted in Table 4.15. Table 4.15. Comparison between the proposed plasmonic logic gates and previous works Criteria/Research

This Thesis

Software Program Used

FEM-2D

Proposed Structure

Nano-ring InsulatorMetalInsulator (IMI) Plasmonic NanoWaveguides

Ref. [25] Finite Difference Time Domain (FDTD)-2D

MIMPlasmonic Waveguides with NanoDisk Resonator

95

Ref. [26] Finite Difference Time Domain (FDTD)-2D

Ref. [27] Finite Difference Time Domain (FDTD)-2D

Micro-ring MetalInsulatorMetal (MIM) Plasmonic Waveguides

Square Micro-ring MetalInsulatorMetal (MIM) Nonlinear Plasmonic Waveguides

Ref. [28] Finite Difference Time Domain (FDTD)-2D Plasmonic MetalInsulatorMetal (MIM) NanoWaveguides with Slot Cavity Resonator

Ref. [29] Finite Difference Time Domain (FDTD)-2D Ring Resonator MetalInsulatorMetal (MIM) Plasmonic Waveguides

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

Number of Proposed Logic Gates

7 Gates

4 Gates

1 Gate

3 Gates

3 Gates

2 Gates

Proposed Logic Gates

NOT, OR, AND, NOR, NAND, XOR, and XNOR

NOT, NAND, XOR, and XNOR

NOT

NOT, AND, and NOR

NOT, OR, and XOR

AND and NOR

Realization of Proposed plasmonic Logic Gates

All proposed Plasmonic logic gates are realized in one structure

The proposed plasmonic logic gates are realized in two structures

The proposed plasmonic logic gate is realized in one structure

The proposed plasmonic logic gates are realized in one structure

The proposed plasmonic logic gates are realized in one structure

Size

400 nm × 400 nm

1220 nm × 1120 nm

2.4 𝜇m × 3 𝜇m

The proposed plasmonic logic gates are realized in two structures 750 nm × 900 nm and 1.5 𝜇m × 1.8 𝜇m

760 nm × 600 nm

More than 3 𝜇m × 2 𝜇m

Operating Wavelength(s)

1550 nm

525 nm

850 nm

1535 nm

1535 nm

944 nm and 999 nm

Dielectric Material Used

Teflon

Air

Air

SiO2

Air

Air

Nobel Metal Used

Silver

Silver

Silver

Silver

Silver

Silver

Model of Description the Relative Permittivity of the Silver

Johnson and Christy Data

Drude Model

Drude Model

Drude Model

Drude Model

Drude Model

Performance Measured Transmission Threshold between ON/OFF States

Transmission Transmission Transmission Transmission and Contrast and Contrast Transmission Transmission and Contrast and Contrast Ratio Ratio Ratio Ratio 0.25 or 25%

0.2 or 20% or Less

0.5 or 50% or Less

0.30 or 30%

0.3 or 30%

70% at NOT Gate

38% at NOT Gate

70% at NOR Gate

80% at OR Gate

90% at AND Gate

40% at XOR Gate

0.5 or 50% or Less

112.3% at NOT Gate

Maximum Transmission %

175% at OR Gate

25% at NAND Gate

72% at AND Gate

42% at XOR Gate

28.07% at NOR Gate

25% at XNOR Gate

112.3% at NAND Gate

96

65.35% at NOT Gate

84.06% at AND Gate 80.07 at NOR Gate

Chapter Four

Simulation Results and Discussion of the Proposed Plasmonic Logic Gates

63% at XOR Gate 175% at XNOR Gate

Enhancement of Transmission

Exists in NOT Gate, OR Gate, NAND Gate, and XNOR Gate

Does Not Exist

Does Not Exist

Does Not Exist

Does Not Exist

From the above table, it can be concluded that the proposed structure in this thesis has better performance than the other structures in previous works according to its size, number of plasmonic logic gates that can be performed, type of logic gates, operating wavelength, and enhanced transmission in some states for some logic gates. For practical issue, the proposed structure and their applied proposed plasmonic logic gates on it can be manufactured and implemented practically by using any modern technology or device that realize these functions with error ratio doesn’t exceed 10%.

97

Does Not Exist

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

CHAPTER FIVE SIMULATION RESULTS AND DISCUSSION OF THE PROPOSED PLASMONIC COMBINATIONAL LOGIC CIRCUITS 5.1 Introduction This chapter shows the simulated results to evaluate the performance of the proposed plasmonic combinational logic functions. The proposed structures have been simulated by using COMSOL Multiphysics package software (Version 5.3) in order to perform the functions of the proposed plasmonic combinational logic circuits optically based on Nano-ring IMI plasmonic waveguide. The transmission of optical power and contrast ratio depend on the two criteria which determine the performance of the desired logic function. The two criteria will be explained and discussed in this chapter. In all four proposed plasmonic combinational logic functions (half-adder, half-subtractor, comparator one-bit, and full-adder), the structure is illuminated by a plane wave with a wavelength ranging from (800 nm - 2000 nm). The illumination of light is launched to the input port(s) (ON state) and to the control port(s). All ports (input port(s), control port(s), and outport(s)) for each proposed plasmonic combinational logic function are mentioned in Chapter Three. In this chapter, Section 5.2 introduces the simulation results and their discussions of the proposed plasmonic combinational logic functions in addition to explaining the operation of each proposed function and calculating the constant ratio of each one. Section 5.3 presents a comparison between the proposed plamonic combinational logic function and previous works. 98

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

5.2 The Proposed Plasmonic Combinational Logic Functions In this section, the simulation results of the proposed plasmonic four combinational logic functions (half-adder, half-subtractor, comparator one-bit, and full adder) will be presented. In addition, calculation of the contrast ration of each one will be demonstrated. However, the calculation of contrast ration is based on Equations (3.3) and (3.4) in Chapter Three. The function of each proposed plasmonic function is achieved by two factors mentioned in Chapter Four. 5.2.1 Plasmonic Half-Adder Combinational Logic Circuit The proposed structure which performs plasmonic half-adder was shown in Figure 3.5. The function of this combination logic circuit can be achieved by depending on the operation of the function of two gates. The first gate is the proposed plasmonic XOR logic gate to obtain the output sum and the second gate is the proposed plasmonic AND logic gate to obtain the carry output in the proposed plasmonic circuit. Each gate is isolated by perfect mirror material, such as Graphene. The simulation results of the combination of the proposed plasmonic XOR and AND gates give the results of the proposed plasmonic halfadder. The transmission spectrum of the proposed plasmonic half-adder combinational logic function is shown in Figure 5.1. Figure 5.2 (a, b, c, and d) shows the magnetic field distribution of logic 00, 01, 10, 11, respectively for this plasmonic logic funtion. The operation of the proposed plasmonic half-adder combinational logic function is summarized in Table 5.1 and Table 5.2.

99

Chapter Five

Simulation Results and Discussion of the

Transmission

Proposed Plasmonic Combinational Logic Circuits

Figure (5.1) The trans mission spectrum of the proposed plasmonic half-adder combinational logic function for different states, according to its truth table In Figure (5.1), the first blue curve and the green curve are aligned with each other and appear as a green curve. In addition, the red curve and the purple curve are aligned with each other also and appear as a purple curve. For information, all curves which are aligned with each other have the same value of transmission in transmission spectrum behavior.

100

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

(a)

(b)

(c)

(d)

Figure (5.2 (a, b, c, and d)) The magnetic field distribution for four input states, respectively for the proposed plasmonic half-adder function Table 5.1. Operation of the transmission for the proposed plasmonic half-adder combinational logic function Input State 1

Input State 2

Logic 0 Logic 0 Logic 1 Logic 1

Logic 0 Logic 1 Logic 0 Logic 1

Input 1 Port 1 (Phase) OFF(0°) OFF(0°) ON(0°) ON(45°)

Input 2 Port 2 (Phase) OFF(0°) ON(0°) OFF(0°) ON(180°)

Input 1 Port 5 (Phase) OFF(0°) OFF(0°) ON(0°) ON(0°)

101

Input 2 Port 6 (Phase) OFF(0°) ON(0°) OFF(0°) ON(0°)

Control Port 3 (Phase) ON(0°) ON(0°) ON(0°) ON(0°)

Control Port 8 (Phase) ON(0°) ON(0°) ON(0°) ON(0°)

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

Table 5.1. Continued T(Port 4)

T(Port 7)

Tthresh.

0.07 0.62 0.63 0.05

0.07 0.06 0.06 0.72

0.25 0.25 0.25 0.25

Sum Output Logic 0 Logic 1 Logic 1 Logic 0

Output Carry Logic 0 Logic 0 Logic 0 Logic 1

Output Port 4 OFF ON ON OFF

Output Port 7 OFF OFF OFF ON

Table 5.2. Calculation of the contrast ration for the proposed plasmonic halfadder combinational logic function Input Optical Power for any Single Port (Pin (W))

Output Optical Power (Pout (W)) for (∑)

Output Optical Power (Pout (W)) for (Cout)

1 1 1 1

0.07 0.62 0.63 0.05

0.07 0.06 0.06 0.72

Output Output Port 4 Port 7

OFF ON ON OFF

OFF OFF OFF ON

Minimum Pout |ON and Maximum Pout |OFF (W) for (∑) Pout |ON = 0.62 Pout |OFF = 0.07

Minimum Pout |ON and Maximum Pout |OFF (W) for (Cout) Pout |ON = 0.72 Pout |OFF = 0.07

Contrast Ratio for (∑)

Contrast Ratio for (Cout)

9.5 dB

10.13 dB

In the proposed plasmonic half-adder combinational logic function, the contrast ratio is known by two outputs. The contrast ratio of the output sum is high because the minimum output optical power in ON state is larger than the maximum output optical power in OFF state and the variance between the values of these optical powers is large. In addition, the contrast ratio of the output carry is also high and better for the same reason. As a result, the performance of the proposed plasmonic half-adder combinational logic function is good because it has high contrast ration between ON and OFF states for both outputs.

102

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Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

5.2.2 Plasmonic Half-Subtractor Combinational Logic Circuit The proposed structure which performs plasmonic half-subtractor was shown in Figure 3.6. The function of this combination logic circuit can be achieved by depending on the operation of the proposed plasmonic XOR logic gate to obtain the first output (Difference) in the proposed plasmonic halfsubtractor and ᾹB logic function to obtain the Borrow output in the proposed plasmonic circuit. Therefore, the Difference is achieved by the same way was obtained in the proposed plasmonic XOR gate, which has explained in Chapter Four. The Borrow process is the same for XOR gate but in third state (ON-OFF); therefore, the output must be OFF instead of ON state. This state is done by launching light at the wavelength of 1550 nm to the input port 1 (port 5) with a phase equal to 180° and to the control port with a phase always equal to 0°. The state of the output ports is OFF according to the value of transmission which is 0.18 (below transmission threshold = 0.25). The simulation results of the combination of the proposed plasmonic XOR logic gate and ᾹB logic function give the simulation results of the proposed plasmonic half-subtractor. The transmission spectrum of the proposed plasmonic half-subtarctor combinational logic function is shown in Figure 5.3. Figure 5.4 (a, b, c, and d) shows the magnetic field distribution of logic 00, 01, 10, 11, respectively for this plasmonic logic function. The operation of the proposed plasmonic half-subtractor combinational logic function is summarized in Table 5.3 and Table 5.4.

103

Chapter Five

Simulation Results and Discussion of the

Transmission

Proposed Plasmonic Combinational Logic Circuits

Figure (5.3) The transmission spectrum of the proposed plasmonic halfsubtractor combinational logic function for different states, according to its truth table In Figure (5.3), the first blue curve and the green curve are aligned with each other and appear as a green curve. In addition, the red curve, light blue curve and the purple curve are also aligned with each other and appear as a purple curve. In addition, the black curve and the second blue curve are aligned with each other and appear as a blue curve.

104

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

(a)

(b)

(c)

(d)

Figure (5.4 (a, b, c, and d)) The magnetic field distribution for four input states, respectively for the proposed plasmonic half-subtractor function Table 5.3. Operation of the transmission for the proposed plasmonic halfsubtractor combinational logic function Input State 1

Input State 2

Logic 0 Logic 0 Logic 1 Logic 1

Logic 0 Logic 1 Logic 0 Logic 1

Input 1 Port 1 (Phase) OFF(0°) OFF(0°) ON(0°) ON(45°)

Input 2 Port 2 (Phase) OFF(0°) ON(0°) OFF(0°) ON(180°)

Input 1 Port 5 (Phase) OFF(0°) OFF(0°) ON(180°) ON(180°)

105

Input 2 Port 6 (Phase) OFF(0°) ON(0°) OFF(0°) ON(45°)

Control Port 3 (Phase) ON(0°) ON(0°) ON(0°) ON(0°)

Control Port 7 (Phase) ON(0°) ON(0°) ON(0°) ON(0°)

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

Table 5.3. Continued T(Port 4)

T(Port 8)

Tthresh.

0.07 0.62 0.63 0.05

0.07 0.63 0.18 0.05

0.25 0.25 0.25 0.25

Sum Output Logic 0 Logic 1 Logic 1 Logic 0

Output Carry Logic 0 Logic 1 Logic 0 Logic 0

Output Port 4 OFF ON ON OFF

Output Port 8 OFF ON OFF OFF

Table 5.4. Calculation of the contrast ration for the proposed plasmonic halfsubtarctor combinational logic function Input Output Output Optical Optical Optical Power Power Power Output Output for any (Pout (Pout (W)) Port 4 Port 8 Single (W)) for Port for (D) (Borrow) (Pin (W)) 1 1 1 1

0.07 0.62 0.63 0.05

0.07 0.63 0.18 0.05

OFF ON ON OFF

OFF ON OFF OFF

Minimum Pout |ON and Maximum Pout |OFF (W) for (D) Pout |ON = 0.62 Pout |OFF = 0.07

Minimum Pout |ON and Maximum Pout |OFF (W) for (Borrow) Pout |ON = 0.63 Pout |OFF = 0.18

Contrast Ratio for (D)

Contrast Ratio for (Borrow)

9.5 dB

5.44 dB

In the proposed plasmonic half-subtarctor combinational logic function, the contrast ratio is also known by two outputs. The contrast ratio of the Difference is high because the variance between the values of Pout|ON and Pout|OFF is large. On the other hand, the contrast ratio of the Borrow output is moderate due to the variance between Pout|ON and Pout|OFF which is not large enough. As a result, the performance of the proposed plasmonic half-subtractor combinational logic function is good because it has a high contrast ration between ON and OFF states for Difference output and a moderate contrast ratio in the Borrow output.

106

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

5.2.3 Plasmonic Comparator One-Bit Combinational Logic Circuit The proposed structure that perform plasmonic comparator one-bit was shown in Figure 3.7. The function of this combinational logic circuit can occur by the constructive and destructive interference between the input signal(s) and the control signal in each sub-structure. The operation of the Inequality in this combinational logic circuit is the same of Sum operation and Difference operation in half-adder and half-subtractor combinational logic circuit, respectively. The output of proposed plasmonic Inequality is regarded as the functions of the Inequality Less Than (ILT), (A < B), in the second state and the Inequality More Than (IMT), (A > B), in the third state. To perform the Equality process, the proposed plasmonic XNOR logic gate must be used. The simulation results of the combination of the proposed plasmonic XNOR and XOR gates give the results of the proposed plasmonic comparator one-bit combinational logic function. The transmission spectrum of the proposed plasmonic comparator onebit combinational logic function is shown in Figure 5.5. Figure 5.6 (a, b, c, and d) shown the magnetic field distribution of logic 00, 01, 10, 11, respectively for the proposed plasmonic comparator one-bit combinational logic function. The operation of the proposed plasmonic comparator one-bit combinational logic function is summarized in Table 5.5 and Table 5.6.

107

Chapter Five

Simulation Results and Discussion of the

Transmission

Proposed Plasmonic Combinational Logic Circuits

Figure (5.5) The trans mission spectrum of the proposed plasmonic comparator one-bit combinational logic function for different states, according to its truth table In Figure (5.5), the first green curve and the red curve are aligned with each other and appear as a red curve. In addition, the light blue curve and the yellow curve are aligned with each other and appear as yellow curve.

108

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

(a)

(b)

(c)

(d)

Figure (5.6 (a, b, c, and d)) The magnetic field distribution for four input states, respectively for the proposed plasmonic comparator one-bit function Table 5.5. Operation of the transmission for the proposed plasmonic comparator one-bit combinational logic function Input State 1

Input State 2

Logic 0 Logic 0 Logic 1 Logic 1

Logic 0 Logic 1 Logic 0 Logic 1

Input 1 Port 2 (Phase) OFF(0°) OFF(0°) ON(45°) ON(180°)

Input 2 Port 3 (Phase) OFF(0°) ON(45°) OFF(0°) ON(180°)

Input 1 Port 5 (Phase) OFF(0°) OFF(0°) ON(0°) ON(45°)

109

Input 2 Port 6 (Phase) OFF(0°) ON(0°) OFF(0°) ON(180°)

Control Port 1 (Phase) ON(180°) ON(180°) ON(180°) ON(180°)

Control Port 7 (Phase) ON(0°) ON(0°) ON(0°) ON(0°)

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

Table 5.5. Continued T(Port 4)

T(Port 8)

Tthresh.

0.2825 0.07 0.002 1.74

0.07 0.63 0.62 0.05

0.25 0.25 0.25 0.25

A=B Output Logic 1 Logic 0 Logic 0 Logic 1

A < B and A > B Output Logic 0 Logic 1 Logic 1 Logic 0

Output Port 4 ON OFF OFF ON

Output Port 8 OFF ON ON OFF

Table 5.6. Calculation of the contrast ration for the proposed plasmonic comparator one-bit combinational logic function Input Optical Power for any Single Port (Pin (W)) 1 1 1 1

Output Output Optical Optical Power Power Output Output (Pout (W)) (Pout (W)) Port 4 Port 8 for for (A = B) (Inequality) 0.2825 0.07 0.002 1.74

0.07 0.63 0.62 0.05

ON OFF OFF ON

OFF ON ON OFF

Minimum Pout |ON and Maximum Pout |OFF (W) for (A = B) Pout |ON = 0.2825 Pout |OFF = 0.07

Minimum Pout |ON and Maximum Pout |OFF (W) for (Inequality) Pout |ON = 0.62 Pout |OFF = 0.07

Contrast Ratio for (A = B)

Contrast Ratio for (Inequ -ality)

6 dB

9.5 dB

Table 5.6 shows the contrast ratio in Equality output is moderate due to the slightly difference between Pout |ON and Pout |OFF. On the other hand, the contrast ratio of the Inequality output is high. As a result, the performance of the proposed plasmonic comparator one-bit combinational logic function is efficient because it especially has a high contrast ration between ON and OFF states in Inequality output.

110

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

5.2.4 Plasmonic Full-Adder Combinational Logic Circuit The proposed structure which performs plasmonic full-adder was shown in Figure 3.8. The function of this combinational logic circuit can be achieved by the constructive and destructive interferences between the input signals in each sub-structure. The assigning of input signal(s) to the input ports for the two outputs of this proposed plasmonic logic function was shown in Table (3.1) in Chapter Three. When one of the input ports is in ON state, such as (OFF-OFFON, OFF-ON-OFF, or ON-OFF-OFF), only the output sum is in ON state according to the value of transmission which is 0.2807 (above transmission threshold = 0.25) for the three states. While, the output carry is OFF in these states according to the value of transmission which is 0.07 (below transmission threshold = 0.25) for the three states. In the fourth state, (OFF-ON-ON), only output carry is in ON state according to the value of transmission which is 1.12 (above transmission threshold = 0.25). While, the output sum is OFF according to the value of transmission that is 0.002 (below transmission threshold = 0.25). In the sixth and seventh states, (ON-OFF-ON or ON-ON-OFF), also the output carry is in ON state according to the value of transmission which is 0.63 (above transmission threshold = 0.25). While, the output sum is OFF according to the value of transmission which is 0.07 (below transmission threshold = 0.25). In the eighth state, (ON-ON-ON), both outputs are in ON state according to the value of transmission which is 1.75 (above transmission threshold = 0.25). The constructive and destructive interferences occur when the phase of input signals is the same or is different, respectively. The phase value for each input signal to the input port is shown in Table 5.7. As a result, a full-adder combinational logic circuit is achieved by manipulation the input ports and without the need to construct their internal logic gates. The transmission spectrum of the proposed plasmonic full-adder combinational logic function is shown in Figure 5.7. Figure 111

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

5.8 (a, b, c, d, e, f, and g) shows the magnetic field distribution of logic 001,010, 011, 100, 101, 110, and 111 input states (except first state (000) because it does not have a field due to no input signal in their input ports), respectively for the proposed plasmonic full-adder combinational logic function. The operation of the proposed plasmonic full-adder combinational logic function is summarized

Transmissio n

in Table 5.7 and Table 5.8.

Figure (5.7) The transmission spectrum of the proposed plasmonic full-adder combinational logic function for different states, according to its truth table In Figure (5.7), the first blue curve, and the first black curve are aligned with each other and appear as a black curve. In addition, the first, the second green curves, the second blue curve, the first, and the second light blue curves are aligned with each other and appears as a light blue curve. The second red curve and the second purple curve are aligned with each other and appears as purple curve. As well as the second yellow curve and the second black curve are aligned with each other and appears as a black curve. It is worth mentioning that all the curves that are aligned with each other have the same value of transmission in transmission spectrum behavior. 112

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

(a)

(b)

(c)

(d)

(e)

(f)

(g) Figure (5.8 (a, b, c, d, e, f, and g)) The magnetic field distribution for seven input states, respectively for the proposed plasmonic full-adder function 113

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

Table 5.7. Operation of the transmission for the proposed plasmonic full-adder combinational logic function Input State 1

Input State 2

Input State 3

Input 1 (Phase)

Logic 0 Logic 0 Logic 0 Logic 0 Logic 1 Logic 1 Logic 1 Logic 1

Logic 0 Logic 0 Logic 1 Logic 1 Logic 0 Logic 0 Logic 1 Logic 1

Logic 0 Logic 1 Logic 0 Logic 1 Logic 0 Logic 1 Logic 0 Logic 1

OFF(0°) OFF(0°) OFF(0°) OFF(0°) ON(0°) ON(180°) ON(180°) ON(0°)

Input 2 Port 2 (Phase) OFF(0°) OFF(0°) ON(0°) ON(180°) OFF(0°) OFF(0°) ON(45°) ON(0°)

Input 3 (Phase)

Input 1 (Phase)

Input 2 (Phase)

Input 3 (Phase)

OFF(0°) ON(0°) OFF(0°) ON(45°) OFF(0°) ON(45°) OFF(0°) ON(0°)

OFF(0°) OFF(0°) OFF(0°) OFF(0°) ON(0°) ON(0°) ON(0°) ON(0°)

OFF(0°) OFF(0°) ON(0°) ON(0°) OFF(0°) OFF(0°) ON(0°) ON(0°)

OFF(0°) ON(0°) OFF(0°) ON(0°) OFF(0°) ON(0°) OFF(0°) ON(0°)

Table 5.7. Continued T(Port 4)

T(Port 8)

Tthresh.

0 0.2825 0.274 0.002 0.2825 0.07 0.07 1.74

0 0.07 0.07 1.12 0.07 0.62 0.63 1.74

0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25

Sum Output Logic 0 Logic 1 Logic 1 Logic 0 Logic 1 Logic 0 Logic 0 Logic 1

Output Carry Logic 0 Logic 0 Logic 0 Logic 1 Logic 0 Logic 1 Logic 1 Logic 1

Output Port 4 OFF ON ON OFF ON OFF OFF ON

Output Port 8 OFF OFF OFF ON OFF ON ON ON

Table 5.8. Calculation of the contrast ration for the proposed plasmonic fulladder combinational logic function Input Optical Power for any Single Port (Pin (W)) 0 1 1 1 1 1 1 1

Output Optical Power (Pout (W)) for (∑)

Output Optical Power (Pout (W)) for (Cout)

Output Port 4

Output Port 8

0 0.2825 0.274 0.002 0.2825 0.07 0.07 1.74

0 0.07 0.07 1.12 0.07 0.62 0.63 1.74

OFF ON ON OFF ON OFF OFF ON

OFF OFF OFF ON OFF ON ON ON

114

Minimum Pout |ON and Maximum Pout |OFF (W) for (∑) Pout |ON = 0.274

Minimum Pout |ON and Maximum Pout |OFF (W) for (Cout) Pout |ON = 0.62

Pout |OFF = 0.07

Pout |OFF = 0.07

Cont -rast Ratio for (∑)

Cont -rast Ratio for (Cout)

6 dB

9.5 dB

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

Table 5.8 shows the contrast ratio for sum output is moderate due to the slightly difference between Pout |ON and Pout |OFF. In addition, the contrast ratio of the output carry is high. As a result, the performance of the proposed plasmonic full-adder combinational logic function is efficient because it has a moderate and high contrast ration between ON and OFF states for sum output and output carry, respectively.

5.3

The

Comparison

between

the

Proposed

Plamonic

Combinational Logic Functions and the Previous Works The proposed plasmonic combinational logic functions are compared to previous works as depicted in Table 5.9. Table 5.9. Comparison between the proposed plasmonic combinational logic functions and previous works Criteria/Paper

Software Program Used

This Thesis

FEM-2D

Ref. [30]

Ref. [31] Finite Difference Time Domain (FDTD)-2D

FEM-2D

Ref. [32]

Ref. [33]

Finite Difference Time Domain (FDTD)-2D

FEM-2D

Linear Interference Effects in Dielectric Crossed Waveguide Structure

Ring Resonator Based Metal– Insulator– Metal (MIM) Plasmonic Waveguides

Nonlinear Plasmonic Nanocavities

Ref. [34] Finite Difference Time Domain (FDTD)-2D Mach– Zehnder Interferomet -er (MZI) Using a Plasmonic MIM Waveguides

Proposed Structure

Nano-Rings InsulatorMetalInsulator (IMI) Plasmonic NanoWaveguides

Number of Proposed Combinational Logic Functions

4 Combinational Logic Functions

1 Combinational Logic Functions

1 Combinational Logic Functions

2 Combinational Logic Functions

2 Combinational Logic Functions

1 Combinational Logic Functions

Proposed Combinational Logic Functions

Half-Adder, HalfSubtractor, Comparator One-Bit, and Full-Adder

Half-Adder

Half-Adder

Half-Adder, and HalfSubtractor

Half-Adder and FullAdder

Comparator One-Bit

Plasmonic Metal Slot Waveguides

115

Chapter Five

Simulation Results and Discussion of the Proposed Plasmonic Combinational Logic Circuits

Size

850 nm × 400 nm

Not Available

10 𝜇m × 28 𝜇m

More than 1260 nm × 1260 nm

Less than 15 𝜇m × 15 𝜇m

17 𝜇m × 3 𝜇m

Operating Wavelength(s)

1550 nm

530 nm

800 nm

630 nm, 901 nm, 1775 nm, and 1856 nm

750 nm and 770 nm

1550 nm

Teflon

SiO2

Organically Modified Silica (ORMOSIL )

Air

Air

Non-Linear Kerr Material

Silver

Gold

Gold

Silver

Gold

Silver

Johnson and Christy Data

Not Available

Not Available

Drude-Lorentz Model

Not Available

DrudeLorentz Model

Transmission

Output Optical Power

Intensity

Transmission

Transmission and Contrast Ratio

Intensity

Dielectric Material Used Nobel Metal Used Model of Description the Relative Permittivity of the Metal Performance Measured

From the above table, it can be concluded that the proposed structure in this thesis has better performance than the other structures in previous works according to its size, number of plasmonic combinational logic functions gperformed, type of combinational logic functions, operating wavelength, and enhanced transmission in some states for some proposed plasmonic combinational logic function. For practical issue, the proposed structure and their applied proposed plasmonic combinational logic functions on it can be manufactured and implemented practically by using any modern technology or device that realize these functions with error ratio doesn’t exceed 9%.

116

Chapter Six

Conclusions and Suggestions for Future Works

CHAPTER SIX CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORKS 6.1 Conclusions In this thesis, seven plasmonic logic gates and four plasmonic combinational logic circuits have been proposed, designed, analyzed, simulated and achieved using 2-D FEM method by COMSOL Multiphysics package software (5.3). These gates and combinational logic functions are NOT, OR, AND, NOR, NAND, XOR, and XNOR as well as half-adder, half-subtractor, comparator one-bit, and full-adder, respectively. The gates and the functions are constructed by the Nano-ring IMI plasmonic waveguide structure. The operation principle of these gate and these functions is based on the constructive and destructive interferences between the input signal(s) and control signal(s). By employing the coupling property between straight stripes and Nanoring resonator waveguides, achieving a plasmonic logic gate or a plasmonic combinational logic function can occur. On the other hand, by changing the state of the input port(s), the position of the input port(s) and a control port(s), and the phase of incident light in these ports, the transmission in the output port(s) is minimized or maximized according to the required plasmonic logic gate or required plasmonic combinational logic function. To give a decision that the proposed plasmonic logic gate or plasmonic combinational logic function is achieving the truth table of one of the logic gates or one of the combinational logic function, it is necessary to know the threshold value of the transmission to distinguish between logic 0 and logic 1 states. Numerical simulations show that a transmission threshold exists in 0.25, which allows all proposed seven plasmonic logic gates to be achieved in one structure. This allows all proposed

117

Chapter Six

Conclusions and Suggestions for Future Works

four plasmonic combinational logic functions to be achieved in one structure also. Finally, the proposed works (plasmonic logic gates and plasmonic combinational logic functions) are considered fundamental building blocks in photonic integrated circuits and all-optical signal processing systems, and pave the way to achieve ultra-high-speed optical chip circuits, and all-optical computers. The main conclusions taken from these proposed works as follows: 1. The principle operation of the proposed plasmonic logic gates and the proposed plasmonic combinational logic functions is based on the constructive and destructive interferences between the input signal(s) and control signal(s). 2. The constructive and destructive interferences can be achieved by the same phase of the input (or control) signals and phase difference between the input or (control) signals, respectively. 3. The proposed plasmonic logic gates and the proposed plasmonic logic functions can be achieved by the right choice for assigning the ports in the proposed structures (which is an input port(s), which is a control port(s), and which is an output port(s)), and the right choice of phase angle which makes the constructive and destructive interferences between input signal(s) and control signal(s). 4. The proposed value of the transmission threshold which must be depended in order to achieve all seven proposed plasmonic logic gate in one structure and achieve all four proposed plasmonic combinational logic functions in one structure is 0.25 (or 25%). 5. The proposed structure of the proposed plasmonic logic gates is regarded as a general structure for performing any function for logic circuits which 118

Chapter Six

Conclusions and Suggestions for Future Works

have one-input/one output and two-inputs/one-output at 0.25 transmission threshold in addition to perform the proposed seven plasmonic logic gates. 6. The proposed structure of the proposed plasmonic combinational logic functions is regarded as a general structure for performing any function for logic circuits which have one-input/one-output, one-input/two-outputs, two-inputs/one-output, and two-inputs/two-outputs at 0.25 transmission threshold in addition to perform the proposed four plasmonic combinational logic functions. 7. The transmission in the proposed works is minimized or maximized depending on the size, shape, and parameters of the proposed structure (except the side stripes length), materials and refractive index of the chosen materials, the port position, the polarization of incident field and its phase. 8. According to the size, the shape, the parameters, and the materials of structure, the SPP is excited at 1550 nm wavelength. 9. The factors that affect the changing of the desired wavelength (1550 nm), when the size and shape of the proposed structures remain unchanged, are metal, dielectric (slightly linear proportional with the desired wavelength), outer radius of the Nano-ring (linear proportional with the desired wavelength), side stripes length (linear proportional with the desired wavelength with slope of 2), and stripes width. While the factors, which have a small effect on the changing of the desired wavelength under the same conditions are the inner radius of the Nano-ring and coupling distance.

119

Chapter Six

Conclusions and Suggestions for Future Works

6.2 Suggestions for Future Works Suggestions for future research are: 1. Constructing the proposed plasmonic logic gates and the proposed plasmonic logic circuits practically via the modern fabrication technology and modern devices. 2. Reducing the size and structure parameters as much as possible, in accordance with its manufacturer and application in fabrication techniques. 3. Increasing the numbers and functions of the plasmonic combinational logic circuits in one structure to produce all-optical Arithmetic Logic Unit (ALU). 4. Reducing the losses due to the metal by choosing a metal which has low losses such as graphene or using a gain material to compensate the losses due to the metal used. 5. Constructing plasmonic reversible logic gates such as Wire gate, Not gate, Swap gate, Feynman gate, Toffoli gate, and Fredkin gate. 6. Constructing plasmonic reversible combinational logic circuits. 7. Proposing a structure to perform the proposed plasmonic logic gates or the proposed plasmonic combinational logic functions with a high transmission threshold value up to a default threshold value of 0.5 or 50%. 8. Improving the contrast ratio as much as possible for plasmonic logic gates and for plasmonic combinational logic functions to improve their performance. 9. Enhancing the transmission value as much as possible to be more than 90% or exceeding 100% for all ON output states.

120

Chapter Six

Conclusions and Suggestions for Future Works

10. Reducing the transmission value as much as possible for all OFF output states. 11. Using hybrid plasmonic waveguide as a new technique used recently in modern research. 12. Proposing a general structure to perform more than two-inputs/twooutputs plasmonic logic circuit.

121

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159

Appendix (A)

APPENDIX (A) DESCRIPTION OF SPPs IN METALLIC NANOSTRUCTURES WITH ELECTROMAGNETIC FIELDS A.1 The Optical Properties of Metals Before explaining Maxwell’s equations and electromagnetic waves propagation in plasmonic structures, the behavior of metals in these structures must be demonstrated. Metals behave in a variety of ways with respect to different parts of the electromagnetic spectrum of the incident light wave. They are highly reflective for frequencies up to the visible part of the spectrum, preventing light from penetrating them, which is why, for lower frequencies, they are generally considered as good conductors [97]. On the other hand, for near infrared and higher frequencies, the amount of field penetration of the incident light into metals increases significantly, resulting in increased absorption of the light. At ultraviolet frequencies, metals behave as dielectric media, allowing electromagnetic waves to propagate through them with different degrees of attenuation. For noble metals, such as gold or silver, strong absorption between electronic bands due to inter-band transition occur, which is why they tend to be very lossy in this regime. Table A.1 shows the quality factors and SPP propagation lengths for four common plasmonic metals that are the most commonly used in plasmonic nanostructures [98].

A-1

Appendix (A)

Table A.1. The quality factors and SPP propagation lengths for four common plasmonic metals

Where 𝑄𝐿𝑆𝑃𝑅 and 𝑄𝑆𝑃𝑃 are Quality factor of Localized Surface Plasmon Resonance (LSPR) and Quality factor of SPP, respectively. These two factors are described by Equations (A.1) and (A.2), respectively [99]. While LSPP is a propagation length of SPP which is described by Equation (A.3) [63, 69]. QLSPR = −𝜀𝑟𝑒 /𝜀𝑖𝑚

(A.1)

2 QSPP =−𝜀𝑟𝑒 /𝜀𝑖𝑚

(A.2)

LSPP =

1 2𝑖𝑚[𝛽]

=

1 2𝑘𝑠𝑝𝑝 𝑖𝑚

= 𝜆0

𝜀𝑟𝑒 2 2𝜋𝜀𝑖𝑚

𝜀 +𝜀

{ 𝜀𝑟𝑒 𝜀 2}

3⁄2

𝑟𝑒 2

(A.3)

Where 𝜀𝑟𝑒 is a real part of the complex dielectric function (permittivity) of the metal, 𝜀𝑖𝑚 is an imaginary part of dielectric function (permittivity) of the metal, 𝑘𝑠𝑝𝑝 𝑖𝑚 is an imaginary part of propagation constant, and 𝜀2 is permittivity of dielectric medium.

A-2

Appendix (A)

The two factors (QSPP and LSPP) are explained and defined in Appendix (D). From Table A.1, Silver exhibits the lowest losses of current materials in both the visible, near-infrared (NIR) at telecommunication wavelengths as well as higher QLSPR, QSPP, and LSPP than other metals. Therefore, this thesis used this material (Silver). For these advantages it has overcome other metals in the same wavelength (1550 nm). The dispersive properties of metals can be described by a complex dielectric function 𝜀(𝜔) which is a function of frequency (wavelength), which is related to the conductivity 𝜎 as shown in Equation (A.4) [69]. 𝜀(𝜔) = 1+

𝑖𝜎(𝐾,𝜔)

(A.4)

𝜀0 𝜔

Where 𝜔 is the angular frequency of an incident plane wave, 𝐾 is the wavevector and 𝜀0 is permittivity of the vacuum. 𝜀 ( 𝜔 )

can be

separated into real and imaginary parts, 𝜀𝑟𝑒 and 𝜀𝑖𝑚 as shown in Equation (A.5) related to the complex refractive index 𝑛(𝜔) as shown in Equation (A.6). 𝜀(𝜔) = 𝜀𝑟𝑒 + 𝑖𝜀𝑖𝑚

(A.5)

𝜀(𝜔) = 𝑛(𝜔) 2 = (𝑛𝑟𝑒 (𝜔) + 𝑖𝑘𝑖𝑚 (𝜔)) 2

(A.6)

From the above two equations, the derivation of the following four relationships between the real part of 𝜀(𝜔) and 𝑛(𝜔), and the imaginary part of them is easy [36]. 𝜀𝑟𝑒 = 𝑛𝑟𝑒 2 − 𝑘𝑖𝑚 2

(A.7)

𝜀𝑖𝑚 = 2𝑛𝑟𝑒 𝑘𝑖𝑚

(A.8) A-3

Appendix (A)

𝑛𝑟𝑒 = √ 𝑘𝑖𝑚 =

𝜀𝑟𝑒 2

1

+ √𝜀𝑟𝑒 2 + 𝜀𝑖𝑚 2 2

(A.9)

𝜀𝑖𝑚

(A.10)

2𝑛𝑟𝑒

Where 𝑘𝑖𝑚 is the extinction coefficient which determines the amount of optical absorption of the EM waves propagating through the medium. It is useful to study the permittivity of the metal for different frequency regimes with respect to the plasma frequency: i.e for 𝜔 < 𝜔p and 𝜔 > 𝜔p. For high frequencies close to 𝜔p, the permittivity is predominantly real as in Equation A.11: 𝜀(𝜔) = 1 −

𝜔𝑝 2

(A.11)

𝜔2

It can be noted from the above equation that at frequencies less than the plasma frequency 𝜔p, the dielectric permittivity of the metals is negative, i.e. the plasma of the excited electrons protects the interior of metals from the external applied field. Thus, metals (such as silver) in this regime tend to provide very low resistance to the external field, and therefore have a good conductivity [100-101]. However, when the frequencies of the incident plane wave are larger than the plasma frequency, metals behave as a dielectric material with real and positive permittivity. This thesis used Johnson and Christy data to describe the permittivity of the metal used (Silver) because it is more practical than the analytical equation of other models (such as Drude Model) which depend on practical points to describe the permittivity of the metal (Rounding and fitting do not occur). In Drude model, the rounding and fitting process A-4

Appendix (A)

will occur and this leads to an approximation in the value of permittivity at given point of wavelength or frequency, which results in a high approximation in the final results. In addition, this thesis worked on frequency domain (FEM method) and the accuracy of describing the permittivity is a very important factor since these points vary with frequency or rather with wavelength. Moreover, according to [67], when the dimensions of the parts of the structure become less than 50 nm, the Drude model becomes inefficient in these dimensions while Johnson and Christy data were designed for dimensions which reach to a few of Angstroms [67].

A.2 Maxwell’s Equations and Electromagnetic Wave Propagation Maxwell’s equations describe the electromagnetic field for a given system through four vectors which are strength of the electric field (𝑬), the displacement (𝑫), the strength of magnetic field (𝑯), and the flux density (𝑩) with the external charge and current densities 𝜌 ext and 𝐉ext [102]. The Maxwell’s equations are described in the following four Equations: ∇ . D = 𝜌ext

(A.12)

∇.B=0

(A.13)

∇ × E = −𝜕𝐁/𝜕t

(A.14)

∇ × H = 𝐉ext + 𝜕D/𝜕t

(A.15)

A-5

Appendix (A)

The four fields are further linked via the polarization P and magnetization M by [103]: D = 𝜀0 𝐄 + P H=

1

(A.16)

𝐁–M

(A.17)

μ0

Where ε0 and μ0 are the electric permittivity and magnetic permeability of the vacuum, respectively. P describes the electric dipole moment per unit volume inside the material, caused by the alignment of microscopic dipoles with the electric field. The great advantage of this approach is that the macroscopic electric field includes all polarization effects. the following limits them to linear, isotropic and nonmagnetic media. One can define the constitutive relations [69]. D = 𝜀0 𝜀r E

(A.18)

B = μ0 μ r H

(A.19)

Where 𝜀 r and μr are electric permittivity and magnetic permeability of the material. In order to investigate the physical properties of surface plasmon polaritons (SPPs), one must apply Maxwell’s equations (A.12 to A.15) to the flat interface between a metal and a dielectric. To present this discussion most clearly, it is advantageous to present the equations first in a general form applicable to the guiding of electromagnetic waves, the wave equation. In the absence of external charge and current densities, the curl equations (A.14, A.15) can be combined to yield Equation (A.20) [100]:

A-6

Appendix (A)

∇ × ∇ × E = − μ0𝜕2 D/𝜕t2

(A.20)

Using the identities ∇×∇×E = ∇ (∇·E) −∇2E as well as ∇. (𝜀 E) = E·∇𝜀 + 𝜀 ∇.E, and remembering that due to the absence of external source ∇ · D = 0, Eq. A.20 can be rewritten as [69]: ∇(−(𝐄·∇𝜀) /𝜀) −∇2 E = −𝜇0 𝜀0 𝜀𝑟 𝜕2𝐄/𝜕𝑡2

(A.21)

For negligible variation of the dielectric profile 𝜀𝑟 = 𝜀𝑟(r) over distances about one optical wavelength, Eq. A.21 simplifies the central equation of electromagnetic wave theory [69]. ∇2 E – (𝜀𝑟/c2) 𝜕2𝐄/𝜕𝑡2 = 0

(A.22)

Practically, this equation has to be solved separately in regions of constant 𝜀𝑟, and the obtained solutions have to been matched using appropriate boundary conditions. Eq. A.22 can be represented in a form suitable for the description of confined propagating wave, there is two steps. First, assume in all generality a harmonic time dependence. E(r, t) = E(r) exp(−ωt) of the electric field, where r represents position vector. Insert into Eq. A.22 to yield [69]: ∇2𝐄+𝐾02𝜀𝑟𝐄 = 0 Where 𝐾0 =

(A.23) 𝜔 c

= 2𝜋λ0 is the wave vector of the propagating wave in

vacuum. Where c is speed of light in free space and 𝜔 frequency of incident light. Eq. A.23 is known as the Helmholtz equation. The propagation geometry is shown in Figure (A.1). Assume for simplicity a one-dimensional problem, i.e. 𝜀𝑟 depends only on one spatial coordinate. Specifically, the waves propagate along the x-direction of a Cartesian coordinate system, and show no spatial variation in the perpendicular inplane y-direction (see Figure A.1) [69]. A-7

Appendix (A)

In order to find the surface plasmons which are waves bound to the interfaces (x-z plane of incident light), the magnitudes of the electric and magnetic pharos fields can be written as [104]:

Figure (A.1) Definition of a planar waveguide geometry. The waves propagate along the x-direction in a Cartesian coordinate system [103] (𝑟) = (𝑥, 𝑧) = (𝑧) 𝑒𝑖𝛽𝑥

(A.24)

(𝑟) = (𝑥, 𝑧) = (𝑧) 𝑒𝑖𝛽𝑥

(A.25)

Where β is propagation constant, in the x direction. Creating surface plasmon polariton depends on the type of polarization. Therefore 𝜀𝑟 = (z). Applied to electromagnetic surface problems, the plane z = 0 coincides with the interface sustaining the propagating waves. In this case, the differential operators with respect to the coordinates x and y can be written as [104]. ∂ ∂𝑥 ∂ ∂𝑦

= 𝑖𝛽

(A.26)

=0

(A.27)

This makes it possible to express the Laplacian of any of the fields as [104]: A-8

Appendix (A)

∇2 F (x, z) = 𝜕2F (x, z)/𝜕z2 – 𝛽2 F (x, z) = 0

(A.28)

The Laplacian in Eq. (A.28) and the fields in Eq. A.24 can be used to simplify the Helmholtz's equations to one dimension [104]. 𝜕2E (z)/𝜕z2 + (K02 𝜀𝑟 – 𝛽2) E (z) = 0

(A.29)

Naturally, a similar equation exists for the magnetic field H. Eq. A.29 is the starting point for the general analysis of guided electromagnetic modes in waveguides, and an extended discussion of its properties and applications and similar treatments of photonics and optoelectronics. In order to use the wave equation for determining the spatial field profile and dispersion of propagating waves, now there is a need to find explicit expressions for the different field components of E and H. This can be achieved in a straight forward way using the curl equations (A.14, A.15). Harmonic time dependence 𝜕/𝜕𝑡=−𝑖𝜔 will arrive at the following set of coupled equations [69]. 𝜕𝐸𝑧/𝜕𝑦 − 𝜕𝐸𝑦/𝜕𝑧 = 𝑖𝜔𝜇0𝐻𝑥

(A.30)

𝜕𝐸𝑥/𝜕𝑧 − 𝜕𝐸𝑧/𝜕𝑥 = 𝑖𝜔𝜇0𝐻𝑦

(A.31)

𝜕𝐸𝑦/𝜕𝑥 − 𝜕𝐸𝑥/𝜕𝑦 = 𝑖𝜔𝜇0𝐻𝑧

(A.32)

𝜕𝐻𝑧/𝜕𝑦 − 𝜕𝐻𝑦/𝜕𝑧 = −𝑖𝜔𝜀0𝜀𝑟𝐸𝑥

(A.33)

𝜕𝐻𝑥/𝜕𝑧 − 𝜕𝐻𝑧/𝜕𝑥 = −𝑖𝜔𝜀0𝜀𝑟𝐸𝑦

(A.34)

𝜕𝐻𝑦/𝜕𝑥 − 𝜕𝐻𝑥/𝜕𝑦 = −𝑖𝜔𝜀0𝜀𝑟𝐸𝑧

(A.35)

For propagation along the x-direction (𝜕/𝜕𝑥=𝑖𝛽) and homogeneity in the y-direction (𝜕/𝜕𝑦=0), this system of equation is simplified to [69]: 𝜕𝐸𝑦/𝜕𝑧 = −𝑖𝜔𝜇0𝐻𝑥

(A.36) A-9

Appendix (A)

𝜕𝐸𝑥/𝜕𝑧 − 𝑖𝛽𝐸𝑧= 𝑖𝜔𝜇0𝐻𝑦

(A.37)

𝑖𝛽𝐸𝑦 = 𝑖𝜔𝜇0𝐻𝑧

(A.38)

𝜕𝐻𝑦/𝜕𝑧 = 𝑖𝜔𝜀0𝜀𝑟𝐸𝑥

(A.39)

𝜕𝐻𝑥/𝜕𝑧 – 𝑖𝛽𝐻𝑧 = − 𝑖𝜔𝜀0𝜀𝑟𝐸𝑦

(A.40)

𝑖𝛽𝐻𝑦 = −𝑖𝜔𝜀0𝜀𝑟𝐸𝑧

(A.41)

It can easily be shown that this system allows two sets of selfconsistent solutions with different polarization properties of the propagating waves. The first set are the Transverse Magnetic (TM or PPolarized) modes, where only the field components 𝐸𝑥, 𝐸𝑧 and 𝐻𝑦 are nonzero, and in the second set, the Transverse Electric (TE or SPolarized) modes, only 𝐻𝑥, 𝐻𝑧 and 𝐸𝑦 are nonzero. For TM modes, the system of governing Equations (A.36-A.41) is reduced to [69]: 𝐸𝑥 = − (𝑖𝜕𝐻𝑦/𝜕𝑧)/𝜔𝜀0𝜀𝑟

(A.42)

𝐸𝑧 = −𝛽𝐻𝑦/𝜔𝜀0𝜀𝑟

(A.43)

In addition, the wave equation for TM modes is: ∂2𝐻𝑦(𝑧)/𝜕z2 + (𝐾02𝜀𝑟−𝛽2) 𝐻𝑦(𝑧) = 0

(A.44)

For TE modes the analogous set is 𝐻𝑥 = (𝑖𝜕𝐸𝑦/𝜕𝑧)/𝜔𝜇0

(A.45)

𝐻𝑧 = 𝛽𝐸𝑦/𝜔𝜇0

(A.46)

In addition, the TE wave equation is: ∂2𝐸𝑦 (𝑧)/𝜕z2 + (𝐾02𝜀𝑟−𝛽2) (𝑧) = 0

(A.47) A-10

Appendix (B)

APPENDIX (B) THE POLARIZATION OF INCIDENT LIGHT B.1 Polarization of Incident Light In which the plane of incidence can be defined as the x-z plane. In these conditions, for a plane wave propagating in the x-z plane, the magnitudes of the pharos fields are dependent on the coordinates x and z, but constant along the y direction. The creating surface plasmon polariton is dependent on the type of light polarization (S or P) [104]. 1. S-polarization or TE-polarization The incident electromagnetic wave which is the electric field component E is perpendicular to the plane of incidence, this type of polarization is called SPolarized, and results in an evanescent wave 𝐸y, parallel with the y coordinate. The component of the E-field that lies in the x-y plane is continuous as moving across the plane of the interface. Here, all E-fields are in the y-direction, which is in the plane of the interface [104]. This case is shown in Figure (B.1).

Figure (B.1) S-Polarization [104] B-1

Appendix (B)

2. P-polarization or TM-polarization The incident electromagnetic wave which is the magnetic field component H is perpendicular to the plane of incidence. This type of polarization is called P-Polarized. The component of the E-field which lies in the x-z plane is continuous as moving parallel to the plane of the interface. Here, all E-fields are in the parallel to incident plane, which is in the plane of the interface [104]. This case shown in Figure (B.2).

Figure (B.2) P-polarization [104]

B-2

Appendix (B)

B.2 Existence of SPPs in Which Mode The most simple geometry sustaining SPPs is that of a single, flat interface as shown in Figure (B.3) between a dielectric, non-absorbing half space (z > 0) with positive real dielectric constant 𝜀𝑑 and an adjacent conducting half space (z < 0) described via a dielectric function 𝜀𝑚(ω). The requirement of metallic character implies that Re [𝜀𝑚] < 0. For metals, this condition is fulfilled at frequencies below the bulk plasmon frequency 𝜔p needed to look for propagating wave solutions confined to the interface, i.e. with evanescent decay in the perpendicular z-direction.

Figure (B.3) Geometry for SPP propagation at a single interface between a metal and a dielectric [105] At first look at TM solutions. Using the equation set (A.42-A.44) in both half spaces yields [69]. For z > 0 and 𝐻𝑦 (𝑧) = 𝐴𝑑 exp(𝑖𝛽𝑥) exp(−𝐾𝑑𝑧)

(B.1) B-3

Appendix (B)

𝐸𝑥 (𝑧) = 𝑖𝐴𝑑 𝐸𝑧 (𝑧)= −𝐴𝑑

1 ωε0 εd β ωε0 εd

𝐾𝑑 exp(𝑖𝛽𝑥) exp(−𝐾𝑑𝑧)

(B.2)

exp(𝑖𝛽𝑥) exp(−𝐾𝑑𝑧)

(B.3)

For z < 0 and 𝐻𝑦 (𝑧) = 𝐴𝑚 exp(𝑖𝛽𝑥) exp(𝐾𝑚𝑧) 𝐸𝑥 (𝑧) = −𝑖𝐴𝑚 𝐸𝑧 (𝑧) = −𝐴𝑚

1

𝐾𝑚 exp(𝑖𝛽𝑥) exp (𝐾𝑚𝑧)

(B.5)

exp(𝑖𝛽𝑥) exp(𝐾𝑚𝑧)

(B.6)

ωε0 εd β

ωε0 εd

(B.4)

For z < 0. 𝐾𝑖 ≡ 𝐾𝑧, (i = m, d) is the component of the wave vector perpendicular to the interface in the two media. 𝐴𝑚 and 𝐴𝑑 are the amplitude of electric and magnetic fields in the metal and dielectric, respectively. Its a reciprocal value, Z = 1/|𝐾𝑧|, which defines the evanescent decay length of the fields perpendicular to the interface [69]. This quantifies the confinement of the wave. Continuity of 𝐻𝑦 and 𝐸𝑧 at the interface requires that 𝐴𝑑 = 𝐴𝑚 and. Thus: 𝐾𝑑 /𝐾𝑚 = −𝜀𝑑 /𝜀𝑚

(B.7)

Note that with the convention of the signs in the exponents in (B.1-B.3) and (B.4-B.6), confinement to the surface demands Re [𝜀m] < 0 if 𝜀𝑑 > 0. The surface waves exist only at interfaces between materials with opposite signs of the real part of their dielectric permittivity, i.e. between a conductor and an insulator. The expression for 𝐻𝑦 further has to fulfill the wave Equation Eq. (A.44), yielding [69]: 2 𝐾𝑚 = 𝛽2 − 𝐾02 𝜀𝑚

(B.8)

B-4

Appendix (B)

𝐾𝑑2 = 𝛽2 − 𝐾02 𝜀d

(B.9)

Combining Equations (B.8 and B.9) with Eq. B.7will arrive at the central result of this section. The dispersion relation of SPPs propagates at the interface between the two half spaces that is: 𝛽 = 𝐾0√

ε 𝑚ε 𝑑

(B.10)

ε 𝑚 +ε 𝑑

This expression is valid for both real and complex 𝜀𝑚, i.e. for conductors without and with attenuation. For (TE) modes, the corresponding fields can be written as: For z > 0 and E𝑦 (𝑧) = 𝐴d exp(𝑖𝛽𝑥) exp(-𝐾d𝑧) Hx (𝑧) = −𝑖𝐴d Hz (𝑧) = 𝐴d

1 ωμ0

β ωμ0

(B.11)

𝐾d exp(𝑖𝛽𝑥) exp (-𝐾d 𝑧)

exp(𝑖𝛽𝑥) exp(-𝐾d𝑧)

(B.12) (B.13)

For z < 0 and

E𝑦 (𝑧) = 𝐴𝑚 exp(𝑖𝛽𝑥) exp(𝐾𝑚𝑧)

(B.14)

1

H𝑥 (𝑧) = 𝑖𝐴𝑚 ωμ 𝐾𝑚 exp(𝑖𝛽𝑥) exp (𝐾𝑚𝑧) 0

β

H𝑧 (𝑧) = 𝐴𝑚 ωμ exp(𝑖𝛽𝑥) exp(𝐾𝑚𝑧)

(B.15) (B.16)

0

A gain from the boundary condition (continuity of Ey and Hx) at the interface may yield: C (𝐾d + 𝐾𝑚) = 0

(B.17) B-5

Appendix (B)

Where C is a constant. As the surface waves require that Re [𝐾d] > 0 and Re [𝐾𝑚] > 0, so Eq. (B.17) is obtained only when (𝐴d = 0) and because (𝐴d = 𝐴m = 0). It means no surface wave can exist for (TE) modes. As a result, existence of SPPs is only possible with TM polarization [40]. The following flowchart shown in Figure (B.4) describes the equations, on which SPP is dependent [106].

Figure (B.4) Flowchart for describing the equations, on which SPP is dependent [106]

B-6

Appendix (C)

APPENDIX (C) SPPS EXCITATIONS MECHANISMS C.1 SPPs Excitations Mechanisms The mechanisms of SPPs excitation are explained in the following sections. A. Prism coupling This technique, also known as attenuated total internal reflection, involves the coupling of the SPPs to the evanescent electro-magnetic field established upon total internal reflection of a light beam at a surface in an optically dense medium [107]. Two different geometries for prism coupling are possible as shown in Figure (C.1). In the Kretschmann configuration, the metal film is steamed on top of a glass prism. The film is illuminated through the dielectric prism at an angle of incidence greater than the angle of total internal reflection. The wave vector of light is increased in the optically dense medium [107]. At a certain angle 𝜃 of incidence where the in-plane component of the photon wave vector in the prism synchronizes with the SPP wave vector on an air-metal surface, resonant light tunneling through the metal film occurs and light is coupled to the surface polaritons as depicted in Equation (C.1) [107].

(a)

(b)

Figure (C.1) Prism coupling: (a) Kretschmann, (b) Otto configuration [107] C-1

Appendix (C)

𝜔

𝛽 = √𝜀𝑝𝑟𝑖𝑠𝑚 sin 𝜃 𝑐

(C.1)

Under these resonant conditions, a sharp minimum is observed in the reflectivity from the prism interface as light can be coupled to SPPs with almost 100% efficiency [107]. When increasing the metal film thickness, the efficiency of the SPP excitation reduces as the tunneling distance increases [107]. SPP on an interface between the prism and metal cannot be excited in this geometry becuase the wave vector of SPP at this interface is larger than the photon wave vector in the prism at all incident angles. To be able to excite SPP on the internal metal interface, an additional dielectric layer with a refractive index smaller than of the prism should be deposited between the prism and the metal film [107]. In such a two-layer geometry, the photon tunneling through this additional dielectric layer can provide resonant excitation of SPP on the inner interface. Thus, both SPP modes (on the surface and the interface) can be excited in such a configuration at different angles of illumination [107]. When the thickness of metal (or surfaces of bulk metal) is increased, the Kretschmann configuration cannot be used, SPP can be excited in the Otto configuration. Here, the prism where total internal reflection happens is placed close to the metal surface, so that photon tunneling occurs through the air gap between the prism and the surface [107]. The resonant conditions are analogous to those in the Kretschmann configuration. This configuration is also favored when direct contact with the metal surface is unwanted, e.g. for studying the surface quality [107]. B. Grating coupling The mismatch in wave vector between the in-plane momentum kx = k sin 𝜃 of impinging photons and 𝛽 can also be overcome by using diffraction effects C-2

Appendix (C)

at a grating pattern on the metal surface [107]. For a one-dimensional grating of grooves with lattice constant a, as depicted in Figure (C.2), phase-matching takes place whenever the condition in Equation (C.2) is fulfilled [107]. 𝛽 = k sin 𝜃 ± n G

(C.2)

Where G = 2𝜋/a is the reciprocal vector of the grating and n = 1, 2, 3…..As with prism coupling, excitation of SPPs is detected as a minimum in the reflected light [107].

Figure (C.2) Grating coupling of a light with wave vector k impinging on a metal grating surface of period a [107]

C. Near field excitation mechanism In contrast to the macroscopic SPPs exciation schemes such as prsim or grating coupling, near-field optical microscopy represents a point source to provide local excitation of SPPs over a subwavelength area [108]. In the typical near-field SPPs excitation configuration depicted in Fig. C.3, the illumination light from a small probe tip of aperture size (a) (a ≤ 𝜆𝑆𝑃𝑃 ≤ 𝜆0 ) has wave vectors k0≤ 𝑘𝑆𝑃𝑃 ≤ 𝑘, thus allowing a nearfield coupling of the phase-matched C-3

Appendix (C)

subwavelength aperture diffracted light into SPPs. Using such probes in nearfield scanning optical microscopy (NSOM), SPPs at different positions of the metal surface can be locally excited.

Figure (C.3) Excitation with a near-field scanning optical microscopy (NSOM) probe [109] D. Excitation using surface features diffraction When the surface is randomly rough in the near-field region, the diffracted light components possess all wave vectors and thus SPPs can be excited by conventional illumination without any special arrangements. Unlike using the diffraction grating, this is a non-resonant excitation. Similarly, SPPs can also be optically excited through light diffraction from surface features as shown in Figure (C.4) [110].

Figure (C.4) Diffraction on surface features [111]

C-4

Appendix (C)

E. Excitation using highly focused optical beams A typical setup of using highly focused optical beams for SPP excitation is sketched in Figure C.5. Instead of using a prism to satisfy the total internal reflection and SPP resonance condition, a high numerical index, which matched oil-immersion microscope objective, is brought into contact with the glass substrate, on which a thin metal film is deposited [112]. Owing to the high numerical aperture of the lens, the broad angular spread of the focused illumination beam is large enough to have the resonance wave vector for SPP excitation at the metal-air interface. The highly focused illumination beam provides localized SPPs excitation over a diffraction–limited area [112].

Figure (C.5) Excitation with highly focused optical beams [113]

C-5

Appendix (D)

APPENDIX (D) PARAMETERS PERFORMANCE OF PLASMONIC WAVEGUIDES D.1 Definition of Confinement, Propagation Length, Quality Factor and Figure of Merit A. Definition of confinement The rapid evolution of PWs with strongly confined SPPs demonstrated their ability to achieve the sub-wavelength of the conventional DWs [114]. Basically, the sub-wavelength confinement of light in the plasmonic waveguide is associated with engineering the evanescent fields outside the core of the waveguide [115]. When an optical ray traverses a flat interface between two different dielectrics which can be seen in Figure (D.1 (a)), the light is partially reflected back to the core medium and is partly refracted in the cladding medium. Snell’s law governs the angle of reflection and refraction. If 𝑛1 > 𝑛2 (𝑛1 and 𝑛2 are the refractive index of the two dielectrics) and the incident angle is greater than the critical angle 𝜃c, as shown in Equation (D.1), light is totally reflected back to the core medium and evanescently decays in the cladding medium. This process is known as total internal reflection (TIR) [71]. 𝜃c = 𝑠𝑖𝑛−1

𝑛2

(D.1)

𝑛1

However, if the cladding is a metal (e.g. Au or Ag), the SPP can be excited when certain phase matching conditions are met, and the energy from the excitatory light wave can be transferred to the free electron to form an SPP which spreads at the metal - insulator surface. SPP has a shorter wavelength than a free excited light. Moreover, a very small skin depth can be achieved where the D-1

Appendix (D)

energy is rapidly degraded in the metal as can be seen in Figure D.1 (b). In a more complicated sandwich structure, the dielectric waveguide (Figure D.1 (c)) could not achieve sub-wavelength of light confinement because the diffraction limit phenomenon. For the plasmonic waveguide as shown in Figure (D.1 (d)), which can be described as a MIM structure. In this type of structure, the wavelength of the resonance, the thickness of the core layer and the skin depth of the evanescent waves in the cladding medium achieve the sub-wavelength light confinement in the waveguide core. While, the confinement factor in IMI PWs is less in MIM PWs as shown in the comparison between them.

Figure (D.1) (a) TIR happens when 𝑛1 > 𝑛2 (b) In a One dimensional subwavelength light confinement in a metal-dielectric interface, 𝜀 m is the permittivity of the metal and 𝜀 d is the permittivity of the dielectric (c) Twodimentional light confinement in a sandwiched DW (d) Two dimensional subwavelength light confinement in a sandwiched PW [116]

D-2

Appendix (D)

B. Definition of propagation length The propagation length is defined as the distance space where a mode can travel before the energy density decays to 1/e of its original value [40, 117]. It described by Equation (A.3) in Appendix A. C. Definition of quality factor The quality factor is the ratio of twice propagation length to the resonance wavelength of SPPs [72]. It is described in Equation (D.2) in addition to previous description in Equation (A.2) [72]. QSPP =2𝜋Lspp / 𝜆spp

(D.2)

D. Definition of figure of merit The figure of merit (FoM) is a quality measure for surface plasmon waveguides. It is defined as benefit-to-cost ratio where the benefit is confinement and the cost is attenuation for a particular mode [73]. It can be described by Equations below [74]. FoMconfinment = 𝜆0 / 𝛿

(D.3)

Where 𝛿 is a skin depth of the medium in meters. FoMpropagation = Lspp / 𝜆spp

(D.4)

Substituting Eq. (D.2) in Eq. (D.4), yields: FoMpropagation = QSPP / 2𝜋

(D.5)

When applying the definition of FoM, the result is the following equations: FoM = FoMconfinment / FoMpropagation

(D.6)

FoM = (𝜆0 / 𝛿) / (Lspp / 𝜆spp) =( 𝜆0 𝜆spp) / (𝛿 Lspp) = (2𝜋 𝜆0) / (𝛿 QSPP)

(D.7)

D-3

‫الخالصة‬ ‫على الرغم من أن الضوئيات تعرض حالً جذابًا لسرعة اإللكترونيات المحدودة‪ ،‬إال أن‬ ‫تقليل حجم المكونات الضوئية الضخمة يعد أحد المشكالت الرئيسية في تنفيذ الدوائر المتكاملة‬ ‫الضوئية‪ .‬يمكن أن تكون دوائر البالزمية (أدلة الموجات البالزمية في هذا العمل)‪ ،‬التي تحصر‬ ‫بإحكام الموجات الكهرومغناطيسية في الواجهة المعدنية العازلة أو العازلة المعدنية‪ ،‬حالً محتمالً‬ ‫لملء الفجوات في اإللكترونيات (عرض النطاق الترددي الكبير والسرعة الفائقة) والضوئيات‬ ‫(حد الحيود بسبب حجم التصغير)‪ .‬في هذه األطروحة‪ ،‬تم استخدام أدلة الموجات البالزمية‬ ‫العازلة النانوية الحلقيّة (‪ )IMI‬كتكوين جديد القتراح وتحليل وتصميم ومحاكاة وتنفيذ بوابات‬ ‫المنطق البصري الكلّية ووظائف منطق التوافق البصري الكلّية‪ .‬في هذه األطروحة‪ ،‬تم تصميم‬ ‫هياكل البوابات المنطقية البالزمية المقترحة ووظائف المنطق ومحاكاتها عدديًا باستخدام طريقة‬ ‫العناصر المحددة (‪ )FEM‬في برنامج حزمة ‪ )5.3( COMSOL Multiphysics‬واستخدام‬ ‫شرط الحدود المطابق تما ًما المتصاص الطبقة مع بنية ثنائية األبعاد‪ .‬مواد الهيكل المقترح‬ ‫للبوابات المنطقية البالزمية هي الفضة والتفلون‪ .‬تم تمثيل االشرطة وحلقات النانو االثنين بمادة‬ ‫الفضة ‪ ،‬في حين أن الجزء المتبقي من الهيكل هو مادة التفلون‪ .‬في حين أن مواد هيكل وظائف‬ ‫المنطق المنطقي التوافقي البالزمي هي نفسها‪ ،‬ولكن بما في ذلك مادة التوصيل الكهربائي المثالي‬ ‫(‪ )PEC‬كمرآة مثالية بين اثنين من الهياكل الفرعية للبوابات المنطقية البالزمية المقترحة‪.‬‬ ‫البوابات التي تم تحليلها ‪NOT‬و ‪ OR‬و‪ AND‬و‪ NOR‬و‪ NAND‬و‪ XOR‬و‪ .XNOR‬في‬ ‫حين أن وظائف المنطق التوافقية التي تم تحليلها هي ‪ ،Half-Adder‬و ‪ ،Half-Subtractor‬و‬ ‫‪ ،Comparator One-Bit‬و ‪ .Full-Adder‬ويستند مبدأ التشغيل لهذه البوابات والوظائف إلى‬ ‫التداخل البناء والتداخل المد ّمر بين إشارة (إشارات) اإلدخال وإشارة (إشارات) التحكم‪ .‬تُظهر‬ ‫المحاكاة العددية أن عتبة اإلرسال موجودة في (‪ )0.25‬والتي تتيح تحقيق جميع البوابات المنطقية‬

‫البالزمية السبعة المقترحة في هيكل واحد‪ ،‬وكذلك تحقيق جميع وظائف منطق التوافقية األربعة‬ ‫المقترحة في هيكل واحد‪ .‬في هذا العمل‪ ،‬استخدم نفس البنية بنفس األبعاد عند الطول الموجي‬ ‫‪ 1550‬نانومتر لجميع البوابات المنطقية البالزمية المقترحة ووظائف المنطق التوافقية البالزمية‪.‬‬ ‫ومع ذلك‪ ،‬في بعض الحاالت‪ ،‬يتجاوز نقل بوابات المنطق البالزمية المقترحة ووظائف المنطق‬ ‫التوافقية البالزمية ‪ ،٪ 100‬على سبيل المثال‪ ،‬في ‪ NOT‬بوابة (‪ ،)٪ 112.3‬في بوابة ‪OR‬‬ ‫(‪ ،)٪ 175‬في بوابة ‪ ،)٪ 112.3( NAND‬وفي بوابة ‪ )٪ 175( XNOR‬وكذلك في‬ ‫‪ ،)٪ 174( Comparator One-Bit‬وفي ‪ ٪ 112( Full-Adder‬و‪ .)٪ 174‬عالوة على‬ ‫ذلك‪ ،‬تم تصميم الهياكل المقترحة للبوابات المنطقية البالزمية ووظائفها بمساحة صغيرة جدًا‬ ‫أخيرا‪ ،‬تُعتبر األعمال المقترحة‬ ‫)‪(400nm × 400nm‬و)‪ ،(850nm × 400nm‬على التوالي‪.‬‬ ‫ً‬ ‫(بوابات المنطق البالزمية ووظائف المنطق التوافقي البالزمي) لبنات بناء أساسية في الدوائر‬ ‫المتكاملة الضوئية وأنظمة معالجة اإلشارات الضوئية‪ ،‬وتمهد طريقة لتحقيق دوائر شرائح‬ ‫ضوئية فائقة السرعة‪ ،‬أجهزة الكمبيوتر الضوئية كليا‪.‬‬

‫جمهورية العراق‬ ‫وزارة التعليم العالي والبحث العلمي‬ ‫جامعة بغداد‬ ‫كلية الهندسة‬ ‫قسم الهندسة الكهربائية‬

‫تصميم وتنفيذ كل البوابات المنطقية ضوئيا ً باستخدام أجزاء‬ ‫االطوال الموجية‬ ‫اطروحة‬ ‫مقدمة لقسم الهندسة الكهربائية‬ ‫كلية الهندسة – جامعة بغداد‬ ‫كجزء من متطلبات نيل درجة‬ ‫دكتوراه فلسفة في الهندسة الكهربائية‬ ‫(الكترونيك واتصاالت)‬

‫إعداد‬ ‫سيف حسن عبد النبي عباس‬ ‫بكالوريوس ‪ ،2012‬ماجستير ‪2015‬‬ ‫إشراف‬ ‫األستاذ المساعد الدكتور محمد ناظم عباس‬ ‫شاعبا‬

‫نيساا‬

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‫‪2019‬‬